The shareable_bits indicates which cache portions might be shared with
other agents (e.g., GPU, other I/O devices). On some platforms, all L3
cache ways are marked as potentially shared.

The L3_CAT test should fall back to using the full CBM mask when no
exclusive portion exists, since the test logic (writing different
schemata and measuring cache misses) still works. The shareable mask
is a hint about potential interference, not a hard exclusion.

Reported-by: Hongyu Ning <hongyu.ning@linux.intel.com>
Signed-off-by: Chen Yu <yu.c.chen@intel.com>
---
 tools/testing/selftests/resctrl/cat_test.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/selftests/resctrl/cat_test.c
index f00b622c1460..b6994ba4504b 100644
--- a/tools/testing/selftests/resctrl/cat_test.c
+++ b/tools/testing/selftests/resctrl/cat_test.c
@@ -248,7 +248,7 @@ static int cat_run_test(const struct resctrl_test *test, const struct user_param
 	/* Get the largest contiguous exclusive portion of the cache */
 	ret = get_mask_no_shareable(test->resource, &long_mask);
 	if (ret)
-		return ret;
+		long_mask = full_cache_mask;
 
 	/* Get L3/L2 cache size */
 	ret = get_cache_size(uparams->cpu, test->resource, &cache_total_size);
-- 
2.25.1