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[77.2.222.217]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4904526c926sm110773475e9.1.2026.05.22.14.20.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 22 May 2026 14:20:23 -0700 (PDT) From: Karl Mehltretter To: Russell King Cc: Abbott Liu , Linus Walleij , Ard Biesheuvel , Florian Fainelli , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Karl Mehltretter Subject: [PATCH] ARM: io: avoid KASAN instrumentation of raw halfword I/O Date: Fri, 22 May 2026 23:20:18 +0200 Message-Id: <20260522212018.25295-1-kmehltretter@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit 421015713b30 ("ARM: 9017/2: Enable KASan for ARM") made KASAN instrument ARM C memory accesses. For CPUs before ARMv6, __raw_readw() and __raw_writew() are C volatile halfword accesses, so KASAN instruments them as normal memory accesses. That is not valid for MMIO. On the QEMU versatilepb machine with an ARM926EJ-S CPU and CONFIG_KASAN=3Dy, PL011 probing traps while registering the UART: Unable to handle kernel paging request at virtual address bd23e207 PC is at __asan_store2+0x2c/0x9c LR is at pl011_register_port+0x4c/0x19c Keep the existing volatile halfword access, but move the pre-ARMv6 definitions into __no_kasan_or_inline functions so raw MMIO halfword accesses are not instrumented by KASAN. The ARMv6-and-newer inline assembly path is unchanged. Fixes: 421015713b30 ("ARM: 9017/2: Enable KASan for ARM") Cc: stable@vger.kernel.org # v5.11+ Assisted-by: Codex:gpt-5 Signed-off-by: Karl Mehltretter Reviewed-by: Linus Walleij --- arch/arm/include/asm/io.h | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index bae5edf348ef..e6bd9e79737c 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -56,8 +56,19 @@ void __raw_readsl(const volatile void __iomem *addr, voi= d *data, int longlen); * the bus. Rather than special-case the machine, just let the compiler * generate the access for CPUs prior to ARMv6. */ -#define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short= __force *)(a)) -#define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigne= d short __force *)(a) =3D (v))) +#define __raw_writew __raw_writew +static __no_kasan_or_inline void __raw_writew(u16 val, volatile void __iom= em *addr) +{ + __chk_io_ptr(addr); + *(volatile unsigned short __force *)addr =3D val; +} + +#define __raw_readw __raw_readw +static __no_kasan_or_inline u16 __raw_readw(const volatile void __iomem *a= ddr) +{ + __chk_io_ptr(addr); + return *(const volatile unsigned short __force *)addr; +} #else /* * When running under a hypervisor, we want to avoid I/O accesses with --=20 2.39.5 (Apple Git-154)