Commit 421015713b30 ("ARM: 9017/2: Enable KASan for ARM") made KASAN
instrument ARM C memory accesses. For CPUs before ARMv6, __raw_readw()
and __raw_writew() are C volatile halfword accesses, so KASAN instruments
them as normal memory accesses.

That is not valid for MMIO. On the QEMU versatilepb machine with an
ARM926EJ-S CPU and CONFIG_KASAN=y, PL011 probing traps while registering
the UART:

  Unable to handle kernel paging request at virtual address bd23e207
  PC is at __asan_store2+0x2c/0x9c
  LR is at pl011_register_port+0x4c/0x19c

Keep the existing volatile halfword access, but move the pre-ARMv6
definitions into __no_kasan_or_inline functions so raw MMIO halfword
accesses are not instrumented by KASAN. The ARMv6-and-newer inline
assembly path is unchanged.

Fixes: 421015713b30 ("ARM: 9017/2: Enable KASan for ARM")
Cc: stable@vger.kernel.org # v5.11+
Assisted-by: Codex:gpt-5
Signed-off-by: Karl Mehltretter <kmehltretter@gmail.com>
---
 arch/arm/include/asm/io.h | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index bae5edf348ef..e6bd9e79737c 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -56,8 +56,19 @@ void __raw_readsl(const volatile void __iomem *addr, void *data, int longlen);
  * the bus. Rather than special-case the machine, just let the compiler
  * generate the access for CPUs prior to ARMv6.
  */
-#define __raw_readw(a)         (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
-#define __raw_writew(v,a)      ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
+#define __raw_writew __raw_writew
+static __no_kasan_or_inline void __raw_writew(u16 val, volatile void __iomem *addr)
+{
+	__chk_io_ptr(addr);
+	*(volatile unsigned short __force *)addr = val;
+}
+
+#define __raw_readw __raw_readw
+static __no_kasan_or_inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+	__chk_io_ptr(addr);
+	return *(const volatile unsigned short __force *)addr;
+}
 #else
 /*
  * When running under a hypervisor, we want to avoid I/O accesses with
-- 
2.39.5 (Apple Git-154)

On Fri, May 22, 2026 at 11:20 PM Karl Mehltretter
<kmehltretter@gmail.com> wrote:

> Commit 421015713b30 ("ARM: 9017/2: Enable KASan for ARM") made KASAN
> instrument ARM C memory accesses. For CPUs before ARMv6, __raw_readw()
> and __raw_writew() are C volatile halfword accesses, so KASAN instruments
> them as normal memory accesses.
>
> That is not valid for MMIO. On the QEMU versatilepb machine with an
> ARM926EJ-S CPU and CONFIG_KASAN=y, PL011 probing traps while registering
> the UART:
>
>   Unable to handle kernel paging request at virtual address bd23e207
>   PC is at __asan_store2+0x2c/0x9c
>   LR is at pl011_register_port+0x4c/0x19c
>
> Keep the existing volatile halfword access, but move the pre-ARMv6
> definitions into __no_kasan_or_inline functions so raw MMIO halfword
> accesses are not instrumented by KASAN. The ARMv6-and-newer inline
> assembly path is unchanged.
>
> Fixes: 421015713b30 ("ARM: 9017/2: Enable KASan for ARM")
> Cc: stable@vger.kernel.org # v5.11+
> Assisted-by: Codex:gpt-5
> Signed-off-by: Karl Mehltretter <kmehltretter@gmail.com>

That makes sense.
Reviewed-by: Linus Walleij <linusw@kernel.org>

Please put this patch into Russell's patch tracker.

Yours,
Linus Walleij

On Sun, May 24, 2026 at 12:11:36AM +0100, Linus Walleij wrote:
> Please put this patch into Russell's patch tracker.

Done: https://www.armlinux.org.uk/developer/patches/viewpatch.php?id=9474/1

Thanks,
Karl