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Fri, 22 May 2026 13:33:25 -0700 (PDT) Received: from hu-nandam-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84164ac9c77sm3062251b3a.2.2026.05.22.13.33.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 May 2026 13:33:24 -0700 (PDT) From: Ajay Kumar Nandam To: Bjorn Andersson , Linus Walleij Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, mohammad.rafi.shaik@oss.qualcomm.com, ajay.nandam@oss.qualcomm.com, Konrad Dybcio Subject: [PATCH v6 1/2] pinctrl: qcom: lpass-lpi: Enable runtime PM hooks on LPASS LPI SoCs Date: Sat, 23 May 2026 02:03:03 +0530 Message-Id: <20260522203304.4065305-2-ajay.nandam@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260522203304.4065305-1-ajay.nandam@oss.qualcomm.com> References: <20260513140009.3841770-1-ajay.nandam@oss.qualcomm.com> <20260522203304.4065305-1-ajay.nandam@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=JN0LdcKb c=1 sm=1 tr=0 ts=6a10bd96 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=Rko4qIHHiJ4K03xOnZQA:9 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIyMDIwMyBTYWx0ZWRfXxAhUaXxISlym dsUkxYdEzqfp9ZvebgVfCIanyqoT1IiqcHC6u3xdcPyzJjBc3M2ktyBsDbs7QWa+xw9/xzI2bpM FQd5qSvDGqes1FjbtfpLbwGSLYfA7ufbHCTWV1n6PJVnMDtcjaz27vvtITRJrLM/6B7vtMJ1IvG J9B2UmvWwXeeo8AurW8MSR30p+wk51CPJMAUvEXtgRjJJz1y/GZWBGQ2HkQkSZv9YznlhGLOMFg K7zvSPrBvbXM4ZQ7yfQD9U1+UIFjC5mJgc+oehk13hhgTsThnEr7Jzj7yU9BWH4MU84PRCUJrTh jR2q+j6RK+JCaTYq0+uHmgAq+W1FtRF2VE3tzT6KWSoWrbsyzz6bqMSY+rGVs73YiLR9/uBqv54 xg9veCDtRc7Omb6lS2rL5n/S1cIg6EJ+KaI2oOwg6v2GdU0NtVaB6/ufvnXjNYyVxGfXkt6EgcX xbmYrZR+KUPua6mp5WQ== X-Proofpoint-GUID: 9Jd_lpA8wdv8QrF-1PMAHr8_LiuJ_Muf X-Proofpoint-ORIG-GUID: 9Jd_lpA8wdv8QrF-1PMAHr8_LiuJ_Muf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-22_05,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 impostorscore=0 phishscore=0 bulkscore=0 clxscore=1015 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605220203 Content-Type: text/plain; charset="utf-8" The LPASS LPI core conversion to PM clock framework relies on variant drivers wiring runtime PM callbacks. Hook up runtime PM callbacks for the LPASS LPI variant drivers touched in this patch so they are prepared for the shared core conversion. This commit is a preparatory NOP on its own, as runtime PM is still disabled on these devices until the following core conversion patch. This is a mechanical per-variant driver update that relies on the same generic PM clock flow (of_pm_clk_add_clks() + pm_clk_suspend/ pm_clk_resume()) and DT-provided clocks. Runtime behavior was validated on Kodiak (sc7280). Suggested-by: Konrad Dybcio Signed-off-by: Ajay Kumar Nandam --- .../pinctrl/qcom/pinctrl-milos-lpass-lpi.c | 7 +++++++ .../pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 19 +++++++++++++------ .../pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c | 15 +++++++++++---- .../pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c | 7 +++++++ .../pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c | 7 +++++++ .../pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c | 7 +++++++ .../pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c | 7 +++++++ .../pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c | 7 +++++++ .../pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 15 +++++++++++---- .../pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c | 15 +++++++++++---- .../pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c | 15 +++++++++++---- .../pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c | 15 +++++++++++---- 12 files changed, 110 insertions(+), 26 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c b/drivers/pinct= rl/qcom/pinctrl-milos-lpass-lpi.c index 3bf6fe0cf1bb..72b8ffd97860 100644 --- a/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -203,10 +205,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { .name =3D "qcom-milos-lpass-lpi-pinctrl", .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sc7280-lpass-lpi.c index 750f410311a8..a61df10d46cb 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -129,20 +131,25 @@ static const struct lpi_pinctrl_variant_data sc7280_l= pi_data =3D { =20 static const struct of_device_id lpi_pinctrl_of_match[] =3D { { - .compatible =3D "qcom,sc7280-lpass-lpi-pinctrl", - .data =3D &sc7280_lpi_data, + .compatible =3D "qcom,sc7280-lpass-lpi-pinctrl", + .data =3D &sc7280_lpi_data, }, { - .compatible =3D "qcom,sm8350-lpass-lpi-pinctrl", - .data =3D &sc7280_lpi_data, + .compatible =3D "qcom,sm8350-lpass-lpi-pinctrl", + .data =3D &sc7280_lpi_data, }, { } }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { - .name =3D "qcom-sc7280-lpass-lpi-pinctrl", - .of_match_table =3D lpi_pinctrl_of_match, + .name =3D "qcom-sc7280-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c b/drivers/pi= nctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c index 0e839b6aaaf4..27c47710365e 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -166,17 +168,22 @@ static const struct lpi_pinctrl_variant_data sc8280xp= _lpi_data =3D { =20 static const struct of_device_id lpi_pinctrl_of_match[] =3D { { - .compatible =3D "qcom,sc8280xp-lpass-lpi-pinctrl", - .data =3D &sc8280xp_lpi_data, + .compatible =3D "qcom,sc8280xp-lpass-lpi-pinctrl", + .data =3D &sc8280xp_lpi_data, }, { } }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { - .name =3D "qcom-sc8280xp-lpass-lpi-pinctrl", - .of_match_table =3D lpi_pinctrl_of_match, + .name =3D "qcom-sc8280xp-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sdm660-lpass-lpi.c index 65411abfbfac..7b5aacaae7d7 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include #include =20 #include "pinctrl-lpass-lpi.h" @@ -145,10 +147,15 @@ static const struct of_device_id sdm660_lpi_pinctrl_o= f_match[] =3D { }; MODULE_DEVICE_TABLE(of, sdm660_lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver sdm660_lpi_pinctrl_driver =3D { .driver =3D { .name =3D "qcom-sdm660-lpass-lpi-pinctrl", .of_match_table =3D sdm660_lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sdm670-lpass-lpi.c index 858146c408d0..0a31f7ad2e0d 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include =20 #include "pinctrl-lpass-lpi.h" @@ -151,10 +153,15 @@ static const struct of_device_id sdm670_lpi_pinctrl_o= f_match[] =3D { }; MODULE_DEVICE_TABLE(of, sdm670_lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver sdm670_lpi_pinctrl_driver =3D { .driver =3D { .name =3D "qcom-sdm670-lpass-lpi-pinctrl", .of_match_table =3D sdm670_lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm4250-lpass-lpi.c index c0e178be9cfc..75bafa62426a 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -221,10 +223,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { .name =3D "qcom-sm4250-lpass-lpi-pinctrl", .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm6115-lpass-lpi.c index b7d9186861a2..05435ea6e17a 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -141,10 +143,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { .name =3D "qcom-sm6115-lpass-lpi-pinctrl", .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm6350-lpass-lpi.c index 4d06abcfedfd..946b23084304 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -135,10 +137,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { .name =3D "qcom-sm6350-lpass-lpi-pinctrl", .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm8250-lpass-lpi.c index c27452eece3e..454de788be21 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -127,17 +129,22 @@ static const struct lpi_pinctrl_variant_data sm8250_l= pi_data =3D { =20 static const struct of_device_id lpi_pinctrl_of_match[] =3D { { - .compatible =3D "qcom,sm8250-lpass-lpi-pinctrl", - .data =3D &sm8250_lpi_data, + .compatible =3D "qcom,sm8250-lpass-lpi-pinctrl", + .data =3D &sm8250_lpi_data, }, { } }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { - .name =3D "qcom-sm8250-lpass-lpi-pinctrl", - .of_match_table =3D lpi_pinctrl_of_match, + .name =3D "qcom-sm8250-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm8450-lpass-lpi.c index 439f6541622e..834eee8dcce9 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -195,17 +197,22 @@ static const struct lpi_pinctrl_variant_data sm8450_l= pi_data =3D { =20 static const struct of_device_id lpi_pinctrl_of_match[] =3D { { - .compatible =3D "qcom,sm8450-lpass-lpi-pinctrl", - .data =3D &sm8450_lpi_data, + .compatible =3D "qcom,sm8450-lpass-lpi-pinctrl", + .data =3D &sm8450_lpi_data, }, { } }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { - .name =3D "qcom-sm8450-lpass-lpi-pinctrl", - .of_match_table =3D lpi_pinctrl_of_match, + .name =3D "qcom-sm8450-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm8550-lpass-lpi.c index 73065919c8c2..875e04e5d2b9 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -203,17 +205,22 @@ static const struct lpi_pinctrl_variant_data sm8550_l= pi_data =3D { =20 static const struct of_device_id lpi_pinctrl_of_match[] =3D { { - .compatible =3D "qcom,sm8550-lpass-lpi-pinctrl", - .data =3D &sm8550_lpi_data, + .compatible =3D "qcom,sm8550-lpass-lpi-pinctrl", + .data =3D &sm8550_lpi_data, }, { } }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { - .name =3D "qcom-sm8550-lpass-lpi-pinctrl", - .of_match_table =3D lpi_pinctrl_of_match, + .name =3D "qcom-sm8550-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm8650-lpass-lpi.c index f9fcedf5a65d..bc7889c993d0 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -210,17 +212,22 @@ static const struct lpi_pinctrl_variant_data sm8650_l= pi_data =3D { =20 static const struct of_device_id lpi_pinctrl_of_match[] =3D { { - .compatible =3D "qcom,sm8650-lpass-lpi-pinctrl", - .data =3D &sm8650_lpi_data, + .compatible =3D "qcom,sm8650-lpass-lpi-pinctrl", + .data =3D &sm8650_lpi_data, }, { } }; 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Fri, 22 May 2026 13:33:28 -0700 (PDT) X-Received: by 2002:a05:6a00:1255:b0:82f:3a1e:5618 with SMTP id d2e1a72fcca58-8415f1a6201mr5358955b3a.22.1779482008436; Fri, 22 May 2026 13:33:28 -0700 (PDT) Received: from hu-nandam-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84164ac9c77sm3062251b3a.2.2026.05.22.13.33.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 May 2026 13:33:28 -0700 (PDT) From: Ajay Kumar Nandam To: Bjorn Andersson , Linus Walleij Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, mohammad.rafi.shaik@oss.qualcomm.com, ajay.nandam@oss.qualcomm.com, Konrad Dybcio Subject: [PATCH v6 2/2] pinctrl: qcom: lpass-lpi: Switch to PM clock framework for runtime PM Date: Sat, 23 May 2026 02:03:04 +0530 Message-Id: <20260522203304.4065305-3-ajay.nandam@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260522203304.4065305-1-ajay.nandam@oss.qualcomm.com> References: <20260513140009.3841770-1-ajay.nandam@oss.qualcomm.com> <20260522203304.4065305-1-ajay.nandam@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=JN0LdcKb c=1 sm=1 tr=0 ts=6a10bd99 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=gi8XeulvwEclXWRguk8A:9 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIyMDIwMyBTYWx0ZWRfX3PXqx9UODGNN K/Hi1BckCx88cFgCfENpO9r3j37VzFAvcUf+AeOJdZtxipegM/EMXahg/xLW6dTmQJXKfGk+bXT NzyPxBKdq+6bi+TGkOyx1oOGAqtyb5+kZ0rRcSkIGWkelGBBsaQFAUpTfdg+LY8MOVSrqajeRnU gDfUHA2VRT5B+h0lZoaIdRFJybCiYvIrYP70zpsmS6X3XdnR9BFpCigaMpy3D7ef9Drs8oqX0// XeNhbd7Ljqb0hPQy6AQyN87lDeFA5hNoev+beKB31/RqqZpbMKpPC8AN9ytFuxmxiLvwKpo83fE ZphuQQ8CjHB5KKqFBxEbdWz709YAzp02U1N2VeiAgzt8l6KjrdIrzR3YomY6F0gDibe1TuWlg96 QgZfIiDhhlvE9fgNFRZmLnBUTIi/GuuqcQ7APgB1VNUcpAxUI+LtnnIWWpzSelScG2GlbUAW3+o MGKSSZap/RflUrkHBAw== X-Proofpoint-GUID: Ysd2cG9xEYaWqY1SbggLxovj8ug48Ul7 X-Proofpoint-ORIG-GUID: Ysd2cG9xEYaWqY1SbggLxovj8ug48Ul7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-22_05,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 impostorscore=0 phishscore=0 bulkscore=0 clxscore=1015 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605220203 Content-Type: text/plain; charset="utf-8" Convert the LPASS LPI pinctrl driver to use the PM clock framework for runtime power management. This allows the LPASS LPI pinctrl driver to drop clock votes when idle, improves power efficiency on platforms using LPASS LPI island mode, and aligns the driver with common runtime PM patterns used across Qualcomm LPASS subsystems. Guard GPIO register read/write helpers and slew-rate register programming with synchronous runtime PM calls so the device is active during MMIO operations whenever autosuspend is enabled. Make PINCTRL_LPASS_LPI depend on PM_CLK, since this patch introduces direct PM clock API use in the shared core. Suggested-by: Konrad Dybcio Signed-off-by: Ajay Kumar Nandam --- drivers/pinctrl/qcom/Kconfig | 1 + drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 144 +++++++++++++++-------- 2 files changed, 99 insertions(+), 46 deletions(-) diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index a09e840a01c6..18db350222b9 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -55,6 +55,7 @@ config PINCTRL_LPASS_LPI select PINCONF select GENERIC_PINCONF select GENERIC_PINCTRL_GROUPS + depends on PM_CLK depends on GPIOLIB help This is the pinctrl, pinmux, pinconf and gpiolib driver for the diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.c index 15ced5027579..4d758fd117c4 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -11,10 +11,13 @@ #include #include #include +#include =20 #include #include #include +#include +#include =20 #include "../pinctrl-utils.h" =20 @@ -22,7 +25,6 @@ =20 #define MAX_NR_GPIO 32 #define GPIO_FUNC 0 -#define MAX_LPI_NUM_CLKS 2 =20 struct lpi_pinctrl { struct device *dev; @@ -31,15 +33,14 @@ struct lpi_pinctrl { struct pinctrl_desc desc; char __iomem *tlmm_base; char __iomem *slew_base; - struct clk_bulk_data clks[MAX_LPI_NUM_CLKS]; /* Protects from concurrent register updates */ struct mutex lock; DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO); const struct lpi_pinctrl_variant_data *data; }; =20 -static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, - unsigned int addr) +static void __iomem *lpi_gpio_reg(struct lpi_pinctrl *state, + unsigned int pin, unsigned int addr) { u32 pin_offset; =20 @@ -48,22 +49,48 @@ static int lpi_gpio_read(struct lpi_pinctrl *state, uns= igned int pin, else pin_offset =3D LPI_TLMM_REG_OFFSET * pin; =20 - return ioread32(state->tlmm_base + pin_offset + addr); + return state->tlmm_base + pin_offset + addr; +} + +static void __lpi_gpio_read(struct lpi_pinctrl *state, + unsigned int pin, unsigned int addr, u32 *val) +{ + *val =3D ioread32(lpi_gpio_reg(state, pin, addr)); +} + +static void __lpi_gpio_write(struct lpi_pinctrl *state, + unsigned int pin, unsigned int addr, + unsigned int val) +{ + iowrite32(val, lpi_gpio_reg(state, pin, addr)); +} + +static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, + unsigned int addr, u32 *val) +{ + int ret; + + ret =3D pm_runtime_resume_and_get(state->dev); + if (ret < 0) + return ret; + + __lpi_gpio_read(state, pin, addr, val); + + return pm_runtime_put_autosuspend(state->dev); } =20 static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, unsigned int addr, unsigned int val) { - u32 pin_offset; + int ret; =20 - if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET) - pin_offset =3D state->data->groups[pin].pin_offset; - else - pin_offset =3D LPI_TLMM_REG_OFFSET * pin; + ret =3D pm_runtime_resume_and_get(state->dev); + if (ret < 0) + return ret; =20 - iowrite32(val, state->tlmm_base + pin_offset + addr); + __lpi_gpio_write(state, pin, addr, val); =20 - return 0; + return pm_runtime_put_autosuspend(state->dev); } =20 static const struct pinctrl_ops lpi_gpio_pinctrl_ops =3D { @@ -107,8 +134,8 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev= , unsigned int function, { struct lpi_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctldev); const struct lpi_pingroup *g =3D &pctrl->data->groups[group]; - u32 val; - int i, pin =3D g->pin; + u32 io_val, val; + int i, pin =3D g->pin, ret; =20 for (i =3D 0; i < g->nfuncs; i++) { if (g->funcs[i] =3D=3D function) @@ -118,8 +145,12 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctlde= v, unsigned int function, if (WARN_ON(i =3D=3D g->nfuncs)) return -EINVAL; =20 - mutex_lock(&pctrl->lock); - val =3D lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG); + ret =3D pm_runtime_resume_and_get(pctrl->dev); + if (ret < 0) + return ret; + + guard(mutex)(&pctrl->lock); + __lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG, &val); =20 /* * If this is the first time muxing to GPIO and the direction is @@ -129,24 +160,25 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctld= ev, unsigned int function, */ if (i =3D=3D GPIO_FUNC && (val & LPI_GPIO_OE_MASK) && !test_and_set_bit(group, pctrl->ever_gpio)) { - u32 io_val =3D lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG); + __lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG, &io_val); =20 if (io_val & LPI_GPIO_VALUE_IN_MASK) { if (!(io_val & LPI_GPIO_VALUE_OUT_MASK)) - lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, - io_val | LPI_GPIO_VALUE_OUT_MASK); + __lpi_gpio_write(pctrl, group, + LPI_GPIO_VALUE_REG, + io_val | LPI_GPIO_VALUE_OUT_MASK); } else { if (io_val & LPI_GPIO_VALUE_OUT_MASK) - lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, - io_val & ~LPI_GPIO_VALUE_OUT_MASK); + __lpi_gpio_write(pctrl, group, + LPI_GPIO_VALUE_REG, + io_val & ~LPI_GPIO_VALUE_OUT_MASK); } } =20 u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK); - lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val); - mutex_unlock(&pctrl->lock); + __lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val); =20 - return 0; + return pm_runtime_put_autosuspend(pctrl->dev); } =20 static const struct pinmux_ops lpi_gpio_pinmux_ops =3D { @@ -162,11 +194,15 @@ static int lpi_config_get(struct pinctrl_dev *pctldev, unsigned int param =3D pinconf_to_config_param(*config); struct lpi_pinctrl *state =3D dev_get_drvdata(pctldev->dev); unsigned int arg =3D 0; + u32 ctl_reg; int is_out; int pull; - u32 ctl_reg; + int ret; + + ret =3D lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG, &ctl_reg); + if (ret) + return ret; =20 - ctl_reg =3D lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG); is_out =3D ctl_reg & LPI_GPIO_OE_MASK; pull =3D FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg); =20 @@ -197,6 +233,7 @@ static int lpi_config_get(struct pinctrl_dev *pctldev, } =20 *config =3D pinconf_to_config_packed(param, arg); + return 0; } =20 @@ -206,7 +243,7 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl = *pctrl, { unsigned long sval; void __iomem *reg; - int slew_offset; + int slew_offset, ret; =20 if (slew > LPI_SLEW_RATE_MAX) { dev_err(pctrl->dev, "invalid slew rate %u for pin: %d\n", @@ -225,6 +262,10 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl= *pctrl, else reg =3D pctrl->slew_base + LPI_SLEW_RATE_CTL_REG; =20 + ret =3D pm_runtime_resume_and_get(pctrl->dev); + if (ret < 0) + return ret; + mutex_lock(&pctrl->lock); =20 sval =3D ioread32(reg); @@ -234,7 +275,7 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl = *pctrl, =20 mutex_unlock(&pctrl->lock); =20 - return 0; + return pm_runtime_put_autosuspend(pctrl->dev); } =20 static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, @@ -244,8 +285,8 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, = unsigned int group, unsigned int param, arg, pullup =3D LPI_GPIO_BIAS_DISABLE, strength =3D 2; bool value, output_enabled =3D false; const struct lpi_pingroup *g; - int i, ret; u32 val; + int i, ret; =20 g =3D &pctrl->data->groups[group]; for (i =3D 0; i < nconfs; i++) { @@ -289,23 +330,26 @@ static int lpi_config_set(struct pinctrl_dev *pctldev= , unsigned int group, * As per Hardware Programming Guide, when configuring pin as output, * set the pin value before setting output-enable (OE). */ + ret =3D pm_runtime_resume_and_get(pctrl->dev); + if (ret < 0) + return ret; + + guard(mutex)(&pctrl->lock); if (output_enabled) { val =3D u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK); - lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val); + __lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val); } =20 - mutex_lock(&pctrl->lock); - val =3D lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG); + __lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG, &val); =20 u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK); u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength), LPI_GPIO_OUT_STRENGTH_MASK); u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK); =20 - lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val); - mutex_unlock(&pctrl->lock); + __lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val); =20 - return 0; + return pm_runtime_put_autosuspend(pctrl->dev); } =20 static const struct pinconf_ops lpi_gpio_pinconf_ops =3D { @@ -354,9 +398,14 @@ static int lpi_gpio_direction_output(struct gpio_chip = *chip, static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin) { struct lpi_pinctrl *state =3D gpiochip_get_data(chip); + u32 val; + int ret; + + ret =3D lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG, &val); + if (ret) + return ret; =20 - return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) & - LPI_GPIO_VALUE_IN_MASK; + return val & LPI_GPIO_VALUE_IN_MASK; } =20 static int lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int valu= e) @@ -399,7 +448,9 @@ static void lpi_gpio_dbg_show_one(struct seq_file *s, =20 pctldev =3D pctldev ? : state->ctrl; pindesc =3D pctldev->desc->pins[offset]; - ctl_reg =3D lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG); + if (lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG, &ctl_reg)) + return; + is_out =3D ctl_reg & LPI_GPIO_OE_MASK; =20 func =3D FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg); @@ -482,9 +533,6 @@ int lpi_pinctrl_probe(struct platform_device *pdev) pctrl->data =3D data; pctrl->dev =3D &pdev->dev; =20 - pctrl->clks[0].id =3D "core"; - pctrl->clks[1].id =3D "audio"; - pctrl->tlmm_base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pctrl->tlmm_base)) return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base), @@ -497,13 +545,19 @@ int lpi_pinctrl_probe(struct platform_device *pdev) "Slew resource not provided\n"); } =20 - ret =3D devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks); + ret =3D devm_pm_clk_create(dev); if (ret) return ret; =20 - ret =3D clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks); + ret =3D of_pm_clk_add_clks(dev); + if (ret < 0 && ret !=3D -ENODEV) + return ret; + + pm_runtime_set_autosuspend_delay(dev, 100); + pm_runtime_use_autosuspend(dev); + ret =3D devm_pm_runtime_enable(dev); if (ret) - return dev_err_probe(dev, ret, "Can't enable clocks\n"); + return ret; =20 pctrl->desc.pctlops =3D &lpi_gpio_pinctrl_ops; pctrl->desc.pmxops =3D &lpi_gpio_pinmux_ops; @@ -542,7 +596,6 @@ int lpi_pinctrl_probe(struct platform_device *pdev) =20 err_pinctrl: mutex_destroy(&pctrl->lock); - clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); =20 return ret; } @@ -554,7 +607,6 @@ void lpi_pinctrl_remove(struct platform_device *pdev) int i; =20 mutex_destroy(&pctrl->lock); - clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); =20 for (i =3D 0; i < pctrl->data->npins; i++) pinctrl_generic_remove_group(pctrl->ctrl, i); --=20 2.34.1