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charset="utf-8" Axelera AI is an EU-based provider of AIPUs for edge AI inference. Link: https://axelera.ai/ Signed-off-by: Patrick Barsanti --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 28784d66ae7b..595ad9423ece 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -217,6 +217,8 @@ patternProperties: description: Avnet, Inc. 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Fri, 22 May 2026 10:49:31 -0700 (PDT) From: Patrick Barsanti To: devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, heiko@sntech.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, dario.binacchi@amarulasolutions.com, Patrick Barsanti Subject: [PATCH 2/3] dt-bindings: arm: rockchip: Add Axelera AI Metis Compute Board Date: Fri, 22 May 2026 19:49:17 +0200 Message-ID: <20260522174918.61523-3-patrick.barsanti@amarulasolutions.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260522174918.61523-1-patrick.barsanti@amarulasolutions.com> References: <20260522174918.61523-1-patrick.barsanti@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Axelera AI Metis Compute Board is a SBC based on the Rockchip RK3588 SoC. Specification: - Rockchip RK3588 - 16GB LPDDR4 - Axelera AI Metis AIPU, 4GB/16GB LPDDR4X - 64GB eMMC - uSD slot - 2x SATA ports - 2x Gigabit LAN - 1x M.2 E key - 1x M.2 B key - 1x HDMI2.0 - 1x USB-C with DP - 4x USB3.1 Link: https://axelera.ai/evaluation-systems/metis-compute-board Signed-off-by: Patrick Barsanti --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 1a9dde18626d..a784c9eddc50 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -107,6 +107,11 @@ properties: - asus,rk3566-tinker-board-3s - const: rockchip,rk3566 =20 + - description: Axelera AI Metis Compute Board + items: + - const: axelera,metis-sbc + - const: rockchip,rk3588 + - description: Beelink A1 items: - const: azw,beelink-a1 --=20 2.53.0 From nobody Sun May 24 19:33:20 2026 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EB2A368958 for ; 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Fri, 22 May 2026 10:49:35 -0700 (PDT) Received: from thinkpat.amarulasolutions.com ([94.162.24.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bddc5eca6f9sm74302366b.38.2026.05.22.10.49.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 May 2026 10:49:35 -0700 (PDT) From: Patrick Barsanti To: devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, heiko@sntech.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, dario.binacchi@amarulasolutions.com, Patrick Barsanti Subject: [PATCH 3/3] arm64: dts: rockchip: Add Axelera AI metis-sbc Date: Fri, 22 May 2026 19:49:18 +0200 Message-ID: <20260522174918.61523-4-patrick.barsanti@amarulasolutions.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260522174918.61523-1-patrick.barsanti@amarulasolutions.com> References: <20260522174918.61523-1-patrick.barsanti@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add minimal device tree for the Axelera AI Metis Compute Board (rk3588-metis-sbc). It offers efficient AI compute for multi-stream computer vision and GenAI applications in a compact design. It features a quad-core Axelera AI Metis AIPU and an RK3588 SoC processor. This basic version of the dts supports: - Console - eMMC - HDMI - 4x USB-A - 2x Gigabit Ethernet - RTC - Enumeration of on-board Axelera Metis AIPU Link: https://axelera.ai/evaluation-systems/metis-compute-board Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi Signed-off-by: Patrick Barsanti --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588-metis-sbc.dts | 840 ++++++++++++++++++ 2 files changed, 841 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-metis-sbc.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index cb55c6b70d0e..8241f6ec2606 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -192,6 +192,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-h96-max-v58.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-jaguar.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-jaguar-ethernet-switch.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-jaguar-pre-ict-tester.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-metis-sbc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-mnt-reform2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-nanopc-t6.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-nanopc-t6-lts.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-metis-sbc.dts b/arch/arm64= /boot/dts/rockchip/rk3588-metis-sbc.dts new file mode 100644 index 000000000000..56d734f9f25b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-metis-sbc.dts @@ -0,0 +1,840 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include +#include "rk3588.dtsi" + +/ { + model =3D "Axelera AI Metis Compute Board"; + compatible =3D "axelera,metis-sbc", "rockchip,rk3588"; + + aliases { + ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; + mmc0 =3D &sdhci; + }; + + chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + hdmi0-con { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint =3D <&hdmi0_out_con>; + }; + }; + }; + + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "pcie20_avdd0v85"; + vin-supply =3D <&vdda_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "pcie20_avdd1v8"; + vin-supply =3D <&vcca_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "pcie30_avdd0v75"; + vin-supply =3D <&hdmi_vdda0v85_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "pcie30_avdd1v8"; + vin-supply =3D <&vcca_1v8_s0>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; /* TYPEC5V_PWREN */ + pinctrl-0 =3D <&typec5v_pwren>; + pinctrl-names =3D "default"; + regulator-name =3D "usbc_ss_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_sus>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-name =3D "vcc_1v1_nldo_s3"; + vin-supply =3D <&vcc4v0_sys>; + }; + + vcc_1v8_pcie: vcc-1v8-pcie { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; /* PCIE30_PWREN_H */ + pinctrl-0 =3D <&pcie30_pwren_h>; + pinctrl-names =3D "default"; + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_pcie"; + startup-delay-us =3D <50000>; + vin-supply =3D <&vcc_1v8_s3>; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0 { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; /* SDMMC_PWREN */ + pinctrl-0 =3D <&sdmmc_pwren>; + pinctrl-names =3D "default"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vsd_3v3"; + startup-delay-us =3D <1000000>; + vin-supply =3D <&vcc_3v3_s3>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + regulator-name =3D "12vsus"; + }; + + vcc3v3_hubreset: vcc3v3-hubreset { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; /* USB_HUB_RST_N */ + pinctrl-0 =3D <&usb_hub_rst_n>; + pinctrl-names =3D "default"; + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vcc3v3_hubreset"; + vin-supply =3D <&vcc_3v3_s3>; + }; + + vcc3v3_m2: vcc3v3-m2 { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; /* PCIE_PWREN_H */ + pinctrl-0 =3D <&pcie_pwren_h>; + pinctrl-names =3D "default"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "3v_m2"; + vin-supply =3D <&vcc3v3_sus>; + }; + + vcc3v3_sus: vcc3v3-sus { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "3vsus"; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc4v0_sys: vcc4v0-sys { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <4000000>; + regulator-max-microvolt =3D <4000000>; + regulator-name =3D "vcc4v0_sys"; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* USB_HOST_PWREN */ + pinctrl-0 =3D <&usb_host_pwren>; + pinctrl-names =3D "default"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-name =3D "vcc5v0_host"; + vin-supply =3D <&vcc5v0_sus>; + }; + + vcc5v0_sus: vcc5v0-sus { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-name =3D "5vsus"; + vin-supply =3D <&vcc12v_dcin>; + }; +}; + +&cpu_b0 { + cpu-supply =3D <&vdd_cpu_big0_s0>; + mem-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply =3D <&vdd_cpu_big0_s0>; + mem-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply =3D <&vdd_cpu_big1_s0>; + mem-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply =3D <&vdd_cpu_big1_s0>; + mem-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply =3D <&vdd_cpu_lit_s0>; + mem-supply =3D <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l1 { + cpu-supply =3D <&vdd_cpu_lit_s0>; + mem-supply =3D <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l2 { + cpu-supply =3D <&vdd_cpu_lit_s0>; + mem-supply =3D <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l3 { + cpu-supply =3D <&vdd_cpu_lit_s0>; + mem-supply =3D <&vdd_cpu_lit_mem_s0>; +}; + +&gmac0 { + clock_in_out =3D "output"; + phy-handle =3D <&rgmii_phy0>; + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode =3D "rgmii-rxid"; + pinctrl-0 =3D <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + pinctrl-names =3D "default"; + tx_delay =3D <0x44>; + snps,reset-gpio =3D <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; /* GMAC0_RST_N */ + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us =3D <0 20000 100000>; + status =3D "okay"; +}; + +&gmac1 { + clock_in_out =3D "output"; + phy-handle =3D <&rgmii_phy1>; + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode =3D "rgmii-rxid"; + pinctrl-0 =3D <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + pinctrl-names =3D "default"; + tx_delay =3D <0x43>; + snps,reset-gpio =3D <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; /* GMAC1_RST_N */ + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us =3D <0 20000 100000>; + status =3D "okay"; +}; + +&gpu { + mali-supply =3D <&vdd_gpu_s0>; + status =3D "okay"; +}; + +&hdmi0 { + pinctrl-0 =3D <&hdmim0_tx0_cec &hdmim0_tx0_hpd_sbc &hdmim0_tx0_scl &hdmim= 0_tx0_sda>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint =3D <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint =3D <&hdmi0_con_in>; + }; +}; + +&hdmi0_sound { + status =3D "okay"; +}; + +&hdptxphy0 { + status =3D "okay"; +}; + +&i2c0 { + pinctrl-0 =3D <&i2c0m2_xfer>; + pinctrl-names =3D "default"; + status =3D "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + reg =3D <0x42>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-name =3D "vdd_cpu_big0_s0"; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc4v0_sys>; + fcs,suspend-voltage-selector =3D <1>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible =3D "rockchip,rk8603", "rockchip,rk8602"; + reg =3D <0x43>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-name =3D "vdd_cpu_big1_s0"; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc4v0_sys>; + fcs,suspend-voltage-selector =3D <1>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + pinctrl-0 =3D <&i2c1m2_xfer>; + pinctrl-names =3D "default"; + status =3D "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + reg =3D <0x42>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-name =3D "vdd_npu_s0"; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc4v0_sys>; + fcs,suspend-voltage-selector =3D <1>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + status =3D "okay"; + + rtc: rtc@68 { + compatible =3D "ti,bq32000"; + reg =3D <0x68>; + }; +}; + +&i2s5_8ch { + status =3D "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@3 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x3>; + }; +}; + +&pcie30phy { + status =3D "okay"; +}; + +&pcie3x4 { + pinctrl-0 =3D <&pciex4_perst_n>; + pinctrl-names =3D "default"; + reset-gpios =3D <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; /* PCIEX4_PERST_N */ + /* + * Add specific mapping required by the onboard + * Axelera Metis AIPU to function. + */ + ranges =3D <0x81000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x100000 + 0x82000000 0x0 0x40000000 0x9 0x00000000 0x0 0x20000000 + 0xc3000000 0x0 0x60000000 0x9 0x20000000 0x0 0x20000000>; + /* + * Set to 1v8 because the electronics on the pcie3x4 slot + * do not receive 3v3 supply at all, but vpcie3v3-supply + * must be specified. + */ + vpcie3v3-supply =3D <&vcc_1v8_pcie>; + status =3D "okay"; +}; + +&pinctrl { + hdmi { + hdmim0_tx0_hpd_sbc: hdmim0-tx0-hpd-sbc { + rockchip,pins =3D <3 RK_PD4 3 &pcfg_pull_none>; + }; + }; + + pci { + pcie_pwren_h: pcie-pwren-h { + rockchip,pins =3D <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30_pwren_h: pcie30-pwren-h { + rockchip,pins =3D <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pciex1_clkreq_n: pciex1-clkreq-n { + rockchip,pins =3D <4 RK_PA0 4 &pcfg_pull_down>; + }; + + pcie_wake_n: pcie-wake-n { /* M.2_TYPE_B1 wake irq */ + rockchip,pins =3D <4 RK_PA1 4 &pcfg_pull_down>; + }; + + pciex1_perst_n: pciex1-perst-n { /* pcie reset */ + rockchip,pins =3D <4 RK_PA2 4 &pcfg_pull_none>; + }; + + pciex4_perst_n: pciex4-perst-n { /* pcie3x4 reset */ + rockchip,pins =3D <4 RK_PB6 4 &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_pwren: sdmmc-pwren { + rockchip,pins =3D <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + usb_hub_rst_n: usb-hub-rst-n { + rockchip,pins =3D <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_host_pwren: usb-host-pwren { + rockchip,pins =3D <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + cc_int_n: cc-int-n { + rockchip,pins =3D <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins =3D <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply =3D <&vcca_1v8_s0>; + status =3D "okay"; +}; + +/* eMMC */ +&sdhci { + bus-width =3D <8>; + max-frequency =3D <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sd; + no-sdio; + non-removable; + full-pwr-cycle-in-suspend; + status =3D "okay"; +}; + +&spi2 { + assigned-clock-rates =3D <200000000>; + assigned-clocks =3D <&cru CLK_SPI2>; + num-cs =3D <1>; + pinctrl-0 =3D <&spi2m2_cs0 &spi2m2_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + pmic@0 { + compatible =3D "rockchip,rk806"; + reg =3D <0x0>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; /* PMIC_INT_L */ + spi-max-frequency =3D <1000000>; + system-power-controller; + vcc1-supply =3D <&vcc4v0_sys>; + vcc2-supply =3D <&vcc4v0_sys>; + vcc3-supply =3D <&vcc4v0_sys>; + vcc4-supply =3D <&vcc4v0_sys>; + vcc5-supply =3D <&vcc4v0_sys>; + vcc6-supply =3D <&vcc4v0_sys>; + vcc7-supply =3D <&vcc4v0_sys>; + vcc8-supply =3D <&vcc4v0_sys>; + vcc9-supply =3D <&vcc4v0_sys>; + vcc10-supply =3D <&vcc4v0_sys>; + vcc11-supply =3D <&vcc_2v0_pldo_s3>; + vcc12-supply =3D <&vcc4v0_sys>; + vcc13-supply =3D <&vcc_1v1_nldo_s3>; + vcc14-supply =3D <&vcc_1v1_nldo_s3>; + vcca-supply =3D <&vcc4v0_sys>; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-enable-ramp-delay =3D <400>; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-name =3D "vdd_gpu_s0"; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-name =3D "vdd_cpu_lit_s0"; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <800000>; + regulator-name =3D "vdd_log_s0"; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-name =3D "vdd_vdenc_s0"; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdd_ddr_s0"; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2000000>; + regulator-max-microvolt =3D <2000000>; + regulator-name =3D "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-name =3D "vdda_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcca_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca1v8_pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdda_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + hdmi_vdda0v85_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <837500>; + regulator-max-microvolt =3D <837500>; + regulator-name =3D "hdmi_vdda0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdda_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&u2phy1 { + status =3D "okay"; +}; + +&u2phy1_otg { + phy-supply =3D <&vcc5v0_host>; + status =3D "okay"; +}; + +&uart2 { + pinctrl-0 =3D <&uart2m0_xfer>; + status =3D "okay"; +}; + +&usb_host1_xhci { + dr_mode =3D "host"; + status =3D "okay"; +}; + +&usbdp_phy1 { + phy-supply =3D <&vcc3v3_hubreset>; + status =3D "okay"; +}; + +&vop { + status =3D "okay"; +}; + +&vop_mmu { + status =3D "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg =3D ; + remote-endpoint =3D <&hdmi0_in_vp0>; + }; +}; --=20 2.53.0