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charset="utf-8" Outside of a3xx, this was never really used. And it low-key gets in the way of the new perfcntr support (or at least it is confusing to have two things called "perf"). So lets remove it. This drops the "perf" debugfs file. But these days, nvtop is a better option. (Plus perfetto for newer gens.) Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov Reviewed-by: Anna Maniscalco Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/Makefile | 1 - drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 7 - drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 16 -- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 3 - drivers/gpu/drm/msm/msm_debugfs.c | 6 - drivers/gpu/drm/msm/msm_drv.c | 1 - drivers/gpu/drm/msm/msm_drv.h | 5 - drivers/gpu/drm/msm/msm_gpu.c | 107 ------------ drivers/gpu/drm/msm/msm_gpu.h | 31 ---- drivers/gpu/drm/msm/msm_perf.c | 235 -------------------------- 10 files changed, 412 deletions(-) delete mode 100644 drivers/gpu/drm/msm/msm_perf.c diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index ba45e99be05b..ce00cfb0a875 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -122,7 +122,6 @@ msm-y +=3D \ msm_gpu_devfreq.o \ msm_io_utils.o \ msm_iommu.o \ - msm_perf.o \ msm_rd.o \ msm_ringbuffer.o \ msm_submitqueue.o \ diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a2xx_gpu.c index d5a5fa9e2cf8..df4cded9143f 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c @@ -489,10 +489,6 @@ static u32 a2xx_get_rptr(struct msm_gpu *gpu, struct m= sm_ringbuffer *ring) return ring->memptrs->rptr; } =20 -static const struct msm_gpu_perfcntr perfcntrs[] =3D { -/* TODO */ -}; - static struct msm_gpu *a2xx_gpu_init(struct drm_device *dev) { struct a2xx_gpu *a2xx_gpu =3D NULL; @@ -518,9 +514,6 @@ static struct msm_gpu *a2xx_gpu_init(struct drm_device = *dev) adreno_gpu =3D &a2xx_gpu->base; gpu =3D &adreno_gpu->base; =20 - gpu->perfcntrs =3D perfcntrs; - gpu->num_perfcntrs =3D ARRAY_SIZE(perfcntrs); - ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, 1); if (ret) goto fail; diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a3xx_gpu.c index 018183e0ac3f..c17e9777beae 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -266,12 +266,6 @@ static int a3xx_hw_init(struct msm_gpu *gpu) /* Turn on performance counters: */ gpu_write(gpu, REG_A3XX_RBBM_PERFCTR_CTL, 0x01); =20 - /* Enable the perfcntrs that we use.. */ - for (i =3D 0; i < gpu->num_perfcntrs; i++) { - const struct msm_gpu_perfcntr *perfcntr =3D &gpu->perfcntrs[i]; - gpu_write(gpu, perfcntr->select_reg, perfcntr->select_val); - } - gpu_write(gpu, REG_A3XX_RBBM_INT_0_MASK, A3XX_INT0_MASK); =20 ret =3D adreno_hw_init(gpu); @@ -508,13 +502,6 @@ static u32 a3xx_get_rptr(struct msm_gpu *gpu, struct m= sm_ringbuffer *ring) return ring->memptrs->rptr; } =20 -static const struct msm_gpu_perfcntr perfcntrs[] =3D { - { REG_A3XX_SP_PERFCOUNTER6_SELECT, REG_A3XX_RBBM_PERFCTR_SP_6_LO, - SP_ALU_ACTIVE_CYCLES, "ALUACTIVE" }, - { REG_A3XX_SP_PERFCOUNTER7_SELECT, REG_A3XX_RBBM_PERFCTR_SP_7_LO, - SP_FS_FULL_ALU_INSTRUCTIONS, "ALUFULL" }, -}; - static struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) { struct a3xx_gpu *a3xx_gpu =3D NULL; @@ -542,9 +529,6 @@ static struct msm_gpu *a3xx_gpu_init(struct drm_device = *dev) adreno_gpu =3D &a3xx_gpu->base; gpu =3D &adreno_gpu->base; =20 - gpu->perfcntrs =3D perfcntrs; - gpu->num_perfcntrs =3D ARRAY_SIZE(perfcntrs); - adreno_gpu->registers =3D a3xx_registers; =20 ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, 1); diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a4xx_gpu.c index e6ab731f8e9a..6392126f48f2 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -652,9 +652,6 @@ static struct msm_gpu *a4xx_gpu_init(struct drm_device = *dev) adreno_gpu =3D &a4xx_gpu->base; gpu =3D &adreno_gpu->base; =20 - gpu->perfcntrs =3D NULL; - gpu->num_perfcntrs =3D 0; - ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, 1); if (ret) goto fail; diff --git a/drivers/gpu/drm/msm/msm_debugfs.c b/drivers/gpu/drm/msm/msm_de= bugfs.c index 1059a9b29d6a..f12701e286ec 100644 --- a/drivers/gpu/drm/msm/msm_debugfs.c +++ b/drivers/gpu/drm/msm/msm_debugfs.c @@ -344,12 +344,6 @@ static int late_init_minor(struct drm_minor *minor) return ret; } =20 - ret =3D msm_perf_debugfs_init(minor); - if (ret) { - DRM_DEV_ERROR(dev->dev, "could not install perf debugfs\n"); - return ret; - } - return 0; } =20 diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index edc3b4af14f4..3066547f319b 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -87,7 +87,6 @@ static int msm_drm_uninit(struct device *dev, const struc= t component_ops *gpu_op =20 msm_gem_shrinker_cleanup(ddev); =20 - msm_perf_debugfs_cleanup(priv); msm_rd_debugfs_cleanup(priv); =20 if (priv->kms) diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 6d847d593f1a..e53e4f220bed 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -45,7 +45,6 @@ struct msm_gpu; struct msm_mmu; struct msm_mdss; struct msm_rd_state; -struct msm_perf_state; struct msm_gem_submit; struct msm_fence_context; struct msm_disp_state; @@ -89,7 +88,6 @@ struct msm_drm_private { =20 struct msm_rd_state *rd; /* debugfs to dump all submits */ struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */ - struct msm_perf_state *perf; =20 /** * total_mem: Total/global amount of memory backing GEM objects. @@ -442,8 +440,6 @@ void msm_rd_debugfs_cleanup(struct msm_drm_private *pri= v); __printf(3, 4) void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *su= bmit, const char *fmt, ...); -int msm_perf_debugfs_init(struct drm_minor *minor); -void msm_perf_debugfs_cleanup(struct msm_drm_private *priv); #else static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0= ; } __printf(3, 4) @@ -451,7 +447,6 @@ static inline void msm_rd_dump_submit(struct msm_rd_sta= te *rd, struct msm_gem_submit *submit, const char *fmt, ...) {} static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} -static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) = {} #endif =20 struct clk *msm_clk_get(struct platform_device *pdev, const char *name); diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index cf244fd529aa..1bac70473f80 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -699,104 +699,6 @@ void msm_gpu_sysrq_kill(struct msm_gpu *gpu) } } =20 -/* - * Performance Counters: - */ - -/* called under perf_lock */ -static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t = *cntrs) -{ - uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)]; - int i, n =3D min(ncntrs, gpu->num_perfcntrs); - - /* read current values: */ - for (i =3D 0; i < gpu->num_perfcntrs; i++) - current_cntrs[i] =3D gpu_read(gpu, gpu->perfcntrs[i].sample_reg); - - /* update cntrs: */ - for (i =3D 0; i < n; i++) - cntrs[i] =3D current_cntrs[i] - gpu->last_cntrs[i]; - - /* save current values: */ - for (i =3D 0; i < gpu->num_perfcntrs; i++) - gpu->last_cntrs[i] =3D current_cntrs[i]; - - return n; -} - -static void update_sw_cntrs(struct msm_gpu *gpu) -{ - ktime_t time; - uint32_t elapsed; - unsigned long flags; - - spin_lock_irqsave(&gpu->perf_lock, flags); - if (!gpu->perfcntr_active) - goto out; - - time =3D ktime_get(); - elapsed =3D ktime_to_us(ktime_sub(time, gpu->last_sample.time)); - - gpu->totaltime +=3D elapsed; - if (gpu->last_sample.active) - gpu->activetime +=3D elapsed; - - gpu->last_sample.active =3D msm_gpu_active(gpu); - gpu->last_sample.time =3D time; - -out: - spin_unlock_irqrestore(&gpu->perf_lock, flags); -} - -void msm_gpu_perfcntr_start(struct msm_gpu *gpu) -{ - unsigned long flags; - - pm_runtime_get_sync(&gpu->pdev->dev); - - spin_lock_irqsave(&gpu->perf_lock, flags); - /* we could dynamically enable/disable perfcntr registers too.. */ - gpu->last_sample.active =3D msm_gpu_active(gpu); - gpu->last_sample.time =3D ktime_get(); - gpu->activetime =3D gpu->totaltime =3D 0; - gpu->perfcntr_active =3D true; - update_hw_cntrs(gpu, 0, NULL); - spin_unlock_irqrestore(&gpu->perf_lock, flags); -} - -void msm_gpu_perfcntr_stop(struct msm_gpu *gpu) -{ - gpu->perfcntr_active =3D false; - pm_runtime_put_sync(&gpu->pdev->dev); -} - -/* returns -errno or # of cntrs sampled */ -int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, - uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs) -{ - unsigned long flags; - int ret; - - spin_lock_irqsave(&gpu->perf_lock, flags); - - if (!gpu->perfcntr_active) { - ret =3D -EINVAL; - goto out; - } - - *activetime =3D gpu->activetime; - *totaltime =3D gpu->totaltime; - - gpu->activetime =3D gpu->totaltime =3D 0; - - ret =3D update_hw_cntrs(gpu, ncntrs, cntrs); - -out: - spin_unlock_irqrestore(&gpu->perf_lock, flags); - - return ret; -} - /* * Cmdstream submission/retirement: */ @@ -899,7 +801,6 @@ void msm_gpu_retire(struct msm_gpu *gpu) msm_update_fence(gpu->rb[i]->fctx, gpu->rb[i]->memptrs->fence); =20 kthread_queue_work(gpu->worker, &gpu->retire_work); - update_sw_cntrs(gpu); } =20 /* add bo's to gpu's ring, and kick gpu: */ @@ -916,8 +817,6 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem= _submit *submit) =20 submit->seqno =3D submit->hw_fence->seqno; =20 - update_sw_cntrs(gpu); - /* * ring->submits holds a ref to the submit, to deal with the case * that a submit completes before msm_ioctl_gem_submit() returns. @@ -1009,9 +908,6 @@ int msm_gpu_init(struct drm_device *drm, struct platfo= rm_device *pdev, void *memptrs; uint64_t memptrs_iova; =20 - if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs))) - gpu->num_perfcntrs =3D ARRAY_SIZE(gpu->last_cntrs); - gpu->dev =3D drm; gpu->funcs =3D funcs; gpu->name =3D name; @@ -1043,9 +939,6 @@ int msm_gpu_init(struct drm_device *drm, struct platfo= rm_device *pdev, =20 timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0); =20 - spin_lock_init(&gpu->perf_lock); - - /* Map registers: */ gpu->mmio =3D msm_ioremap(pdev, config->ioname); if (IS_ERR(gpu->mmio)) { diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 07abbe33d992..78e1478669be 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -22,7 +22,6 @@ =20 struct msm_gem_submit; struct msm_gem_vm_log_entry; -struct msm_gpu_perfcntr; struct msm_gpu_state; struct msm_context; =20 @@ -168,18 +167,6 @@ struct msm_gpu { =20 struct adreno_smmu_priv adreno_smmu; =20 - /* performance counters (hw & sw): */ - spinlock_t perf_lock; - bool perfcntr_active; - struct { - bool active; - ktime_t time; - } last_sample; - uint32_t totaltime, activetime; /* sw counters */ - uint32_t last_cntrs[5]; /* hw counters */ - const struct msm_gpu_perfcntr *perfcntrs; - uint32_t num_perfcntrs; - struct msm_ringbuffer *rb[MSM_GPU_MAX_RINGS]; int nr_rings; =20 @@ -320,19 +307,6 @@ static inline bool msm_gpu_active(struct msm_gpu *gpu) return false; } =20 -/* Perf-Counters: - * The select_reg and select_val are just there for the benefit of the chi= ld - * class that actually enables the perf counter.. but msm_gpu base class - * will handle sampling/displaying the counters. - */ - -struct msm_gpu_perfcntr { - uint32_t select_reg; - uint32_t sample_reg; - uint32_t select_val; - const char *name; -}; - /* * The number of priority levels provided by drm gpu scheduler. The * DRM_SCHED_PRIORITY_KERNEL priority level is treated specially in some @@ -689,11 +663,6 @@ void msm_devfreq_idle(struct msm_gpu *gpu); =20 int msm_gpu_hw_init(struct msm_gpu *gpu); =20 -void msm_gpu_perfcntr_start(struct msm_gpu *gpu); -void msm_gpu_perfcntr_stop(struct msm_gpu *gpu); -int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, - uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs); - void msm_gpu_retire(struct msm_gpu *gpu); void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit); void msm_gpu_sysrq_kill(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/msm_perf.c b/drivers/gpu/drm/msm/msm_perf.c deleted file mode 100644 index 7768bde6745f..000000000000 --- a/drivers/gpu/drm/msm/msm_perf.c +++ /dev/null @@ -1,235 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Red Hat - * Author: Rob Clark - */ - -/* For profiling, userspace can: - * - * tail -f /sys/kernel/debug/dri//gpu - * - * This will enable performance counters/profiling to track the busy time - * and any gpu specific performance counters that are supported. - */ - -#ifdef CONFIG_DEBUG_FS - -#include -#include - -#include - -#include "msm_drv.h" -#include "msm_gpu.h" - -struct msm_perf_state { - struct drm_device *dev; - - bool open; - int cnt; - struct mutex read_lock; - - char buf[256]; - int buftot, bufpos; - - unsigned long next_jiffies; -}; - -#define SAMPLE_TIME (HZ/4) - -/* wait for next sample time: */ -static int wait_sample(struct msm_perf_state *perf) -{ - unsigned long start_jiffies =3D jiffies; - - if (time_after(perf->next_jiffies, start_jiffies)) { - unsigned long remaining_jiffies =3D - perf->next_jiffies - start_jiffies; - int ret =3D schedule_timeout_interruptible(remaining_jiffies); - if (ret > 0) { - /* interrupted */ - return -ERESTARTSYS; - } - } - perf->next_jiffies +=3D SAMPLE_TIME; - return 0; -} - -static int refill_buf(struct msm_perf_state *perf) -{ - struct msm_drm_private *priv =3D perf->dev->dev_private; - struct msm_gpu *gpu =3D priv->gpu; - char *ptr =3D perf->buf; - int rem =3D sizeof(perf->buf); - int i, n; - - if ((perf->cnt++ % 32) =3D=3D 0) { - /* Header line: */ - n =3D scnprintf(ptr, rem, "%%BUSY"); - ptr +=3D n; - rem -=3D n; - - for (i =3D 0; i < gpu->num_perfcntrs; i++) { - const struct msm_gpu_perfcntr *perfcntr =3D &gpu->perfcntrs[i]; - n =3D scnprintf(ptr, rem, "\t%s", perfcntr->name); - ptr +=3D n; - rem -=3D n; - } - } else { - /* Sample line: */ - uint32_t activetime =3D 0, totaltime =3D 0; - uint32_t cntrs[5]; - uint32_t val; - int ret; - - /* sleep until next sample time: */ - ret =3D wait_sample(perf); - if (ret) - return ret; - - ret =3D msm_gpu_perfcntr_sample(gpu, &activetime, &totaltime, - ARRAY_SIZE(cntrs), cntrs); - if (ret < 0) - return ret; - - val =3D totaltime ? 1000 * activetime / totaltime : 0; - n =3D scnprintf(ptr, rem, "%3d.%d%%", val / 10, val % 10); - ptr +=3D n; - rem -=3D n; - - for (i =3D 0; i < ret; i++) { - /* cycle counters (I think).. convert to MHz.. */ - val =3D cntrs[i] / 10000; - n =3D scnprintf(ptr, rem, "\t%5d.%02d", - val / 100, val % 100); - ptr +=3D n; - rem -=3D n; - } - } - - n =3D scnprintf(ptr, rem, "\n"); - ptr +=3D n; - rem -=3D n; - - perf->bufpos =3D 0; - perf->buftot =3D ptr - perf->buf; - - return 0; -} - -static ssize_t perf_read(struct file *file, char __user *buf, - size_t sz, loff_t *ppos) -{ - struct msm_perf_state *perf =3D file->private_data; - int n =3D 0, ret =3D 0; - - mutex_lock(&perf->read_lock); - - if (perf->bufpos >=3D perf->buftot) { - ret =3D refill_buf(perf); - if (ret) - goto out; - } - - n =3D min((int)sz, perf->buftot - perf->bufpos); - if (copy_to_user(buf, &perf->buf[perf->bufpos], n)) { - ret =3D -EFAULT; - goto out; - } - - perf->bufpos +=3D n; - *ppos +=3D n; - -out: - mutex_unlock(&perf->read_lock); - if (ret) - return ret; - return n; -} - -static int perf_open(struct inode *inode, struct file *file) -{ - struct msm_perf_state *perf =3D inode->i_private; - struct drm_device *dev =3D perf->dev; - struct msm_drm_private *priv =3D dev->dev_private; - struct msm_gpu *gpu =3D priv->gpu; - int ret =3D 0; - - if (!gpu) - return -ENODEV; - - mutex_lock(&gpu->lock); - - if (perf->open) { - ret =3D -EBUSY; - goto out; - } - - file->private_data =3D perf; - perf->open =3D true; - perf->cnt =3D 0; - perf->buftot =3D 0; - perf->bufpos =3D 0; - msm_gpu_perfcntr_start(gpu); - perf->next_jiffies =3D jiffies + SAMPLE_TIME; - -out: - mutex_unlock(&gpu->lock); - return ret; -} - -static int perf_release(struct inode *inode, struct file *file) -{ - struct msm_perf_state *perf =3D inode->i_private; - struct msm_drm_private *priv =3D perf->dev->dev_private; - msm_gpu_perfcntr_stop(priv->gpu); - perf->open =3D false; - return 0; -} - - -static const struct file_operations perf_debugfs_fops =3D { - .owner =3D THIS_MODULE, - .open =3D perf_open, - .read =3D perf_read, - .release =3D perf_release, -}; - -int msm_perf_debugfs_init(struct drm_minor *minor) -{ - struct msm_drm_private *priv =3D minor->dev->dev_private; - struct msm_perf_state *perf; - - /* only create on first minor: */ - if (priv->perf) - return 0; - - perf =3D kzalloc_obj(*perf); - if (!perf) - return -ENOMEM; - - perf->dev =3D minor->dev; - - mutex_init(&perf->read_lock); - priv->perf =3D perf; - - debugfs_create_file("perf", S_IFREG | S_IRUGO, minor->debugfs_root, - perf, &perf_debugfs_fops); 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charset="utf-8" Use perfmon_capable() which checks both CAP_SYS_ADMIN and CAP_PERFMON. This matches what i915 and xe do, and seems more appropriate. Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov Reviewed-by: Anna Maniscalco Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/= adreno/adreno_gpu.c index 66f80f2d12f9..72b71e9e44f0 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -494,7 +494,7 @@ int adreno_set_param(struct msm_gpu *gpu, struct msm_co= ntext *ctx, return 0; } case MSM_PARAM_SYSPROF: - if (!capable(CAP_SYS_ADMIN)) + if (!perfmon_capable()) return UERR(EPERM, drm, "invalid permissions"); return msm_context_set_sysprof(ctx, gpu, value); case MSM_PARAM_EN_VM_BIND: --=20 2.54.0 From nobody Sun May 24 19:33:39 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 498F43655EC for ; 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charset="utf-8" Most of the churn is just reworking the usage attribute on the mesa side. Sync from mesa commit 4d4a951ac622 ("fd: add a8xx perfcntr countables"). Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov Reviewed-by: Anna Maniscalco Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 16 +- drivers/gpu/drm/msm/registers/adreno/a3xx.xml | 8 +- drivers/gpu/drm/msm/registers/adreno/a5xx.xml | 141 +- drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 1300 +++++------ .../msm/registers/adreno/a6xx_descriptors.xml | 71 +- .../drm/msm/registers/adreno/a6xx_enums.xml | 3 + .../msm/registers/adreno/a8xx_descriptors.xml | 96 +- .../msm/registers/adreno/a8xx_perfcntrs.xml | 1929 +++++++++++++++++ .../msm/registers/adreno/adreno_common.xml | 42 + .../drm/msm/registers/adreno/adreno_pm4.xml | 50 +- 10 files changed, 2846 insertions(+), 810 deletions(-) create mode 100644 drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.xml diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a5xx_gpu.c index 79acae11154a..9a03684288d3 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -752,17 +752,13 @@ static int a5xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A5XX_UCHE_CACHE_WAYS, 0x02); =20 /* Disable L2 bypass in the UCHE */ - gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_LO, lower_32_bits(adreno_gpu->uche= _trap_base)); - gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_HI, upper_32_bits(adreno_gpu->uche= _trap_base)); - gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_LO, lower_32_bits(adreno_gpu= ->uche_trap_base)); - gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_HI, upper_32_bits(adreno_gpu= ->uche_trap_base)); + gpu_write64(gpu, REG_A5XX_UCHE_TRAP_BASE, adreno_gpu->uche_trap_base); + gpu_write64(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_bas= e); =20 /* Set the GMEM VA range (0 to gpu->gmem) */ - gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_LO, 0x00100000); - gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_HI, 0x00000000); - gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_LO, + gpu_write64(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN, 0x00100000); + gpu_write64(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX, 0x00100000 + adreno_gpu->info->gmem - 1); - gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000); =20 if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) || adreno_is_a510(adreno_gpu)) { @@ -1217,9 +1213,7 @@ static void a5xx_rbbm_err_irq(struct msm_gpu *gpu, u3= 2 status) =20 static void a5xx_uche_err_irq(struct msm_gpu *gpu) { - uint64_t addr =3D (uint64_t) gpu_read(gpu, REG_A5XX_UCHE_TRAP_LOG_HI); - - addr |=3D gpu_read(gpu, REG_A5XX_UCHE_TRAP_LOG_LO); + uint64_t addr =3D gpu_read64(gpu, REG_A5XX_UCHE_TRAP_LOG); =20 dev_err_ratelimited(gpu->dev->dev, "UCHE | Out of bounds access | addr=3D= 0x%llX\n", addr); diff --git a/drivers/gpu/drm/msm/registers/adreno/a3xx.xml b/drivers/gpu/dr= m/msm/registers/adreno/a3xx.xml index 6717abc0a897..09c9606fc3e1 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a3xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a3xx.xml @@ -1330,11 +1330,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org= /freedreno/ rules-fd.xsd"> - - + @@ -1420,7 +1416,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/= freedreno/ rules-fd.xsd"> - + diff --git a/drivers/gpu/drm/msm/registers/adreno/a5xx.xml b/drivers/gpu/dr= m/msm/registers/adreno/a5xx.xml index bd8df5945166..4af76b3750f7 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a5xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a5xx.xml @@ -1418,8 +1418,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/= freedreno/ rules-fd.xsd"> - - + @@ -1498,12 +1497,10 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.or= g/freedreno/ rules-fd.xsd"> - - + - - + @@ -1555,20 +1552,14 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.or= g/freedreno/ rules-fd.xsd"> - - - - - - - - + + + + - - - - + + @@ -1583,8 +1574,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/= freedreno/ rules-fd.xsd"> - - + =20 @@ -1923,8 +1913,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/= freedreno/ rules-fd.xsd"> invalidates the LRZ buffer? (Or just the covered positions? --> - - + @@ -1933,8 +1922,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/= freedreno/ rules-fd.xsd"> is also divided by 8 (ie. covers 8x8 pixels) - - + =20 @@ -2035,8 +2023,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear= of depth32? not set --> - - + @@ -2089,8 +2076,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear= of depth32? not set - - + stride of depth/stencil buffer @@ -2119,8 +2105,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear= of depth32? not set - - + @@ -2163,8 +2148,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear= of depth32? not set also for gmem->mem preserving tiling --> - - + @@ -2235,25 +2219,22 @@ bit 7 for RECTLIST (clear) when z32s8 (used for cle= ar of depth32? not set =20 =20 - - + - + - - + =20 - - + =20 @@ -2357,13 +2338,11 @@ bit 7 for RECTLIST (clear) when z32s8 (used for cle= ar of depth32? not set - - + - - + =20 @@ -2423,8 +2402,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear= of depth32? not set - - + @@ -2475,7 +2453,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear= of depth32? not set - + @@ -2516,8 +2494,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear= of depth32? not set - - + =20 @@ -2538,8 +2515,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear= of depth32? not set - - + @@ -2577,8 +2553,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear= of depth32? not set - - + @@ -2587,22 +2562,19 @@ bit 7 for RECTLIST (clear) when z32s8 (used for cle= ar of depth32? not set =20 - - + - - + - - + @@ -2615,8 +2587,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear= of depth32? not set - - + =20 diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/dr= m/msm/registers/adreno/a6xx.xml index 2309870f5031..3349c01646e1 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml @@ -10,19 +10,24 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fr= eedreno/ rules-fd.xsd"> + =20 @@ -1321,7 +1326,7 @@ by a particular renderpass/blit. =20 - + @@ -1331,13 +1336,13 @@ by a particular renderpass/blit. =20 - + - + - + Configures the mapping between VSC_PIPE buffer and @@ -1370,7 +1375,7 @@ by a particular renderpass/blit. =20 - + Seems to be a bitmap of which tiles mapped to the VSC pipe contain geometry. @@ -1381,7 +1386,7 @@ by a particular renderpass/blit. =20 - + Has the size of data written to corresponding VSC_PRIM_STRM buffer. @@ -1389,7 +1394,7 @@ by a particular renderpass/blit. =20 - + Has the size of data written to corresponding VSC pipe, ie. same thing that is written out to VSC_SIZE_BASE @@ -1397,7 +1402,7 @@ by a particular renderpass/blit. =20 - + =20 @@ -1428,29 +1433,22 @@ by a particular renderpass/blit. =20 - - + + =20 - - - - - - - - - - - - - - - - + + + + + + + + + =20 @@ -1465,16 +1463,16 @@ by a particular renderpass/blit. =20 - - + + =20 =20 - - + + =20 @@ -1499,33 +1497,48 @@ by a particular renderpass/blit. =20 - + + + =20 - + - + - + - + =20 + + + + + + + + + + + + + =20 - + @@ -1534,7 +1547,7 @@ by a particular renderpass/blit. =20 - + @@ -1543,16 +1556,16 @@ by a particular renderpass/blit. =20 - + - + =20 - + @@ -1572,17 +1585,18 @@ by a particular renderpass/blit. TODO: what about gen2 (a640)? --> - - - - - - - - + + + + + + + + + =20 @@ -1590,49 +1604,49 @@ by a particular renderpass/blit. =20 - - + + =20 - - + + =20 =20 - - + + =20 =20 - - + + =20 =20 - - + + =20 =20 - - + + =20 - - + + =20 - - + + =20 - - + + =20 @@ -1640,8 +1654,8 @@ by a particular renderpass/blit. =20 - - + + =20 @@ -1667,19 +1681,19 @@ by a particular renderpass/blit. - - - + + + =20 - - - + + + =20 =20 - + =20 @@ -1738,10 +1752,10 @@ by a particular renderpass/blit. =20 - + - + =20 @@ -1778,7 +1792,7 @@ by a particular renderpass/blit. =20 - + =20 @@ -1795,7 +1809,7 @@ by a particular renderpass/blit. =20 - + @@ -1808,16 +1822,16 @@ by a particular renderpass/blit. =20 - - + + =20 =20 - - + + =20 @@ -1835,15 +1849,15 @@ by a particular renderpass/blit. =20 - - - + + + =20 - - - - - + + + + + =20 @@ -1860,30 +1874,53 @@ by a particular renderpass/blit. =20 - + =20 - + =20 - + - + =20 - - + + + + + + + + + + + + + + + + + + + + + + =20 - - + + + + + =20 @@ -1893,45 +1930,59 @@ by a particular renderpass/blit. =20 - + + + + + + + + + =20 - - + + + + + =20 =20 - - + + + + + =20 =20 - - + + =20 - - + + =20 =20 - - + + =20 @@ -1966,24 +2017,23 @@ by a particular renderpass/blit. =20 - + - - + + =20 - + The total size of the LRZ image array (not including fast clear buffer), used as a stride for double buffering used with concurrent binning. - - - - + + + =20 @@ -1995,28 +2045,28 @@ by a particular renderpass/blit. =20 - - + + =20 =20 - - + + =20 - - + + =20 - + =20 - - + + =20 - + =20 - - + + =20 - + =20 @@ -2082,8 +2132,8 @@ by a particular renderpass/blit. =20 - - + + =20 LUT used to convert quality buffer values to HW shading rate values.= An array of 4-bit values. @@ -2128,32 +2178,32 @@ by a particular renderpass/blit. =20 - + - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + =20 @@ -2180,10 +2230,10 @@ by a particular renderpass/blit. --> =20 - - + + =20 - + @@ -2197,7 +2247,7 @@ by a particular renderpass/blit. - + @@ -2206,26 +2256,26 @@ by a particular renderpass/blit. =20 - + - + =20 - - - - - + + + + + - + @@ -2236,7 +2286,7 @@ by a particular renderpass/blit. - + @@ -2248,16 +2298,16 @@ by a particular renderpass/blit. =20 - + - + - + @@ -2277,7 +2327,7 @@ by a particular renderpass/blit. - + @@ -2289,11 +2339,11 @@ by a particular renderpass/blit. =20 - + - + @@ -2316,7 +2366,7 @@ by a particular renderpass/blit. =20 - + =20 @@ -2330,12 +2380,12 @@ by a particular renderpass/blit. =20 - + =20 - + @@ -2383,16 +2433,16 @@ by a particular renderpass/blit. =20 - - - - + + + + - + @@ -2401,12 +2451,12 @@ by a particular renderpass/blit. - + - + =20 - + @@ -2422,23 +2472,23 @@ by a particular renderpass/blit. =20 - + - + =20 - - - - + + + + =20 - - + + - + - + - + @@ -2498,41 +2548,41 @@ by a particular renderpass/blit. - - + + =20 - + - + =20 - + - - + + - + =20 - - - + + + =20 - - + + - + - + @@ -2541,23 +2591,23 @@ by a particular renderpass/blit. - - + + - - + + =20 =20 - + =20 - - - - + + + + =20 @@ -2567,7 +2617,7 @@ by a particular renderpass/blit. =20 - + @@ -2595,7 +2645,7 @@ by a particular renderpass/blit. - + =20 @@ -2637,17 +2687,17 @@ by a particular renderpass/blit. =20 - + =20 - + =20 - + @@ -2656,16 +2706,25 @@ by a particular renderpass/blit. + + + + + + + + + - - + + =20 - + @@ -2683,7 +2742,8 @@ by a particular renderpass/blit. =20 - + + =20 @@ -2693,13 +2753,13 @@ by a particular renderpass/blit. These show up in a6xx gen3+ but so far haven't found an example of blob writing non-zero: --> - - - - + + + + =20 - - + + =20 @@ -2731,28 +2791,28 @@ by a particular renderpass/blit. =20 - - - + + + - - - + + + =20 - - + + - - + + =20 - - - - + + + + =20 - + =20 =20 @@ -2821,7 +2881,7 @@ by a particular renderpass/blit. =20 - + =20 @@ -2847,7 +2907,7 @@ by a particular renderpass/blit. =20 =20 - + =20 @@ -2860,17 +2920,17 @@ by a particular renderpass/blit. - - - + + + =20 - - - + + + =20 - - - + + + =20 @@ -2878,17 +2938,17 @@ by a particular renderpass/blit. =20 - - - + + + =20 - - - + + + =20 - - - + + + =20 @@ -2897,19 +2957,19 @@ by a particular renderpass/blit. =20 - - - - + + + + =20 - + =20 - - + + @@ -2949,14 +3009,14 @@ by a particular renderpass/blit. =20 - - - - - - - - + + + + + + + + =20 @@ -2973,20 +3033,20 @@ by a particular renderpass/blit. =20 - + Packed array of a6xx_varying_interp_mode - + Packed array of a6xx_varying_ps_repl_mode =20 - + Packed array of a6xx_varying_interp_mode - + Packed array of a6xx_varying_ps_repl_mode @@ -2995,12 +3055,12 @@ by a particular renderpass/blit. =20 - + =20 - + @@ -3034,8 +3094,8 @@ by a particular renderpass/blit. =20 - - + + =20 @@ -3047,8 +3107,8 @@ by a particular renderpass/blit. =20 - - + + =20 @@ -3097,13 +3157,13 @@ by a particular renderpass/blit. =20 - - - + + + =20 - - - + + + =20 @@ -3124,8 +3184,8 @@ by a particular renderpass/blit. =20 - - + + =20 - - + + =20 @@ -3253,7 +3313,7 @@ by a particular renderpass/blit. =20 - + @@ -3287,9 +3347,12 @@ by a particular renderpass/blit. =20 =20 - - - + + + + + + =20 =20 - - + + =20 @@ -3324,31 +3387,31 @@ by a particular renderpass/blit. =20 - - - - + + + + =20 - - - - + + + + =20 - - + + =20 - + size in vec4s of per-primitive storage for gs. TODO: not actually in V= PC =20 - - + + - - + + @@ -3426,18 +3489,18 @@ by a particular renderpass/blit. =20 - + - + - + This is the ID of the current patch within the @@ -3450,20 +3513,20 @@ by a particular renderpass/blit. - + - - + + - + - + - + @@ -3474,7 +3537,7 @@ by a particular renderpass/blit. =20 - + @@ -3482,14 +3545,14 @@ by a particular renderpass/blit. =20 - - - + + + - + @@ -3502,14 +3565,14 @@ by a particular renderpass/blit. - + =20 - + =20 =20 @@ -3549,10 +3612,12 @@ by a particular renderpass/blit. --> - - - + + + + + =20 @@ -3580,7 +3645,7 @@ by a particular renderpass/blit. =20 - + - - + + @@ -3623,7 +3688,7 @@ by a particular renderpass/blit. an extra varying after, but with a lower OUTLOC position. If present, psize is last, preceded by position. --> - + @@ -3712,20 +3777,20 @@ by a particular renderpass/blit. =20 - - - - - - - - - + + + + + + + + + =20 - + @@ -3735,32 +3800,32 @@ by a particular renderpass/blit. the maximum size of local storage should be: 64 (wavesize) * 64 (SP_HS_CNTL_1) * 4 =3D 16k --> - - + + =20 - - - - - - - - - + + + + + + + + + =20 - + =20 - - + + @@ -3768,7 +3833,7 @@ by a particular renderpass/blit. - + @@ -3778,24 +3843,24 @@ by a particular renderpass/blit. =20 - - - - - - - - - + + + + + + + + + =20 - + - + Normally the size of the output of the last stage in dwords. It should be programmed as follows: @@ -3809,14 +3874,14 @@ by a particular renderpass/blit. doesn't matter in practice. - + =20 - + - + @@ -3825,7 +3890,7 @@ by a particular renderpass/blit. =20 - + @@ -3835,15 +3900,15 @@ by a particular renderpass/blit. =20 - - - - - - - - - + + + + + + + + + @@ -3859,7 +3924,7 @@ by a particular renderpass/blit. =20 =20 - + @@ -3878,16 +3943,15 @@ by a particular renderpass/blit. and so one pixel's value is always unused. - - - - - - + + + + + =20 @@ -3897,12 +3961,12 @@ by a particular renderpass/blit. =20 - - + + =20 - + @@ -3913,7 +3977,7 @@ by a particular renderpass/blit. - + @@ -3923,17 +3987,17 @@ by a particular renderpass/blit. - + - + =20 - + per MRT @@ -3941,7 +4005,7 @@ by a particular renderpass/blit. =20 - + @@ -3950,7 +4014,7 @@ by a particular renderpass/blit. =20 - + @@ -3967,7 +4031,7 @@ by a particular renderpass/blit. - + @@ -3981,7 +4045,7 @@ by a particular renderpass/blit. - + @@ -3993,21 +4057,21 @@ by a particular renderpass/blit. - + - + - + =20 =20 - + @@ -4025,7 +4089,7 @@ by a particular renderpass/blit. =20 - + If 0 - all 32k of shared storage is enabled, otherwise @@ -4045,29 +4109,29 @@ by a particular renderpass/blit. - - - - - - - - - - - - + + + + + + + + + + + + =20 - + - + @@ -4104,10 +4168,10 @@ by a particular renderpass/blit. =20 =20 - - - - + + + + =20 @@ -4118,13 +4182,13 @@ by a particular renderpass/blit. =20 - + - + @@ -4134,9 +4198,9 @@ by a particular renderpass/blit. - - - + + + =20 @@ -4192,7 +4256,7 @@ by a particular renderpass/blit. =20 - + - + =20 - + =20 - - + + =20 - + =20 - + - + @@ -4259,8 +4323,8 @@ by a particular renderpass/blit. =20 - - + + =20 @@ -4268,7 +4332,14 @@ by a particular renderpass/blit. - + + + When this bit is enabled, new waves may be unlocked once + all invocations have signaled they don't need local + memory anymore using (eolm)nop. + + + @@ -4333,7 +4404,7 @@ by a particular renderpass/blit. =20 - + =20 - - - - + + + + =20 - + =20 + =20 - =20 - + @@ -4387,6 +4458,11 @@ by a particular renderpass/blit. + + + + + =20 @@ -4395,24 +4471,26 @@ by a particular renderpass/blit. badly named or the functionality moved in a6xx. But downstream kernel calls this "a6xx_sp_ps_tp_2d_cluster" --> - - + + - - + + =20 - - + + - - + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + - - + + + =20 - - + + + - + + + - + - - - - - - + + + + + + - + - + - - - - + + + + =20 - + - + - + - + - + - + - + - + - - - + + + =20 - + - + - + - + - + - + - + - - - + + + =20 @@ -4690,7 +4774,7 @@ by a particular renderpass/blit. =20 - + @@ -4711,7 +4795,7 @@ by a particular renderpass/blit. =20 - + @@ -4723,7 +4807,7 @@ by a particular renderpass/blit. =20 - + @@ -4731,7 +4815,7 @@ by a particular renderpass/blit. =20 - + @@ -4750,7 +4834,7 @@ by a particular renderpass/blit. =20 - + This register clears pending loads queued up by CP_LOAD_STATE6. Each bit resets a particular kind(s) of @@ -4790,7 +4874,7 @@ by a particular renderpass/blit. =20 - + This register clears pending loads queued up by CP_LOAD_STATE6. Each bit resets a particular kind(s) of @@ -4813,7 +4897,7 @@ by a particular renderpass/blit. =20 - + This register clears pending loads queued up by CP_LOAD_STATE6. Each bit resets a particular kind(s) of @@ -4829,16 +4913,16 @@ by a particular renderpass/blit. =20 - - + + =20 - - + + =20 - - + + =20 - + Shared constants are intended to be used for Vulkan push constants. When enabled, 8 vec4's are reserved in the FS diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_descriptors.xml b/dr= ivers/gpu/drm/msm/registers/adreno/a6xx_descriptors.xml index 56cfaff614a4..08bc37f29a6f 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx_descriptors.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_descriptors.xml @@ -45,19 +45,21 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fr= eedreno/ rules-fd.xsd"> =20 - + Texture constant dwords - - - - - + + + + + + - - + + + probably for D3D structured UAVs, normally set to 1 - - + + =20 - + Pitch in bytes (so actually stride) - + @@ -94,15 +97,15 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fr= eedreno/ rules-fd.xsd"> layer size at the point that it stops being reduced moving to higher (smaller) mipmap levels --> - - + + - - + + - + - + + + + + - + + - + + + + - + + - + - - + + + + + diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml b/drivers/= gpu/drm/msm/registers/adreno/a6xx_enums.xml index 81538831dc19..b44946f36fae 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml @@ -328,6 +328,9 @@ to upconvert to 32b float internally? + + + =20 diff --git a/drivers/gpu/drm/msm/registers/adreno/a8xx_descriptors.xml b/dr= ivers/gpu/drm/msm/registers/adreno/a8xx_descriptors.xml index edcbdb3b6921..d119d021446c 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a8xx_descriptors.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a8xx_descriptors.xml @@ -39,76 +39,92 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fr= eedreno/ rules-fd.xsd"> =20 - + Texture memobj dwords - + + for type TEX_BUFFER + - + + - + + for type TEX_BUFFER, probably for D3D structured UAVs, normally se= t to 1 + - - - + + + + - - - - + + + + - - - - + + + + - + - + - + - - - - + + + + + + + + + + - = - - + + + - - - - - - + + + + + + - - + + + + + + - + - - + + - + - + - - + + diff --git a/drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.xml b/driv= ers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.xml new file mode 100644 index 000000000000..a5bb44f76956 --- /dev/null +++ b/drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.xml @@ -0,0 +1,1929 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml b/drive= rs/gpu/drm/msm/registers/adreno/adreno_common.xml index 79d204f1e400..195cee078357 100644 --- a/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml +++ b/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml @@ -14,6 +14,27 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fre= edreno/ rules-fd.xsd"> =20 + + + + TEX_MEMOBJ descriptor types. These are used + to mark fields that only apply to certain + descriptor types, and potentially overlap + with fields in other types. + + + + + + + Additional descriptor types not part of + TEX_MEMOBJ. These are described by their + own toplevel domain. + + + + + @@ -409,4 +430,25 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/f= reedreno/ rules-fd.xsd"> =20 + + + + + + + + + + + + + + + + diff --git a/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml b/drivers/= gpu/drm/msm/registers/adreno/adreno_pm4.xml index 51e9c94f5e37..f185b541aa70 100644 --- a/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml +++ b/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml @@ -152,6 +152,8 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fr= eedreno/ rules-fd.xsd"> + + @@ -1095,7 +1097,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - + @@ -1275,8 +1277,15 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - + + @@ -1469,6 +1478,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) + =20 @@ -1476,7 +1486,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - + @@ -2055,28 +2065,20 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) =20 - Executes the following DWORDs of commands if the dword at = ADDR0 - is not equal to 0 and the dword at ADDR1 is less than REF - (signed comparison). + Executes the following DWORDs of commands if the dword + at BOOL_ADDR is not equal to 0 and the the timestamp + value ACTIVE_TIMESTAMP is ahead of the value fetched + from TIMESTAMP_ADDR. + + The timestamp comparision is an unsigned compare with + wraparound, ie: + + (ACTIVE_TIMESTAMP - *TIMESTAMP_ADDR) < 0x80000000 - - - - - - - - - - - - - - - - - - + + + + =20 --=20 2.54.0 From nobody Sun May 24 19:33:39 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BD293655CB for ; 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charset="utf-8" Update gen_header.py to bring in support for generating perfcntr tables. Sync from mesa commit 1fd18a9734ad ("freedreno/registers: Add gen8 perfcntr support") Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov Reviewed-by: Anna Maniscalco Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/registers/gen_header.py | 2079 ++++++++++--------- 1 file changed, 1146 insertions(+), 933 deletions(-) diff --git a/drivers/gpu/drm/msm/registers/gen_header.py b/drivers/gpu/drm/= msm/registers/gen_header.py index 2acad951f1e2..d3b56a9d84fb 100644 --- a/drivers/gpu/drm/msm/registers/gen_header.py +++ b/drivers/gpu/drm/msm/registers/gen_header.py @@ -11,997 +11,1210 @@ import collections import argparse import time import datetime +import json + =20 class Error(Exception): - def __init__(self, message): - self.message =3D message + def __init__(self, message): + self.message =3D message + =20 class Enum(object): - def __init__(self, name): - self.name =3D name - self.values =3D [] - - def has_name(self, name): - for (n, value) in self.values: - if n =3D=3D name: - return True - return False - - def names(self): - return [n for (n, value) in self.values] - - def dump(self, is_deprecated): - use_hex =3D False - for (name, value) in self.values: - if value > 0x1000: - use_hex =3D True - - print("enum %s {" % self.name) - for (name, value) in self.values: - if use_hex: - print("\t%s =3D 0x%08x," % (name, value)) - else: - print("\t%s =3D %d," % (name, value)) - print("};\n") - - def dump_pack_struct(self, is_deprecated): - pass + def __init__(self, name): + self.name =3D name + self.values =3D [] + + def has_name(self, name): + for (n, value) in self.values: + if n =3D=3D name: + return True + return False + + def names(self): + return [n for (n, value) in self.values] + + def value(self, name): + for (n, v) in self.values: + if n =3D=3D name: + return v + + def dump(self, has_variants): + use_hex =3D False + for (name, value) in self.values: + if value > 0x1000: + use_hex =3D True + + print("enum %s {" % self.name) + for (name, value) in self.values: + if use_hex: + print("\t%s =3D 0x%08x," % (name, value)) + else: + print("\t%s =3D %d," % (name, value)) + print("};\n") + + def dump_pack_struct(self, has_variants): + pass + =20 class Field(object): - def __init__(self, name, low, high, shr, type, parser): - self.name =3D name - self.low =3D low - self.high =3D high - self.shr =3D shr - self.type =3D type - - builtin_types =3D [ None, "a3xx_regid", "boolean", "uint", "hex", "int",= "fixed", "ufixed", "float", "address", "waddress" ] - - maxpos =3D parser.current_bitsize - 1 - - if low < 0 or low > maxpos: - raise parser.error("low attribute out of range: %d" % low) - if high < 0 or high > maxpos: - raise parser.error("high attribute out of range: %d" % high) - if high < low: - raise parser.error("low is greater than high: low=3D%d, high=3D%d" % (l= ow, high)) - if self.type =3D=3D "boolean" and not low =3D=3D high: - raise parser.error("booleans should be 1 bit fields") - elif self.type =3D=3D "float" and not (high - low =3D=3D 31 or high - lo= w =3D=3D 15): - raise parser.error("floats should be 16 or 32 bit fields") - elif self.type not in builtin_types and self.type not in parser.enums: - raise parser.error("unknown type '%s'" % self.type) - - def ctype(self, var_name): - if self.type is None: - type =3D "uint32_t" - val =3D var_name - elif self.type =3D=3D "boolean": - type =3D "bool" - val =3D var_name - elif self.type =3D=3D "uint" or self.type =3D=3D "hex" or self.type =3D= =3D "a3xx_regid": - type =3D "uint32_t" - val =3D var_name - elif self.type =3D=3D "int": - type =3D "int32_t" - val =3D var_name - elif self.type =3D=3D "fixed": - type =3D "float" - val =3D "((int32_t)(%s * %d.0))" % (var_name, 1 << self.radix) - elif self.type =3D=3D "ufixed": - type =3D "float" - val =3D "((uint32_t)(%s * %d.0))" % (var_name, 1 << self.radix) - elif self.type =3D=3D "float" and self.high - self.low =3D=3D 31: - type =3D "float" - val =3D "fui(%s)" % var_name - elif self.type =3D=3D "float" and self.high - self.low =3D=3D 15: - type =3D "float" - val =3D "_mesa_float_to_half(%s)" % var_name - elif self.type in [ "address", "waddress" ]: - type =3D "uint64_t" - val =3D var_name - else: - type =3D "enum %s" % self.type - val =3D var_name - - if self.shr > 0: - val =3D "(%s >> %d)" % (val, self.shr) - - return (type, val) + def __init__(self, name, low, high, shr, type, parser): + self.name =3D name + self.low =3D low + self.high =3D high + self.shr =3D shr + self.type =3D type + + builtin_types =3D [None, "a3xx_regid", "boolean", "uint", "hex", + "int", "fixed", "ufixed", "float", "address", "wa= ddress"] + + maxpos =3D parser.current_bitsize - 1 + + if low < 0 or low > maxpos: + raise parser.error("low attribute out of range: %d" % low) + if high < 0 or high > maxpos: + raise parser.error("high attribute out of range: %d" % high) + if high < low: + raise parser.error( + "low is greater than high: low=3D%d, high=3D%d" % (low, hi= gh)) + if self.type =3D=3D "boolean" and not low =3D=3D high: + raise parser.error("booleans should be 1 bit fields") + elif self.type =3D=3D "float" and not (high - low =3D=3D 31 or hig= h - low =3D=3D 15): + raise parser.error("floats should be 16 or 32 bit fields") + elif self.type not in builtin_types and self.type not in parser.en= ums: + raise parser.error("unknown type '%s'" % self.type) + + def ctype(self, var_name): + if self.type is None: + type =3D "uint32_t" + val =3D var_name + elif self.type =3D=3D "boolean": + type =3D "bool" + val =3D var_name + elif self.type =3D=3D "uint" or self.type =3D=3D "hex" or self.typ= e =3D=3D "a3xx_regid": + type =3D "uint32_t" + val =3D var_name + elif self.type =3D=3D "int": + type =3D "int32_t" + val =3D var_name + elif self.type =3D=3D "fixed": + type =3D "float" + val =3D "(uint32_t)((int32_t)(%s * %d.0))" % (var_name, 1 << s= elf.radix) + elif self.type =3D=3D "ufixed": + type =3D "float" + val =3D "((uint32_t)(%s * %d.0))" % (var_name, 1 << self.radix) + elif self.type =3D=3D "float" and self.high - self.low =3D=3D 31: + type =3D "float" + val =3D "fui(%s)" % var_name + elif self.type =3D=3D "float" and self.high - self.low =3D=3D 15: + type =3D "float" + val =3D "_mesa_float_to_half(%s)" % var_name + elif self.type in ["address", "waddress"]: + type =3D "uint64_t" + val =3D var_name + else: + type =3D "enum %s" % self.type + val =3D var_name + + if self.shr > 0: + val =3D "(%s >> %d)" % (val, self.shr) + + return (type, val) + =20 def tab_to(name, value): - tab_count =3D (68 - (len(name) & ~7)) // 8 - if tab_count <=3D 0: - tab_count =3D 1 - print(name + ('\t' * tab_count) + value) + tab_count =3D (68 - (len(name) & ~7)) // 8 + if tab_count <=3D 0: + tab_count =3D 1 + print(name + ('\t' * tab_count) + value) + +def define_macro(name, value, has_variants): + if has_variants: + value =3D "__FD_DEPRECATED " + value + tab_to(name, value) =20 def mask(low, high): - return ((0xffffffffffffffff >> (64 - (high + 1 - low))) << low) + return ((0xffffffffffffffff >> (64 - (high + 1 - low))) << low) + =20 def field_name(reg, f): - if f.name: - name =3D f.name.lower() - else: - # We hit this path when a reg is defined with no bitset fields, ie. - # - name =3D reg.name.lower() + if f.name: + name =3D f.name.lower() + else: + # We hit this path when a reg is defined with no bitset fields, ie. + # + name =3D reg.name.lower() =20 - if (name in [ "double", "float", "int" ]) or not (name[0].isalpha()): - name =3D "_" + name + if (name in ["double", "float", "int"]) or not (name[0].isalpha()): + name =3D "_" + name =20 - return name + return name =20 # indices - array of (ctype, stride, __offsets_NAME) + + def indices_varlist(indices): - return ", ".join(["i%d" % i for i in range(len(indices))]) + return ", ".join(["i%d" % i for i in range(len(indices))]) + =20 def indices_prototype(indices): - return ", ".join(["%s i%d" % (ctype, idx) - for (idx, (ctype, stride, offset)) in enumerate(indices)]) + return ", ".join(["%s i%d" % (ctype, idx) + for (idx, (ctype, stride, offset)) in enumerate(indi= ces)]) + =20 def indices_strides(indices): - return " + ".join(["0x%x*i%d" % (stride, idx) - if stride else - "%s(i%d)" % (offset, idx) - for (idx, (ctype, stride, offset)) in enumerate(indices)]) + return " + ".join(["0x%x*i%d" % (stride, idx) + if stride else + "%s(i%d)" % (offset, idx) + for (idx, (ctype, stride, offset)) in enumerate(ind= ices)]) + =20 def is_number(str): - try: - int(str) - return True - except ValueError: - return False + try: + int(str) + return True + except ValueError: + return False + =20 def sanitize_variant(variant): - if variant and "-" in variant: - return variant[:variant.index("-")] - return variant + if variant and "-" in variant: + return variant[:variant.index("-")] + return variant + =20 class Bitset(object): - def __init__(self, name, template): - self.name =3D name - self.inline =3D False - self.reg =3D None - if template: - self.fields =3D template.fields[:] - else: - self.fields =3D [] - - # Get address field if there is one in the bitset, else return None: - def get_address_field(self): - for f in self.fields: - if f.type in [ "address", "waddress" ]: - return f - return None - - def dump_regpair_builder(self, reg): - print("#ifndef NDEBUG") - known_mask =3D 0 - for f in self.fields: - known_mask |=3D mask(f.low, f.high) - if f.type in [ "boolean", "address", "waddress" ]: - continue - type, val =3D f.ctype("fields.%s" % field_name(reg, f)) - print(" assert((%-40s & 0x%08x) =3D=3D 0);" % (val, 0xffffffff ^ mas= k(0 , f.high - f.low))) - print(" assert((%-40s & 0x%08x) =3D=3D 0);" % ("fields.unknown", know= n_mask)) - print("#endif\n") - - print(" return (struct fd_reg_pair) {") - print(" .reg =3D (uint32_t)%s," % reg.reg_offset()) - print(" .value =3D") - cast =3D "(uint64_t)" if reg.bit_size =3D=3D 64 else "" - for f in self.fields: - if f.type in [ "address", "waddress" ]: - continue - else: - type, val =3D f.ctype("fields.%s" % field_name(reg, f)) - print(" (%s%-40s << %2d) |" % (cast, val, f.low)) - value_name =3D "dword" - if reg.bit_size =3D=3D 64: - value_name =3D "qword" - print(" fields.unknown | fields.%s," % (value_name,)) - - address =3D self.get_address_field() - if address: - print(" .bo =3D fields.bo,") - print(" .is_address =3D true,") - if f.type =3D=3D "waddress": - print(" .bo_write =3D true,") - print(" .bo_offset =3D fields.bo_offset,") - print(" .bo_shift =3D %d," % address.shr) - print(" .bo_low =3D %d," % address.low) - - print(" };") - - def dump_pack_struct(self, is_deprecated, reg=3DNone): - if not reg: - return - - prefix =3D reg.full_name - - print("struct %s {" % prefix) - for f in self.fields: - if f.type in [ "address", "waddress" ]: - tab_to(" __bo_type", "bo;") - tab_to(" uint32_t", "bo_offset;") - continue - name =3D field_name(reg, f) - - type, val =3D f.ctype("var") - - tab_to(" %s" % type, "%s;" % name) - if reg.bit_size =3D=3D 64: - tab_to(" uint64_t", "unknown;") - tab_to(" uint64_t", "qword;") - else: - tab_to(" uint32_t", "unknown;") - tab_to(" uint32_t", "dword;") - print("};\n") - - depcrstr =3D "" - if is_deprecated: - depcrstr =3D " FD_DEPRECATED" - if reg.array: - print("static inline%s struct fd_reg_pair\npack_%s(uint32_t __i, struct= %s fields)\n{" % - (depcrstr, prefix, prefix)) - else: - print("static inline%s struct fd_reg_pair\npack_%s(struct %s fields)\n{= " % - (depcrstr, prefix, prefix)) - - self.dump_regpair_builder(reg) - - print("\n}\n") - - if self.get_address_field(): - skip =3D ", { .reg =3D 0 }" - else: - skip =3D "" - - if reg.array: - print("#define %s(__i, ...) pack_%s(__i, __struct_cast(%s) { __VA_ARGS_= _ })%s\n" % - (prefix, prefix, prefix, skip)) - else: - print("#define %s(...) pack_%s(__struct_cast(%s) { __VA_ARGS__ })%s\n" % - (prefix, prefix, prefix, skip)) - - - def dump(self, is_deprecated, prefix=3DNone, reg=3DNone): - if prefix is None: - prefix =3D self.name - reg64 =3D reg and self.reg and self.reg.bit_size =3D=3D 64 - if reg64: - print("static inline uint32_t %s_LO(uint32_t val)\n{" % prefix) - print("\treturn val;\n}") - print("static inline uint32_t %s_HI(uint32_t val)\n{" % prefix) - print("\treturn val;\n}") - for f in self.fields: - if f.name: - name =3D prefix + "_" + f.name - else: - name =3D prefix - - if not f.name and f.low =3D=3D 0 and f.shr =3D=3D 0 and f.type not in [= "float", "fixed", "ufixed"]: - pass - elif f.type =3D=3D "boolean" or (f.type is None and f.low =3D=3D f.high= ): - tab_to("#define %s" % name, "0x%08x" % (1 << f.low)) - else: - typespec =3D "ull" if reg64 else "u" - tab_to("#define %s__MASK" % name, "0x%08x%s" % (mask(f.low, f.high), t= ypespec)) - tab_to("#define %s__SHIFT" % name, "%d" % f.low) - type, val =3D f.ctype("val") - ret_type =3D "uint64_t" if reg64 else "uint32_t" - cast =3D "(uint64_t)" if reg64 else "" - - print("static inline %s %s(%s val)\n{" % (ret_type, name, type)) - if f.shr > 0: - print("\tassert(!(val & 0x%x));" % mask(0, f.shr - 1)) - print("\treturn (%s(%s) << %s__SHIFT) & %s__MASK;\n}" % (cast, val, na= me, name)) - print() + def __init__(self, name, template): + self.name =3D name + self.inline =3D False + self.reg =3D None + if template: + self.fields =3D template.fields[:] + else: + self.fields =3D [] + + # Get address field if there is one in the bitset, else return None: + def get_address_field(self): + for f in self.fields: + if f.type in ["address", "waddress"]: + return f + return None + + def dump_regpair_builder(self, reg): + print("#ifndef NDEBUG") + known_mask =3D 0 + for f in self.fields: + known_mask |=3D mask(f.low, f.high) + if f.type in ["boolean", "address", "waddress"]: + continue + type, val =3D f.ctype("fields.%s" % field_name(reg, f)) + print(" assert((%-40s & 0x%08x) =3D=3D 0);" % + (val, 0xffffffff ^ mask(0, f.high - f.low))) + print(" assert((%-40s & 0x%08x) =3D=3D 0);" % + ("fields.unknown", known_mask)) + print("#endif\n") + + print(" return (struct fd_reg_pair) {") + print(" .reg =3D (uint32_t)%s," % reg.reg_offset()) + print(" .value =3D") + cast =3D "(uint64_t)" if reg.bit_size =3D=3D 64 else "" + for f in self.fields: + if f.type in ["address", "waddress"]: + continue + else: + type, val =3D f.ctype("fields.%s" % field_name(reg, f)) + print(" (%s%-40s << %2d) |" % (cast, val, f.low= )) + value_name =3D "dword" + if reg.bit_size =3D=3D 64: + value_name =3D "qword" + print(" fields.unknown | fields.%s," % (value_name,)) + + address =3D self.get_address_field() + if address: + print("#ifndef TU_CS_H") + print(" .bo =3D fields.bo,") + print(" .is_address =3D true,") + print(" .bo_offset =3D fields.bo_offset,") + print(" .bo_shift =3D %d," % address.shr) + print(" .bo_low =3D %d," % address.low) + print("#else") + print(" .is_address =3D true,") + print("#endif") + + print(" };") + + def dump_pack_struct(self, has_variants, reg=3DNone): + if not reg: + return + + prefix =3D reg.full_name + + constexpr_mark =3D " CONSTEXPR" + + print("struct %s {" % prefix) + for f in self.fields: + if f.type in ["address", "waddress"]: + print("#ifndef TU_CS_H") + tab_to(" __bo_type", "bo;") + tab_to(" uint32_t", "bo_offset;") + print("#endif\n") + continue + name =3D field_name(reg, f) + + type, val =3D f.ctype("var") + + tab_to(" %s" % type, "%s;" % name) + + if f.type =3D=3D "float": + # Requires using `fui()` or `_mesa_float_to_half()` + constexpr_mark =3D "" + if reg.bit_size =3D=3D 64: + tab_to(" uint64_t", "qword;") + tab_to(" uint64_t", "unknown;") + else: + tab_to(" uint32_t", "dword;") + tab_to(" uint32_t", "unknown;") + print("};\n") + + if not has_variants: + print("static%s inline struct fd_reg_pair" % constexpr_mark) + if reg.array: + print("pack_%s(uint32_t __i, struct %s fields)\n{" % (pref= ix, prefix)) + else: + print("pack_%s(struct %s fields)\n{" % (prefix, prefix)) + + self.dump_regpair_builder(reg) + + print("\n}\n") + + if self.get_address_field(): + skip =3D ", { .reg =3D 0 }" + else: + skip =3D "" + + if reg.array: + print("#define %s(__i, ...) pack_%s(__i, __struct_cast(%s) { _= _VA_ARGS__ })%s\n" % + (prefix, prefix, prefix, skip)) + else: + print("#define %s(...) pack_%s(__struct_cast(%s) { __VA_ARGS__= })%s\n" % + (prefix, prefix, prefix, skip)) + + def dump(self, has_variants, prefix=3DNone, reg=3DNone): + if prefix is None: + prefix =3D self.name + suffix =3D "" + if self.reg and self.reg.bit_size =3D=3D 64: + print( + "static CONSTEXPR inline uint32_t %s_LO(uint32_t val)\n{" = % prefix) + print("\treturn val;\n}") + print( + "static CONSTEXPR inline uint32_t %s_HI(uint32_t val)\n{" = % prefix) + print("\treturn val;\n}") + suffix =3D "ull" + + for f in self.fields: + if f.name: + name =3D prefix + "_" + f.name + else: + name =3D prefix + + if not f.name and f.low =3D=3D 0 and f.shr =3D=3D 0 and f.type= not in ["float", "fixed", "ufixed"]: + pass + elif f.type =3D=3D "boolean" or (f.type is None and f.low =3D= =3D f.high): + tab_to("#define %s" % name, "0x%08x%s" % ((1 << f.low), su= ffix)) + else: + tab_to("#define %s__MASK" % + name, "0x%08x%s" % (mask(f.low, f.high), suffix)) + tab_to("#define %s__SHIFT" % name, "%d" % f.low) + type, val =3D f.ctype("val") + ret_type =3D "uint64_t" if reg and reg.bit_size =3D=3D 64 = else "uint32_t" + cast =3D "(uint64_t)" if reg and reg.bit_size =3D=3D 64 el= se "" + + constexpr_mark =3D "" if type =3D=3D "float" else " CONSTE= XPR" + print("static%s inline %s %s(%s val)\n{" % ( + constexpr_mark, ret_type, name, type)) + if f.shr > 0: + print("\tassert(!(val & 0x%x));" % mask(0, f.shr - 1)) + print("\treturn (%s(%s) << %s__SHIFT) & %s__MASK;\n}" % + (cast, val, name, name)) + print() + =20 class Array(object): - def __init__(self, attrs, domain, variant, parent, index_type): - if "name" in attrs: - self.local_name =3D attrs["name"] - else: - self.local_name =3D "" - self.domain =3D domain - self.variant =3D variant - self.parent =3D parent - self.children =3D [] - if self.parent: - self.name =3D self.parent.name + "_" + self.local_name - else: - self.name =3D self.local_name - if "offsets" in attrs: - self.offsets =3D map(lambda i: "0x%08x" % int(i, 0), attrs["offsets"].s= plit(",")) - self.fixed_offsets =3D True - elif "doffsets" in attrs: - self.offsets =3D map(lambda s: "(%s)" % s , attrs["doffsets"].split(","= )) - self.fixed_offsets =3D True - else: - self.offset =3D int(attrs["offset"], 0) - self.stride =3D int(attrs["stride"], 0) - self.fixed_offsets =3D False - if "index" in attrs: - self.index_type =3D index_type - else: - self.index_type =3D None - self.length =3D int(attrs["length"], 0) - if "usage" in attrs: - self.usages =3D attrs["usage"].split(',') - else: - self.usages =3D None - - def index_ctype(self): - if not self.index_type: - return "uint32_t" - else: - return "enum %s" % self.index_type.name - - # Generate array of (ctype, stride, __offsets_NAME) - def indices(self): - if self.parent: - indices =3D self.parent.indices() - else: - indices =3D [] - if self.length !=3D 1: - if self.fixed_offsets: - indices.append((self.index_ctype(), None, "__offset_%s" % self.local_n= ame)) - else: - indices.append((self.index_ctype(), self.stride, None)) - return indices - - def total_offset(self): - offset =3D 0 - if not self.fixed_offsets: - offset +=3D self.offset - if self.parent: - offset +=3D self.parent.total_offset() - return offset - - def dump(self, is_deprecated): - depcrstr =3D "" - if is_deprecated: - depcrstr =3D " FD_DEPRECATED" - proto =3D indices_varlist(self.indices()) - strides =3D indices_strides(self.indices()) - array_offset =3D self.total_offset() - if self.fixed_offsets: - print("static inline%s uint32_t __offset_%s(%s idx)" % (depcrstr, self.= local_name, self.index_ctype())) - print("{\n\tswitch (idx) {") - if self.index_type: - for val, offset in zip(self.index_type.names(), self.offsets): - print("\t\tcase %s: return %s;" % (val, offset)) - else: - for idx, offset in enumerate(self.offsets): - print("\t\tcase %d: return %s;" % (idx, offset)) - print("\t\tdefault: return INVALID_IDX(idx);") - print("\t}\n}") - if proto =3D=3D '': - tab_to("#define REG_%s_%s" % (self.domain, self.name), "0x%08x\n" % arr= ay_offset) - else: - tab_to("#define REG_%s_%s(%s)" % (self.domain, self.name, proto), "(0x%= 08x + %s )\n" % (array_offset, strides)) - - def dump_pack_struct(self, is_deprecated): - pass - - def dump_regpair_builder(self): - pass + def __init__(self, attrs, domain, variant, parent, index_type): + if "name" in attrs: + self.local_name =3D attrs["name"] + else: + self.local_name =3D "" + self.domain =3D domain + self.variant =3D variant + self.parent =3D parent + self.children =3D [] + if self.parent: + self.name =3D self.parent.name + "_" + self.local_name + else: + self.name =3D self.local_name + if "offsets" in attrs: + self.offsets =3D map(lambda i: "0x%08x" % + int(i, 0), attrs["offsets"].split(",")) + self.fixed_offsets =3D True + elif "doffsets" in attrs: + self.offsets =3D map(lambda s: "(%s)" % + s, attrs["doffsets"].split(",")) + self.fixed_offsets =3D True + else: + self.offset =3D int(attrs["offset"], 0) + self.stride =3D int(attrs["stride"], 0) + self.fixed_offsets =3D False + if "index" in attrs: + self.index_type =3D index_type + else: + self.index_type =3D None + self.length =3D int(attrs["length"], 0) + if "usage" in attrs: + self.usages =3D attrs["usage"].split(',') + else: + self.usages =3D None + + def index_ctype(self): + if not self.index_type: + return "uint32_t" + else: + return "enum %s" % self.index_type.name + + # Generate array of (ctype, stride, __offsets_NAME) + def indices(self): + if self.parent: + indices =3D self.parent.indices() + else: + indices =3D [] + if self.length !=3D 1: + if self.fixed_offsets: + indices.append((self.index_ctype(), None, + "__offset_%s" % self.local_name)) + else: + indices.append((self.index_ctype(), self.stride, None)) + return indices + + def total_offset(self): + offset =3D 0 + if not self.fixed_offsets: + offset +=3D self.offset + if self.parent: + offset +=3D self.parent.total_offset() + return offset + + def dump(self, has_variants): + proto =3D indices_varlist(self.indices()) + strides =3D indices_strides(self.indices()) + array_offset =3D self.total_offset() + if self.fixed_offsets and not has_variants: + print("static CONSTEXPR inline uint32_t __offset_%s(%s idx)" % + (self.local_name, self.index_ctype())) + print("{\n\tswitch (idx) {") + if self.index_type: + for val, offset in zip(self.index_type.names(), self.offse= ts): + print("\t\tcase %s: return %s;" % (val, offset)) + else: + for idx, offset in enumerate(self.offsets): + print("\t\tcase %d: return %s;" % (idx, offset)) + print("\t\tdefault: return INVALID_IDX(idx);") + print("\t}\n}") + if proto =3D=3D '': + define_macro("#define REG_%s_%s" % + (self.domain, self.name), "0x%08x\n" % array_offs= et, + has_variants) + else: + define_macro("#define REG_%s_%s(%s)" % (self.domain, self.name, + proto), "(0x%08x + %s )\n" % (array_offset, strid= es), + has_variants) + + def dump_pack_struct(self, has_variants): + pass + + def dump_regpair_builder(self): + pass + =20 class Reg(object): - def __init__(self, attrs, domain, array, bit_size): - self.name =3D attrs["name"] - self.domain =3D domain - self.array =3D array - self.offset =3D int(attrs["offset"], 0) - self.type =3D None - self.bit_size =3D bit_size - if array: - self.name =3D array.name + "_" + self.name - array.children.append(self) - self.full_name =3D self.domain + "_" + self.name - if "stride" in attrs: - self.stride =3D int(attrs["stride"], 0) - self.length =3D int(attrs["length"], 0) - else: - self.stride =3D None - self.length =3D None - - # Generate array of (ctype, stride, __offsets_NAME) - def indices(self): - if self.array: - indices =3D self.array.indices() - else: - indices =3D [] - if self.stride: - indices.append(("uint32_t", self.stride, None)) - return indices - - def total_offset(self): - if self.array: - return self.array.total_offset() + self.offset - else: - return self.offset - - def reg_offset(self): - if self.array: - offset =3D self.array.offset + self.offset - return "(0x%08x + 0x%x*__i)" % (offset, self.array.stride) - return "0x%08x" % self.offset - - def dump(self, is_deprecated): - depcrstr =3D "" - if is_deprecated: - depcrstr =3D " FD_DEPRECATED " - proto =3D indices_prototype(self.indices()) - strides =3D indices_strides(self.indices()) - offset =3D self.total_offset() - if proto =3D=3D '': - tab_to("#define REG_%s" % self.full_name, "0x%08x" % offset) - else: - print("static inline%s uint32_t REG_%s(%s) { return 0x%08x + %s; }" % (= depcrstr, self.full_name, proto, offset, strides)) - - if self.bitset.inline: - self.bitset.dump(is_deprecated, self.full_name, self) - print("") - - def dump_pack_struct(self, is_deprecated): - if self.bitset.inline: - self.bitset.dump_pack_struct(is_deprecated, self) - - def dump_regpair_builder(self): - self.bitset.dump_regpair_builder(self) - - def dump_py(self): - print("\tREG_%s =3D 0x%08x" % (self.full_name, self.offset)) + def __init__(self, attrs, domain, array, bit_size): + self.name =3D attrs["name"] + self.domain =3D domain + self.array =3D array + self.offset =3D int(attrs["offset"], 0) + self.type =3D None + self.bit_size =3D bit_size + if array: + self.name =3D array.name + "_" + self.name + array.children.append(self) + self.full_name =3D self.domain + "_" + self.name + if "stride" in attrs: + self.stride =3D int(attrs["stride"], 0) + self.length =3D int(attrs["length"], 0) + else: + self.stride =3D None + self.length =3D None + + # Generate array of (ctype, stride, __offsets_NAME) + def indices(self): + if self.array: + indices =3D self.array.indices() + else: + indices =3D [] + if self.stride: + indices.append(("uint32_t", self.stride, None)) + return indices + + def total_offset(self): + if self.array: + return self.array.total_offset() + self.offset + else: + return self.offset + + def reg_offset(self): + if self.array: + offset =3D self.array.offset + self.offset + return "(0x%08x + 0x%x*__i)" % (offset, self.array.stride) + return "0x%08x" % self.offset + + def dump(self, has_variants): + proto =3D indices_prototype(self.indices()) + strides =3D indices_strides(self.indices()) + offset =3D self.total_offset() + if proto =3D=3D '': + define_macro("#define REG_%s" % self.full_name, "0x%08x" % off= set, has_variants) + elif not has_variants: + depcrstr =3D "" + if has_variants: + depcrstr =3D " __FD_DEPRECATED " + print("static CONSTEXPR inline%s uint32_t REG_%s(%s) { return = 0x%08x + %s; }" % ( + depcrstr, self.full_name, proto, offset, strides)) + + if self.bitset.inline: + self.bitset.dump(has_variants, self.full_name, self) + print("") + + def dump_pack_struct(self, has_variants): + if self.bitset.inline: + self.bitset.dump_pack_struct(has_variants, self) + + def dump_regpair_builder(self): + self.bitset.dump_regpair_builder(self) + + def dump_py(self): + offset =3D self.offset + if self.array: + offset +=3D self.array.offset + print("\tREG_%s =3D 0x%08x" % (self.full_name, offset)) =20 =20 class Parser(object): - def __init__(self): - self.current_array =3D None - self.current_domain =3D None - self.current_prefix =3D None - self.current_prefix_type =3D None - self.current_stripe =3D None - self.current_bitset =3D None - self.current_bitsize =3D 32 - # The varset attribute on the domain specifies the enum which - # specifies all possible hw variants: - self.current_varset =3D None - # Regs that have multiple variants.. we only generated the C++ - # template based struct-packers for these - self.variant_regs =3D {} - # Information in which contexts regs are used, to be used in - # debug options - self.usage_regs =3D collections.defaultdict(list) - self.bitsets =3D {} - self.enums =3D {} - self.variants =3D set() - self.file =3D [] - self.xml_files =3D [] - - def error(self, message): - parser, filename =3D self.stack[-1] - return Error("%s:%d:%d: %s" % (filename, parser.CurrentLineNumber, parse= r.CurrentColumnNumber, message)) - - def prefix(self, variant=3DNone): - if self.current_prefix_type =3D=3D "variant" and variant: - return sanitize_variant(variant) - elif self.current_stripe: - return self.current_stripe + "_" + self.current_domain - elif self.current_prefix: - return self.current_prefix + "_" + self.current_domain - else: - return self.current_domain - - def parse_field(self, name, attrs): - try: - if "pos" in attrs: - high =3D low =3D int(attrs["pos"], 0) - elif "high" in attrs and "low" in attrs: - high =3D int(attrs["high"], 0) - low =3D int(attrs["low"], 0) - else: - low =3D 0 - high =3D self.current_bitsize - 1 - - if "type" in attrs: - type =3D attrs["type"] - else: - type =3D None - - if "shr" in attrs: - shr =3D int(attrs["shr"], 0) - else: - shr =3D 0 - - b =3D Field(name, low, high, shr, type, self) - - if type =3D=3D "fixed" or type =3D=3D "ufixed": - b.radix =3D int(attrs["radix"], 0) - - self.current_bitset.fields.append(b) - except ValueError as e: - raise self.error(e) - - def parse_varset(self, attrs): - # Inherit the varset from the enclosing domain if not overriden: - varset =3D self.current_varset - if "varset" in attrs: - varset =3D self.enums[attrs["varset"]] - return varset - - def parse_variants(self, attrs): - if "variants" not in attrs: - return None - - variant =3D attrs["variants"].split(",")[0] - varset =3D self.parse_varset(attrs) - - if "-" in variant: - # if we have a range, validate that both the start and end - # of the range are valid enums: - start =3D variant[:variant.index("-")] - end =3D variant[variant.index("-") + 1:] - assert varset.has_name(start) - if end !=3D "": - assert varset.has_name(end) - else: - assert varset.has_name(variant) - - return variant - - def add_all_variants(self, reg, attrs, parent_variant): - # TODO this should really handle *all* variants, including dealing - # with open ended ranges (ie. "A2XX,A4XX-") (we have the varset - # enum now to make that possible) - variant =3D self.parse_variants(attrs) - if not variant: - variant =3D parent_variant - - if reg.name not in self.variant_regs: - self.variant_regs[reg.name] =3D {} - else: - # All variants must be same size: - v =3D next(iter(self.variant_regs[reg.name])) - assert self.variant_regs[reg.name][v].bit_size =3D=3D reg.bit_size - - self.variant_regs[reg.name][variant] =3D reg - - def add_all_usages(self, reg, usages): - if not usages: - return - - for usage in usages: - self.usage_regs[usage].append(reg) - - self.variants.add(reg.domain) - - def do_validate(self, schemafile): - if not self.validate: - return - - try: - from lxml import etree - - parser, filename =3D self.stack[-1] - dirname =3D os.path.dirname(filename) - - # we expect this to look like schema.xsd.. I think - # technically it is supposed to be just a URL, but that doesn't - # quite match up to what we do.. Just skip over everything up to - # and including the first whitespace character: - schemafile =3D schemafile[schemafile.rindex(" ")+1:] - - # this is a bit cheezy, but the xml file to validate could be - # in a child director, ie. we don't really know where the schema - # file is, the way the rnn C code does. So if it doesn't exist - # just look one level up - if not os.path.exists(dirname + "/" + schemafile): - schemafile =3D "../" + schemafile - - if not os.path.exists(dirname + "/" + schemafile): - raise self.error("Cannot find schema for: " + filename) - - xmlschema_doc =3D etree.parse(dirname + "/" + schemafile) - xmlschema =3D etree.XMLSchema(xmlschema_doc) - - xml_doc =3D etree.parse(filename) - if not xmlschema.validate(xml_doc): - error_str =3D str(xmlschema.error_log.filter_from_errors()[0]) - raise self.error("Schema validation failed for: " + filename + "\n" + = error_str) - except ImportError as e: - print("lxml not found, skipping validation", file=3Dsys.stderr) - - def do_parse(self, filename): - filepath =3D os.path.abspath(filename) - if filepath in self.xml_files: - return - self.xml_files.append(filepath) - file =3D open(filename, "rb") - parser =3D xml.parsers.expat.ParserCreate() - self.stack.append((parser, filename)) - parser.StartElementHandler =3D self.start_element - parser.EndElementHandler =3D self.end_element - parser.CharacterDataHandler =3D self.character_data - parser.buffer_text =3D True - parser.ParseFile(file) - self.stack.pop() - file.close() - - def parse(self, rnn_path, filename, validate): - self.path =3D rnn_path - self.stack =3D [] - self.validate =3D validate - self.do_parse(filename) - - def parse_reg(self, attrs, bit_size): - self.current_bitsize =3D bit_size - if "type" in attrs and attrs["type"] in self.bitsets: - bitset =3D self.bitsets[attrs["type"]] - if bitset.inline: - self.current_bitset =3D Bitset(attrs["name"], bitset) - self.current_bitset.inline =3D True - else: - self.current_bitset =3D bitset - else: - self.current_bitset =3D Bitset(attrs["name"], None) - self.current_bitset.inline =3D True - if "type" in attrs: - self.parse_field(None, attrs) - - variant =3D self.parse_variants(attrs) - if not variant and self.current_array: - variant =3D self.current_array.variant - - self.current_reg =3D Reg(attrs, self.prefix(variant), self.current_array= , bit_size) - self.current_reg.bitset =3D self.current_bitset - self.current_bitset.reg =3D self.current_reg - - if len(self.stack) =3D=3D 1: - self.file.append(self.current_reg) - - if variant is not None: - self.add_all_variants(self.current_reg, attrs, variant) - - usages =3D None - if "usage" in attrs: - usages =3D attrs["usage"].split(',') - elif self.current_array: - usages =3D self.current_array.usages - - self.add_all_usages(self.current_reg, usages) - - def start_element(self, name, attrs): - self.cdata =3D "" - if name =3D=3D "import": - filename =3D attrs["file"] - self.do_parse(os.path.join(self.path, filename)) - elif name =3D=3D "domain": - self.current_domain =3D attrs["name"] - if "prefix" in attrs: - self.current_prefix =3D sanitize_variant(self.parse_variants(attrs)) - self.current_prefix_type =3D attrs["prefix"] - else: - self.current_prefix =3D None - self.current_prefix_type =3D None - if "varset" in attrs: - self.current_varset =3D self.enums[attrs["varset"]] - elif name =3D=3D "stripe": - self.current_stripe =3D sanitize_variant(self.parse_variants(attrs)) - elif name =3D=3D "enum": - self.current_enum_value =3D 0 - self.current_enum =3D Enum(attrs["name"]) - self.enums[attrs["name"]] =3D self.current_enum - if len(self.stack) =3D=3D 1: - self.file.append(self.current_enum) - elif name =3D=3D "value": - if "value" in attrs: - value =3D int(attrs["value"], 0) - else: - value =3D self.current_enum_value - self.current_enum.values.append((attrs["name"], value)) - elif name =3D=3D "reg32": - self.parse_reg(attrs, 32) - elif name =3D=3D "reg64": - self.parse_reg(attrs, 64) - elif name =3D=3D "array": - self.current_bitsize =3D 32 - variant =3D self.parse_variants(attrs) - index_type =3D self.enums[attrs["index"]] if "index" in attrs else None - self.current_array =3D Array(attrs, self.prefix(variant), variant, self= .current_array, index_type) - if len(self.stack) =3D=3D 1: - self.file.append(self.current_array) - elif name =3D=3D "bitset": - self.current_bitset =3D Bitset(attrs["name"], None) - if "inline" in attrs and attrs["inline"] =3D=3D "yes": - self.current_bitset.inline =3D True - self.bitsets[self.current_bitset.name] =3D self.current_bitset - if len(self.stack) =3D=3D 1 and not self.current_bitset.inline: - self.file.append(self.current_bitset) - elif name =3D=3D "bitfield" and self.current_bitset: - self.parse_field(attrs["name"], attrs) - elif name =3D=3D "database": - self.do_validate(attrs["xsi:schemaLocation"]) - - def end_element(self, name): - if name =3D=3D "domain": - self.current_domain =3D None - self.current_prefix =3D None - self.current_prefix_type =3D None - elif name =3D=3D "stripe": - self.current_stripe =3D None - elif name =3D=3D "bitset": - self.current_bitset =3D None - elif name =3D=3D "reg32": - self.current_reg =3D None - elif name =3D=3D "array": - # if the array has no Reg children, push an implicit reg32: - if len(self.current_array.children) =3D=3D 0: - attrs =3D { - "name": "REG", - "offset": "0", - } - self.parse_reg(attrs, 32) - self.current_array =3D self.current_array.parent - elif name =3D=3D "enum": - self.current_enum =3D None - - def character_data(self, data): - self.cdata +=3D data - - def dump_reg_usages(self): - d =3D collections.defaultdict(list) - for usage, regs in self.usage_regs.items(): - for reg in regs: - variants =3D self.variant_regs.get(reg.name) - if variants: - for variant, vreg in variants.items(): - if reg =3D=3D vreg: - d[(usage, sanitize_variant(variant))].append(reg) - else: - for variant in self.variants: - d[(usage, sanitize_variant(variant))].append(reg) - - print("#ifdef __cplusplus") - - for usage, regs in self.usage_regs.items(): - print("template constexpr inline uint16_t %s_REGS[] =3D {};"= % (usage.upper())) - - for (usage, variant), regs in d.items(): - offsets =3D [] - - for reg in regs: - if reg.array: - for i in range(reg.array.length): - offsets.append(reg.array.offset + reg.offset + i * reg.array.stride) - if reg.bit_size =3D=3D 64: - offsets.append(offsets[-1] + 1) - else: - offsets.append(reg.offset) - if reg.bit_size =3D=3D 64: - offsets.append(offsets[-1] + 1) - - offsets.sort() - - print("template<> constexpr inline uint16_t %s_REGS<%s>[] =3D {" % (usa= ge.upper(), variant)) - for offset in offsets: - print("\t%s," % hex(offset)) - print("};") - - print("#endif") - - def has_variants(self, reg): - return reg.name in self.variant_regs and not is_number(reg.name) and not= is_number(reg.name[1:]) - - def dump(self): - enums =3D [] - bitsets =3D [] - regs =3D [] - for e in self.file: - if isinstance(e, Enum): - enums.append(e) - elif isinstance(e, Bitset): - bitsets.append(e) - else: - regs.append(e) - - for e in enums + bitsets + regs: - e.dump(self.has_variants(e)) - - self.dump_reg_usages() - - - def dump_regs_py(self): - regs =3D [] - for e in self.file: - if isinstance(e, Reg): - regs.append(e) - - for e in regs: - e.dump_py() - - - def dump_reg_variants(self, regname, variants): - if is_number(regname) or is_number(regname[1:]): - return - print("#ifdef __cplusplus") - print("struct __%s {" % regname) - # TODO be more clever.. we should probably figure out which - # fields have the same type in all variants (in which they - # appear) and stuff everything else in a variant specific - # sub-structure. - seen_fields =3D [] - bit_size =3D 32 - array =3D False - address =3D None - for variant in variants.keys(): - print(" /* %s fields: */" % variant) - reg =3D variants[variant] - bit_size =3D reg.bit_size - array =3D reg.array - for f in reg.bitset.fields: - fld_name =3D field_name(reg, f) - if fld_name in seen_fields: - continue - seen_fields.append(fld_name) - name =3D fld_name.lower() - if f.type in [ "address", "waddress" ]: - if address: - continue - address =3D f - tab_to(" __bo_type", "bo;") - tab_to(" uint32_t", "bo_offset;") - continue - type, val =3D f.ctype("var") - tab_to(" %s" %type, "%s;" %name) - print(" /* fallback fields: */") - if bit_size =3D=3D 64: - tab_to(" uint64_t", "unknown;") - tab_to(" uint64_t", "qword;") - else: - tab_to(" uint32_t", "unknown;") - tab_to(" uint32_t", "dword;") - print("};") - # TODO don't hardcode the varset enum name - varenum =3D "chip" - print("template <%s %s>" % (varenum, varenum.upper())) - print("static inline struct fd_reg_pair") - xtra =3D "" - xtravar =3D "" - if array: - xtra =3D "int __i, " - xtravar =3D "__i, " - print("__%s(%sstruct __%s fields) {" % (regname, xtra, regname)) - for variant in variants.keys(): - if "-" in variant: - start =3D variant[:variant.index("-")] - end =3D variant[variant.index("-") + 1:] - if end !=3D "": - print(" if ((%s >=3D %s) && (%s <=3D %s)) {" % (varenum.upper(), sta= rt, varenum.upper(), end)) - else: - print(" if (%s >=3D %s) {" % (varenum.upper(), start)) - else: - print(" if (%s =3D=3D %s) {" % (varenum.upper(), variant)) - reg =3D variants[variant] - reg.dump_regpair_builder() - print(" } else") - print(" assert(!\"invalid variant\");") - print(" return (struct fd_reg_pair){};") - print("}") - - if bit_size =3D=3D 64: - skip =3D ", { .reg =3D 0 }" - else: - skip =3D "" - - print("#define %s(VARIANT, %s...) __%s(%s{__VA_ARGS__})%s" % (r= egname, xtravar, regname, xtravar, skip)) - print("#endif /* __cplusplus */") - - def dump_structs(self): - for e in self.file: - e.dump_pack_struct(self.has_variants(e)) - - for regname in self.variant_regs: - self.dump_reg_variants(regname, self.variant_regs[regname]) + def __init__(self): + self.current_array =3D None + self.current_domain =3D None + self.current_prefix =3D None + self.current_prefix_type =3D None + self.current_stripe =3D None + self.current_bitset =3D None + self.current_bitsize =3D 32 + # The varset attribute on the domain specifies the enum which + # specifies all possible hw variants: + self.current_varset =3D None + # Regs that have multiple variants.. we only generated the C++ + # template based struct-packers for these + self.variant_regs =3D {} + # Information in which contexts regs are used, to be used in + # debug options + self.usage_regs =3D collections.defaultdict(list) + self.bitsets =3D {} + self.enums =3D {} + self.variants =3D set() + self.file =3D [] + self.xml_files =3D [] + + def error(self, message): + parser, filename =3D self.stack[-1] + return Error("%s:%d:%d: %s" % (filename, parser.CurrentLineNumber,= parser.CurrentColumnNumber, message)) + + def prefix(self, variant=3DNone): + if self.current_prefix_type =3D=3D "variant" and variant: + return sanitize_variant(variant) + elif self.current_stripe: + return self.current_stripe + "_" + self.current_domain + elif self.current_prefix: + return self.current_prefix + "_" + self.current_domain + else: + return self.current_domain + + def parse_field(self, name, attrs): + try: + if "pos" in attrs: + high =3D low =3D int(attrs["pos"], 0) + elif "high" in attrs and "low" in attrs: + high =3D int(attrs["high"], 0) + low =3D int(attrs["low"], 0) + else: + low =3D 0 + high =3D self.current_bitsize - 1 + + if "type" in attrs: + type =3D attrs["type"] + else: + type =3D None + + if "shr" in attrs: + shr =3D int(attrs["shr"], 0) + else: + shr =3D 0 + + b =3D Field(name, low, high, shr, type, self) + + if type =3D=3D "fixed" or type =3D=3D "ufixed": + b.radix =3D int(attrs["radix"], 0) + + self.current_bitset.fields.append(b) + except ValueError as e: + raise self.error(e) + + def parse_varset(self, attrs): + # Inherit the varset from the enclosing domain if not overriden: + varset =3D self.current_varset + if "varset" in attrs: + varset =3D self.enums[attrs["varset"]] + return varset + + def parse_variants(self, attrs): + if "variants" not in attrs: + return None + + variant =3D attrs["variants"].split(",")[0] + varset =3D self.parse_varset(attrs) + + if "-" in variant: + # if we have a range, validate that both the start and end + # of the range are valid enums: + start =3D variant[:variant.index("-")] + end =3D variant[variant.index("-") + 1:] + assert varset.has_name(start) + if end !=3D "": + assert varset.has_name(end) + else: + assert varset.has_name(variant) + + return variant + + def add_all_variants(self, reg, attrs, parent_variant): + # TODO this should really handle *all* variants, including dealing + # with open ended ranges (ie. "A2XX,A4XX-") (we have the varset + # enum now to make that possible) + variant =3D self.parse_variants(attrs) + if not variant: + variant =3D parent_variant + + if reg.name not in self.variant_regs: + self.variant_regs[reg.name] =3D {} + else: + # All variants must be same size: + v =3D next(iter(self.variant_regs[reg.name])) + assert self.variant_regs[reg.name][v].bit_size =3D=3D reg.bit_= size + + self.variant_regs[reg.name][variant] =3D reg + + def add_all_usages(self, reg, usages): + if not usages: + return + + for usage in usages: + self.usage_regs[usage].append(reg) + + self.variants.add(reg.domain) + + def do_validate(self, schemafile): + if not self.validate: + return + + try: + from lxml import etree + + parser, filename =3D self.stack[-1] + dirname =3D os.path.dirname(filename) + + # we expect this to look like schema.xsd.. I t= hink + # technically it is supposed to be just a URL, but that doesn't + # quite match up to what we do.. Just skip over everything up = to + # and including the first whitespace character: + schemafile =3D schemafile[schemafile.rindex(" ")+1:] + + # this is a bit cheezy, but the xml file to validate could be + # in a child director, ie. we don't really know where the sche= ma + # file is, the way the rnn C code does. So if it doesn't exist + # just look one level up + if not os.path.exists(dirname + "/" + schemafile): + schemafile =3D "../" + schemafile + + if not os.path.exists(dirname + "/" + schemafile): + raise self.error("Cannot find schema for: " + filename) + + xmlschema_doc =3D etree.parse(dirname + "/" + schemafile) + xmlschema =3D etree.XMLSchema(xmlschema_doc) + + xml_doc =3D etree.parse(filename) + if not xmlschema.validate(xml_doc): + error_str =3D str(xmlschema.error_log.filter_from_errors()= [0]) + raise self.error( + "Schema validation failed for: " + filename + "\n" + e= rror_str) + except ImportError as e: + print("lxml not found, skipping validation", file=3Dsys.stderr) + + def do_parse(self, filename): + filepath =3D os.path.abspath(filename) + if filepath in self.xml_files: + return + self.xml_files.append(filepath) + file =3D open(filename, "rb") + parser =3D xml.parsers.expat.ParserCreate() + self.stack.append((parser, filename)) + parser.StartElementHandler =3D self.start_element + parser.EndElementHandler =3D self.end_element + parser.CharacterDataHandler =3D self.character_data + parser.buffer_text =3D True + parser.ParseFile(file) + self.stack.pop() + file.close() + + def parse(self, rnn_path, filename, validate): + self.path =3D rnn_path + self.stack =3D [] + self.validate =3D validate + self.do_parse(filename) + + def parse_reg(self, attrs, bit_size): + self.current_bitsize =3D bit_size + if "type" in attrs and attrs["type"] in self.bitsets: + bitset =3D self.bitsets[attrs["type"]] + if bitset.inline: + self.current_bitset =3D Bitset(attrs["name"], bitset) + self.current_bitset.inline =3D True + else: + self.current_bitset =3D bitset + else: + self.current_bitset =3D Bitset(attrs["name"], None) + self.current_bitset.inline =3D True + if "type" in attrs: + self.parse_field(None, attrs) + + variant =3D self.parse_variants(attrs) + if not variant and self.current_array: + variant =3D self.current_array.variant + + self.current_reg =3D Reg(attrs, self.prefix( + variant), self.current_array, bit_size) + self.current_reg.bitset =3D self.current_bitset + self.current_bitset.reg =3D self.current_reg + + if len(self.stack) =3D=3D 1: + self.file.append(self.current_reg) + + if variant is not None: + self.add_all_variants(self.current_reg, attrs, variant) + + usages =3D None + if "usage" in attrs: + usages =3D attrs["usage"].split(',') + elif self.current_array: + usages =3D self.current_array.usages + + self.add_all_usages(self.current_reg, usages) + + def start_element(self, name, attrs): + self.cdata =3D "" + if name =3D=3D "import": + filename =3D attrs["file"] + self.do_parse(os.path.join(self.path, filename)) + elif name =3D=3D "domain": + self.current_domain =3D attrs["name"] + if "prefix" in attrs: + self.current_prefix =3D sanitize_variant( + self.parse_variants(attrs)) + self.current_prefix_type =3D attrs["prefix"] + else: + self.current_prefix =3D None + self.current_prefix_type =3D None + if "varset" in attrs: + self.current_varset =3D self.enums[attrs["varset"]] + elif name =3D=3D "stripe": + self.current_stripe =3D sanitize_variant(self.parse_variants(a= ttrs)) + elif name =3D=3D "enum": + self.current_enum_value =3D 0 + self.current_enum =3D Enum(attrs["name"]) + self.enums[attrs["name"]] =3D self.current_enum + if len(self.stack) =3D=3D 1: + self.file.append(self.current_enum) + elif name =3D=3D "value": + if "value" in attrs: + value =3D int(attrs["value"], 0) + else: + value =3D self.current_enum_value + self.current_enum.values.append((attrs["name"], value)) + elif name =3D=3D "reg32": + self.parse_reg(attrs, 32) + elif name =3D=3D "reg64": + self.parse_reg(attrs, 64) + elif name =3D=3D "array": + self.current_bitsize =3D 32 + variant =3D self.parse_variants(attrs) + index_type =3D self.enums[attrs["index"] + ] if "index" in attrs else None + self.current_array =3D Array(attrs, self.prefix( + variant), variant, self.current_array, index_type) + if len(self.stack) =3D=3D 1: + self.file.append(self.current_array) + elif name =3D=3D "bitset": + self.current_bitset =3D Bitset(attrs["name"], None) + if "inline" in attrs and attrs["inline"] =3D=3D "yes": + self.current_bitset.inline =3D True + self.bitsets[self.current_bitset.name] =3D self.current_bitset + if len(self.stack) =3D=3D 1 and not self.current_bitset.inline: + self.file.append(self.current_bitset) + elif name =3D=3D "bitfield" and self.current_bitset: + self.parse_field(attrs["name"], attrs) + elif name =3D=3D "database": + self.do_validate(attrs["xsi:schemaLocation"]) + + def end_element(self, name): + if name =3D=3D "domain": + self.current_domain =3D None + self.current_prefix =3D None + self.current_prefix_type =3D None + elif name =3D=3D "stripe": + self.current_stripe =3D None + elif name =3D=3D "bitset": + self.current_bitset =3D None + elif name =3D=3D "reg32": + self.current_reg =3D None + elif name =3D=3D "array": + # if the array has no Reg children, push an implicit reg32: + if len(self.current_array.children) =3D=3D 0: + attrs =3D { + "name": "REG", + "offset": "0", + } + self.parse_reg(attrs, 32) + self.current_array =3D self.current_array.parent + elif name =3D=3D "enum": + self.current_enum =3D None + + def character_data(self, data): + self.cdata +=3D data + + def dump_reg_usages(self): + d =3D collections.defaultdict(list) + for usage, regs in self.usage_regs.items(): + for reg in regs: + variants =3D self.variant_regs.get(reg.name) + if variants: + for variant, vreg in variants.items(): + if reg =3D=3D vreg: + d[(usage, sanitize_variant(variant))].append(r= eg) + else: + for variant in self.variants: + d[(usage, sanitize_variant(variant))].append(reg) + + print("#ifdef __cplusplus") + + for usage, regs in self.usage_regs.items(): + print("template constexpr inline uint16_t %s_REGS[]= =3D {};" % ( + usage.upper())) + + for (usage, variant), regs in d.items(): + offsets =3D [] + + for reg in regs: + if reg.array: + for i in range(reg.array.length): + offsets.append(reg.array.offset + + reg.offset + i * reg.array.stride) + if reg.bit_size =3D=3D 64: + offsets.append(offsets[-1] + 1) + else: + offsets.append(reg.offset) + if reg.bit_size =3D=3D 64: + offsets.append(offsets[-1] + 1) + + offsets.sort() + + print("template<> constexpr inline uint16_t %s_REGS<%s>[] =3D = {" % ( + usage.upper(), variant)) + for offset in offsets: + print("\t%s," % hex(offset)) + print("};") + + print("#endif") + + def has_variants(self, reg): + return reg.name in self.variant_regs and not is_number(reg.name) a= nd not is_number(reg.name[1:]) + + def dump(self): + enums =3D [] + bitsets =3D [] + regs =3D [] + for e in self.file: + if isinstance(e, Enum): + enums.append(e) + elif isinstance(e, Bitset): + bitsets.append(e) + else: + regs.append(e) + + for e in enums + bitsets + regs: + e.dump(self.has_variants(e)) + + self.dump_reg_usages() + + def dump_regs_py(self): + regs =3D [] + for e in self.file: + if isinstance(e, Reg): + regs.append(e) + + for e in regs: + e.dump_py() + + def dump_reg_variants(self, regname, variants): + if is_number(regname) or is_number(regname[1:]): + return + print("#ifdef __cplusplus") + print("struct __%s {" % regname) + # TODO be more clever.. we should probably figure out which + # fields have the same type in all variants (in which they + # appear) and stuff everything else in a variant specific + # sub-structure. + seen_fields =3D [] + bit_size =3D 32 + array =3D False + address =3D None + constexpr_mark =3D " CONSTEXPR" + for variant in variants.keys(): + print(" /* %s fields: */" % variant) + reg =3D variants[variant] + bit_size =3D reg.bit_size + array =3D reg.array + for f in reg.bitset.fields: + fld_name =3D field_name(reg, f) + if fld_name in seen_fields: + continue + seen_fields.append(fld_name) + name =3D fld_name.lower() + if f.type in ["address", "waddress"]: + if address: + continue + address =3D f + print("#ifndef TU_CS_H") + tab_to(" __bo_type", "bo;") + tab_to(" uint32_t", "bo_offset;") + print("#endif") + continue + type, val =3D f.ctype("var") + tab_to(" %s" % type, "%s;" % name) + if f.type =3D=3D "float": + constexpr_mark =3D "" + print(" /* fallback fields: */") + if bit_size =3D=3D 64: + tab_to(" uint64_t", "unknown;") + tab_to(" uint64_t", "qword;") + else: + tab_to(" uint32_t", "unknown;") + tab_to(" uint32_t", "dword;") + print("};") + # TODO don't hardcode the varset enum name + varenum =3D "chip" + print("template <%s %s>" % (varenum, varenum.upper())) + print("static%s inline struct fd_reg_pair" % (constexpr_mark)) + xtra =3D "" + xtravar =3D "" + if array: + xtra =3D "int __i, " + xtravar =3D "__i, " + print("__%s(%sstruct __%s fields) {" % (regname, xtra, regname)) + for variant in variants.keys(): + if "-" in variant: + start =3D variant[:variant.index("-")] + end =3D variant[variant.index("-") + 1:] + if end !=3D "": + print(" if ((%s >=3D %s) && (%s <=3D %s)) {" % ( + varenum.upper(), start, varenum.upper(), end)) + else: + print(" if (%s >=3D %s) {" % (varenum.upper(), start)) + else: + print(" if (%s =3D=3D %s) {" % (varenum.upper(), variant)) + reg =3D variants[variant] + reg.dump_regpair_builder() + print(" } else") + print(" assert(!\"invalid variant\");") + print(" return (struct fd_reg_pair){};") + print("}") + + if bit_size =3D=3D 64: + skip =3D ", { .reg =3D 0 }" + else: + skip =3D "" + + print("#define %s(VARIANT, %s...) __%s(%s{__VA_ARGS__})%s= " % ( + regname, xtravar, regname, xtravar, skip)) + print("#endif /* __cplusplus */") + + def dump_structs(self): + for e in self.file: + e.dump_pack_struct(self.has_variants(e)) + + for regname in self.variant_regs: + self.dump_reg_variants(regname, self.variant_regs[regname]) =20 =20 def dump_c(args, guard, func): - p =3D Parser() - - try: - p.parse(args.rnn, args.xml, args.validate) - except Error as e: - print(e, file=3Dsys.stderr) - exit(1) - - print("#ifndef %s\n#define %s\n" % (guard, guard)) - - print("/* Autogenerated file, DO NOT EDIT manually! */") - - print() - print("#ifdef __KERNEL__") - print("#include ") - print("#define assert(x) BUG_ON(!(x))") - print("#else") - print("#include ") - print("#endif") - print() - - print("#ifdef __cplusplus") - print("#define __struct_cast(X)") - print("#else") - print("#define __struct_cast(X) (struct X)") - print("#endif") - print() - - print("#ifndef FD_NO_DEPRECATED_PACK") - print("#define FD_DEPRECATED __attribute__((deprecated))") - print("#else") - print("#define FD_DEPRECATED") - print("#endif") - print() - - func(p) - - print() - print("#undef FD_DEPRECATED") - print() - - print("#endif /* %s */" % guard) + p =3D Parser() + + try: + p.parse(args.rnn, args.xml, args.validate) + except Error as e: + print(e, file=3Dsys.stderr) + exit(1) + + print("#ifndef %s\n#define %s\n" % (guard, guard)) + + print("/* Autogenerated file, DO NOT EDIT manually! */") + + print() + print("#ifdef __KERNEL__") + print("#include ") + print("#define assert(x) BUG_ON(!(x))") + print("#else") + print("#include ") + print("#endif") + print() + + print("#ifdef __cplusplus") + print("#define __struct_cast(X)") + print("#define CONSTEXPR constexpr") + print("#else") + print("#define __struct_cast(X) (struct X)") + print("#define CONSTEXPR") + print("#endif") + print() + + # TODO figure out what to do about fd_reg_stomp_allowed() + # vs gcc.. for now only enable the warnings with clang: + print("#if defined(__clang__) && !defined(FD_NO_DEPRECATED_PACK) && !d= efined(__KERNEL__)") + print("#define __FD_DEPRECATED _Pragma (\"GCC warning \\\"Deprecated r= eg builder\\\"\")") + print("#else") + print("#define __FD_DEPRECATED") + print("#endif") + print() + + func(p) + + print("#endif /* %s */" % guard) =20 =20 def dump_c_defines(args): - guard =3D str.replace(os.path.basename(args.xml), '.', '_').upper() - dump_c(args, guard, lambda p: p.dump()) + guard =3D str.replace(os.path.basename(args.xml), '.', '_').upper() + dump_c(args, guard, lambda p: p.dump()) =20 =20 def dump_c_pack_structs(args): - guard =3D str.replace(os.path.basename(args.xml), '.', '_').upper() + '_S= TRUCTS' - dump_c(args, guard, lambda p: p.dump_structs()) - + guard =3D str.replace(os.path.basename(args.xml), + '.', '_').upper() + '_STRUCTS' + dump_c(args, guard, lambda p: p.dump_structs()) + + +def dump_perfcntrs(args): + p =3D Parser() + + try: + p.parse(args.rnn, args.xml, args.validate) + except Error as e: + print(e, file=3Dsys.stderr) + exit(1) + + perfcntrs =3D json.load(open(args.json, "r", encoding=3D"utf-8")) + + chip_type =3D p.enums['chip'] + chip =3D perfcntrs['chip'] + if not chip_type.has_name(chip): + raise Error("Invalid chip: " + chip) + + groups =3D perfcntrs['groups'] + + guard =3D "__" + chip + "_PERFCNTRS_" + print("#ifndef %s\n#define %s\n" % (guard, guard)) + print("/* Autogenerated file, DO NOT EDIT manually! */") + print() + print("#ifdef __KERNEL__") + print("#include \"msm_perfcntr.h\"") + print("#endif") + print() + + def has_variant(variant): + if variant is None: + return True + if "-" in variant: + start =3D chip_type.value(variant[:variant.index("-")]) + end =3D chip_type.value(variant[variant.index("-") + 1:]) + chipn =3D chip_type.value(chip) + + return (start is None or chipn >=3D start) and (end is None or= chipn <=3D end) + return chip =3D=3D variant + + # Split out arrays and regs for later access: + arrays =3D {} + regs =3D {} + for e in p.file: + if isinstance(e, Array) and has_variant(e.variant): + arrays[e.local_name] =3D e + if isinstance(e, Reg): + regs[e.name] =3D e + + # For variant regs, overwrite 'regs' entries with correct variant: + for regname in p.variant_regs: + for (variant, reg) in p.variant_regs[regname].items(): + if has_variant(variant): + regs[regname] =3D reg + break + + for group in groups: + name =3D group['name'] + name_low =3D name.lower() + num =3D group['num'] + countable_type_name =3D group['countable_type'] + + if not countable_type_name in p.enums: + raise Error("Invalid type: " + countable_type_name) + + countable_type =3D p.enums[countable_type_name] + + print("#ifndef __KERNEL__") + print("static const struct fd_perfcntr_countable " + name_low + "_= countables[] =3D {") + for (name, value) in countable_type.values: + # if the countable is prefixed with the chip, strip that: + # (note: avoid py3.9 dependency for kernel) + if name.startswith(chip + "_"): + name =3D name[len(chip)+1:] + print(" { \"" + name + "\", " + str(value) + " },") + print("};") + print("#endif") + + print("static const struct fd_perfcntr_counter " + name_low + "_co= unters[] =3D {") + for i in range(0, num): + if "reserved" in group and i in group["reserved"]: + continue + def get_reg(name): + # if reg has {} pattern, expand that first: + name =3D name.format(i) + + if name in arrays: + arr =3D arrays[name] + return arr.offset + (i * arr.stride) + + if not name in regs: + raise Error("Invalid reg: " + name) + + reg =3D regs[name] + return reg.offset + + def get_counter(): + # if the counter is just a single "counter" value + # should be specified in the json, but for legacy separate + # hi/lo pairs "counter_lo" and "counter_hi" should + # be specified + if "counter" in group: + counter =3D get_reg(group["counter"]) + return [counter, counter+1] + counter_lo =3D get_reg(group["counter_lo"]) + counter_hi =3D get_reg(group["counter_hi"]) + return [counter_lo, counter_hi] + + (counter_lo, counter_hi) =3D get_counter() + select =3D get_reg(group['select']) + + select_offset =3D 0 + if "select_offset" in group: + select_offset =3D int(group["select_offset"]) + select =3D select + select_offset + + slice_select_str =3D "" + if "slice_select" in group: + slice_select =3D group["slice_select"] + for reg in slice_select: + val =3D get_reg(reg) + select_offset + slice_select_str +=3D "0x%04x, " % val + + # TODO add support for things that need enable/clear regs + + print(" { 0x%04x, {%s}, 0x%04x, 0x%04x }," % (select, slice_= select_str, counter_lo, counter_hi)) + print("};") + + print() + + print("const struct fd_perfcntr_group " + chip.lower() + "_perfcntr_gr= oups[] =3D {") + for group in groups: + name =3D group['name'] + name_low =3D name.lower() + pipe =3D 'NONE' + if 'pipe' in group: + pipe =3D group['pipe'] + + print(" GROUP(\"%s\", PIPE_%s, %s_counters, %s_countables)," % (= name, pipe, name_low, name_low)) + + print("};") + print("const unsigned " + chip.lower() + "_num_perfcntr_groups =3D ARR= AY_SIZE(" + chip.lower() + "_perfcntr_groups);") + + print() + print("#endif /* %s */" % guard) =20 def dump_py_defines(args): - p =3D Parser() + p =3D Parser() =20 - try: - p.parse(args.rnn, args.xml, args.validate) - except Error as e: - print(e, file=3Dsys.stderr) - exit(1) + try: + p.parse(args.rnn, args.xml, args.validate) + except Error as e: + print(e, file=3Dsys.stderr) + exit(1) =20 - file_name =3D os.path.splitext(os.path.basename(args.xml))[0] + file_name =3D os.path.splitext(os.path.basename(args.xml))[0] =20 - print("from enum import IntEnum") - print("class %sRegs(IntEnum):" % file_name.upper()) + print("from enum import IntEnum") + print("class %sRegs(IntEnum):" % file_name.upper()) =20 - os.path.basename(args.xml) + os.path.basename(args.xml) =20 - p.dump_regs_py() + p.dump_regs_py() =20 =20 def main(): - parser =3D argparse.ArgumentParser() - parser.add_argument('--rnn', type=3Dstr, required=3DTrue) - parser.add_argument('--xml', type=3Dstr, required=3DTrue) - parser.add_argument('--validate', default=3DFalse, action=3D'store_true') - parser.add_argument('--no-validate', dest=3D'validate', action=3D'store_f= alse') + parser =3D argparse.ArgumentParser() + parser.add_argument('--rnn', type=3Dstr, required=3DTrue) + parser.add_argument('--xml', type=3Dstr, required=3DTrue) + parser.add_argument('--validate', default=3DFalse, action=3D'store_tru= e') + parser.add_argument('--no-validate', dest=3D'validate', action=3D'stor= e_false') + + subparsers =3D parser.add_subparsers() + subparsers.required =3D True =20 - subparsers =3D parser.add_subparsers() - subparsers.required =3D True + parser_c_defines =3D subparsers.add_parser('c-defines') + parser_c_defines.set_defaults(func=3Ddump_c_defines) =20 - parser_c_defines =3D subparsers.add_parser('c-defines') - parser_c_defines.set_defaults(func=3Ddump_c_defines) + parser_c_pack_structs =3D subparsers.add_parser('c-pack-structs') + parser_c_pack_structs.set_defaults(func=3Ddump_c_pack_structs) =20 - parser_c_pack_structs =3D subparsers.add_parser('c-pack-structs') - parser_c_pack_structs.set_defaults(func=3Ddump_c_pack_structs) + parser_perfcntrs =3D subparsers.add_parser('perfcntrs') + parser_perfcntrs.add_argument('--json', type=3Dstr, required=3DTrue) + parser_perfcntrs.set_defaults(func=3Ddump_perfcntrs) =20 - parser_py_defines =3D subparsers.add_parser('py-defines') - parser_py_defines.set_defaults(func=3Ddump_py_defines) + parser_py_defines =3D subparsers.add_parser('py-defines') + parser_py_defines.set_defaults(func=3Ddump_py_defines) =20 - args =3D parser.parse_args() - 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dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Akhil P Oommen , Rob Clark , Dmitry Baryshkov , Anna Maniscalco , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Konrad Dybcio , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v9 05/16] drm/msm/registers: Add perfcntr json Date: Fri, 22 May 2026 10:32:51 -0700 Message-ID: <20260522173349.55491-6-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260522173349.55491-1-robin.clark@oss.qualcomm.com> References: <20260522173349.55491-1-robin.clark@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: Osjm1qU1DQUddD_wbhmLmCEwH1UuSxzT X-Authority-Analysis: v=2.4 cv=B/qJFutM c=1 sm=1 tr=0 ts=6a1093b6 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 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definitions=2026-05-22_04,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 priorityscore=1501 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605220175 Content-Type: text/plain; charset="utf-8" Pull in perfcntr json and wire up generation of perfcntr tables. Sync from mesa commit d2c4653ee953 ("freedreno/registers: Add gen8 perfcntr= s") Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov Reviewed-by: Anna Maniscalco Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/Makefile | 25 +- drivers/gpu/drm/msm/msm_perfcntr.h | 48 ++++ .../msm/registers/adreno/a2xx_perfcntrs.json | 109 ++++++++ .../msm/registers/adreno/a5xx_perfcntrs.json | 128 ++++++++++ .../msm/registers/adreno/a6xx_perfcntrs.json | 112 ++++++++ .../msm/registers/adreno/a7xx_perfcntrs.json | 228 +++++++++++++++++ .../msm/registers/adreno/a8xx_perfcntrs.json | 240 ++++++++++++++++++ 7 files changed, 889 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/msm/msm_perfcntr.h create mode 100644 drivers/gpu/drm/msm/registers/adreno/a2xx_perfcntrs.json create mode 100644 drivers/gpu/drm/msm/registers/adreno/a5xx_perfcntrs.json create mode 100644 drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.json create mode 100644 drivers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.json create mode 100644 drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.json diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index ce00cfb0a875..337634e7e247 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -176,6 +176,11 @@ quiet_cmd_headergen =3D GENHDR $@ cmd_headergen =3D mkdir -p $(obj)/generated && $(PYTHON3) $(src)/reg= isters/gen_header.py \ $(headergen-opts) --rnn $(src)/registers --xml $< c-defines > $@ =20 +# TODO how to do this for a2xx/a5xx which have different .xml arg? +quiet_cmd_headergen_json =3D GENHDRJSN $@ + cmd_headergen_json =3D mkdir -p $(obj)/generated && $(PYTHON3) $(src= )/registers/gen_header.py \ + $(headergen-opts) --rnn $(src)/registers --xml $(filter %.xml,$^) = perfcntrs --json $< > $@ + $(obj)/generated/%.xml.h: $(src)/registers/adreno/%.xml \ $(src)/registers/adreno/adreno_common.xml \ $(src)/registers/adreno/adreno_pm4.xml \ @@ -192,6 +197,24 @@ $(obj)/generated/%.xml.h: $(src)/registers/display/%.x= ml \ FORCE $(call if_changed,headergen) =20 +ADRENO_PERFCNTRS =3D + +define adreno_perfcntrs +ADRENO_PERFCNTRS +=3D generated/$(1)_perfcntrs.json.c +$$(obj)/generated/$(1)_perfcntrs.json.c: $$(src)/registers/adreno/$(1)_per= fcntrs.json \ + $$(src)/registers/adreno/$(2).xml \ + FORCE + $$(call if_changed,headergen_json) +endef + +$(eval $(call adreno_perfcntrs,a2xx,a2xx)) +$(eval $(call adreno_perfcntrs,a5xx,a5xx)) +$(eval $(call adreno_perfcntrs,a6xx,a6xx)) +$(eval $(call adreno_perfcntrs,a7xx,a6xx)) +$(eval $(call adreno_perfcntrs,a8xx,a6xx)) + +adreno-y +=3D $(ADRENO_PERFCNTRS:.c=3D.o) + ADRENO_HEADERS =3D \ generated/a2xx.xml.h \ generated/a3xx.xml.h \ @@ -226,4 +249,4 @@ DISPLAY_HEADERS =3D \ $(addprefix $(obj)/,$(adreno-y)): $(addprefix $(obj)/,$(ADRENO_HEADERS)) $(addprefix $(obj)/,$(msm-display-y)): $(addprefix $(obj)/,$(DISPLAY_HEADE= RS)) =20 -targets +=3D $(ADRENO_HEADERS) $(DISPLAY_HEADERS) +targets +=3D $(ADRENO_HEADERS) $(DISPLAY_HEADERS) $(ADRENO_PERFCNTRS) diff --git a/drivers/gpu/drm/msm/msm_perfcntr.h b/drivers/gpu/drm/msm/msm_p= erfcntr.h new file mode 100644 index 000000000000..305dcde15c5e --- /dev/null +++ b/drivers/gpu/drm/msm/msm_perfcntr.h @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __MSM_PERFCNTR_H__ +#define __MSM_PERFCNTR_H__ + +#include "linux/array_size.h" + +#include "adreno_common.xml.h" + +/* + * This is a subset of the tables used by mesa. We don't need to + * enumerate the countables on the kernel side. + */ + +/* Describes a single counter: */ +struct msm_perfcntr_counter { + /* offset of the SELect register to choose what to count: */ + unsigned select_reg; + /* additional SEL regs to enable slice counters (gen8+) */ + unsigned slice_select_regs[2]; + /* offset of the lo/hi 32b to read current counter value: */ + unsigned counter_reg_lo; + unsigned counter_reg_hi; + /* TODO some counters have enable/clear registers */ +}; + +/* Describes an entire counter group: */ +struct msm_perfcntr_group { + const char *name; + enum adreno_pipe pipe; + unsigned num_counters; + const struct msm_perfcntr_counter *counters; +}; + +#define GROUP(_name, _pipe, _counters, _countables) { = \ + .name =3D _name, = \ + .pipe =3D _pipe, = \ + .num_counters =3D ARRAY_SIZE(_counters), = \ + .counters =3D _counters, = \ + } + +#define fd_perfcntr_counter msm_perfcntr_counter +#define fd_perfcntr_group msm_perfcntr_group + +#endif /* __MSM_PERFCNTR_H__ */ diff --git a/drivers/gpu/drm/msm/registers/adreno/a2xx_perfcntrs.json b/dri= vers/gpu/drm/msm/registers/adreno/a2xx_perfcntrs.json new file mode 100644 index 000000000000..8095345ffd8e --- /dev/null +++ b/drivers/gpu/drm/msm/registers/adreno/a2xx_perfcntrs.json @@ -0,0 +1,109 @@ +{ + "chip": "A2XX", + "groups": [ + { + "name": "CP", + "num": 1, + "select": "CP_PERFCOUNTER_SELECT", + "counter_lo": "CP_PERFCOUNTER_LO", + "counter_hi": "CP_PERFCOUNTER_HI", + "countable_type": "a2xx_cp_perfcount_sel" + }, + { + "name": "PA_SU", + "num": 4, + "select": "PA_SU_PERFCOUNTER{}_SELECT", + "counter_lo": "PA_SU_PERFCOUNTER{}_LOW", + "counter_hi": "PA_SU_PERFCOUNTER{}_HI", + "countable_type": "a2xx_su_perfcnt_select" + }, + { + "name": "PA_SC", + "num": 1, + "select": "PA_SC_PERFCOUNTER{}_SELECT", + "counter_lo": "PA_SC_PERFCOUNTER{}_LOW", + "counter_hi": "PA_SC_PERFCOUNTER{}_HI", + "countable_type": "a2xx_sc_perfcnt_select" + }, + { + "name": "VGT", + "num": 4, + "select": "VGT_PERFCOUNTER{}_SELECT", + "counter_lo": "VGT_PERFCOUNTER{}_LOW", + "counter_hi": "VGT_PERFCOUNTER{}_HI", + "countable_type": "a2xx_vgt_perfcount_select" + }, + { + "name": "TCR", + "num": 2, + "select": "TCR_PERFCOUNTER{}_SELECT", + "counter_lo": "TCR_PERFCOUNTER{}_LOW", + "counter_hi": "TCR_PERFCOUNTER{}_HI", + "countable_type": "a2xx_tcr_perfcount_select" + }, + { + "name": "TP0", + "num": 2, + "select": "TP0_PERFCOUNTER{}_SELECT", + "counter_lo": "TP0_PERFCOUNTER{}_LOW", + "counter_hi": "TP0_PERFCOUNTER{}_HI", + "countable_type": "a2xx_tp_perfcount_select" + }, + { + "name": "TCM", + "num": 2, + "select": "TCM_PERFCOUNTER{}_SELECT", + "counter_lo": "TCM_PERFCOUNTER{}_LOW", + "counter_hi": "TCM_PERFCOUNTER{}_HI", + "countable_type": "a2xx_tcm_perfcount_select" + }, + { + "name": "TCF", + "num": 12, + "select": "TCF_PERFCOUNTER{}_SELECT", + "counter_lo": "TCF_PERFCOUNTER{}_LOW", + "counter_hi": "TCF_PERFCOUNTER{}_HI", + "countable_type": "a2xx_tcf_perfcount_select" + }, + { + "name": "SQ", + "num": 4, + "select": "SQ_PERFCOUNTER{}_SELECT", + "counter_lo": "SQ_PERFCOUNTER{}_LOW", + "counter_hi": "SQ_PERFCOUNTER{}_HI", + "countable_type": "a2xx_sq_perfcnt_select" + }, + { + "name": "SX", + "num": 1, + "select": "SX_PERFCOUNTER{}_SELECT", + "counter_lo": "SX_PERFCOUNTER{}_LOW", + "counter_hi": "SX_PERFCOUNTER{}_HI", + "countable_type": "a2xx_sx_perfcnt_select" + }, + { + "name": "MH", + "num": 2, + "select": "MH_PERFCOUNTER{}_SELECT", + "counter_lo": "MH_PERFCOUNTER{}_LOW", + "counter_hi": "MH_PERFCOUNTER{}_HI", + "countable_type": "a2xx_mh_perfcnt_select" + }, + { + "name": "RBBM", + "num": 2, + "select": "RBBM_PERFCOUNTER{}_SELECT", + "counter_lo": "RBBM_PERFCOUNTER{}_LO", + "counter_hi": "RBBM_PERFCOUNTER{}_HI", + "countable_type": "a2xx_rbbm_perfcount1_sel" + }, + { + "name": "RB", + "num": 4, + "select": "RB_PERFCOUNTER{}_SELECT", + "counter_lo": "RB_PERFCOUNTER{}_LOW", + "counter_hi": "RB_PERFCOUNTER{}_HI", + "countable_type": "a2xx_rb_perfcnt_select" + } + ] +} diff --git a/drivers/gpu/drm/msm/registers/adreno/a5xx_perfcntrs.json b/dri= vers/gpu/drm/msm/registers/adreno/a5xx_perfcntrs.json new file mode 100644 index 000000000000..d95503543f94 --- /dev/null +++ b/drivers/gpu/drm/msm/registers/adreno/a5xx_perfcntrs.json @@ -0,0 +1,128 @@ +{ + "chip": "A5XX", + "groups": [ + { + "name": "CP", + "num": 8, + "reserved": [ 0 ], + "select": "CP_PERFCTR_CP_SEL_{}", + "counter_lo": "RBBM_PERFCTR_CP_{}_LO", + "counter_hi": "RBBM_PERFCTR_CP_{}_HI", + "countable_type": "a5xx_cp_perfcounter_select" + }, + { + "name": "CCU", + "num": 4, + "select": "RB_PERFCTR_CCU_SEL_{}", + "counter_lo": "RBBM_PERFCTR_CCU_{}_LO", + "counter_hi": "RBBM_PERFCTR_CCU_{}_HI", + "countable_type": "a5xx_ccu_perfcounter_select" + }, + { + "name": "TSE", + "num": 4, + "select": "GRAS_PERFCTR_TSE_SEL_{}", + "counter_lo": "RBBM_PERFCTR_TSE_{}_LO", + "counter_hi": "RBBM_PERFCTR_TSE_{}_HI", + "countable_type": "a5xx_tse_perfcounter_select" + }, + { + "name": "RAS", + "num": 4, + "select": "GRAS_PERFCTR_RAS_SEL_{}", + "counter_lo": "RBBM_PERFCTR_RAS_{}_LO", + "counter_hi": "RBBM_PERFCTR_RAS_{}_HI", + "countable_type": "a5xx_ras_perfcounter_select" + }, + { + "name": "LRZ", + "num": 4, + "select": "GRAS_PERFCTR_LRZ_SEL_{}", + "counter_lo": "RBBM_PERFCTR_LRZ_{}_LO", + "counter_hi": "RBBM_PERFCTR_LRZ_{}_HI", + "countable_type": "a5xx_lrz_perfcounter_select" + }, + { + "name": "HLSQ", + "num": 8, + "select": "HLSQ_PERFCTR_HLSQ_SEL_{}", + "counter_lo": "RBBM_PERFCTR_HLSQ_{}_LO", + "counter_hi": "RBBM_PERFCTR_HLSQ_{}_HI", + "countable_type": "a5xx_hlsq_perfcounter_select" + }, + { + "name": "PC", + "num": 8, + "select": "PC_PERFCTR_PC_SEL_{}", + "counter_lo": "RBBM_PERFCTR_PC_{}_LO", + "counter_hi": "RBBM_PERFCTR_PC_{}_HI", + "countable_type": "a5xx_pc_perfcounter_select" + }, + { + "name": "RB", + "num": 8, + "select": "RB_PERFCTR_RB_SEL_{}", + "counter_lo": "RBBM_PERFCTR_RB_{}_LO", + "counter_hi": "RBBM_PERFCTR_RB_{}_HI", + "countable_type": "a5xx_rb_perfcounter_select" + }, + { + "name": "RBBM", + "num": 4, + "reserved": [ 0 ], + "select": "RBBM_PERFCTR_RBBM_SEL_{}", + "counter_lo": "RBBM_PERFCTR_RBBM_{}_LO", + "counter_hi": "RBBM_PERFCTR_RBBM_{}_HI", + "countable_type": "a5xx_rbbm_perfcounter_select" + }, + { + "name": "SP", + "num": 12, + "reserved": [ 0 ], + "select": "SP_PERFCTR_SP_SEL_{}", + "counter_lo": "RBBM_PERFCTR_SP_{}_LO", + "counter_hi": "RBBM_PERFCTR_SP_{}_HI", + "countable_type": "a5xx_sp_perfcounter_select" + }, + { + "name": "TP", + "num": 8, + "select": "TPL1_PERFCTR_TP_SEL_{}", + "counter_lo": "RBBM_PERFCTR_TP_{}_LO", + "counter_hi": "RBBM_PERFCTR_TP_{}_HI", + "countable_type": "a5xx_tp_perfcounter_select" + }, + { + "name": "UCHE", + "num": 8, + "select": "UCHE_PERFCTR_UCHE_SEL_{}", + "counter_lo": "RBBM_PERFCTR_UCHE_{}_LO", + "counter_hi": "RBBM_PERFCTR_UCHE_{}_HI", + "countable_type": "a5xx_uche_perfcounter_select" + }, + { + "name": "VFD", + "num": 8, + "select": "VFD_PERFCTR_VFD_SEL_{}", + "counter_lo": "RBBM_PERFCTR_VFD_{}_LO", + "counter_hi": "RBBM_PERFCTR_VFD_{}_HI", + "countable_type": "a5xx_vfd_perfcounter_select" + }, + { + "name": "VPC", + "num": 4, + "select": "VPC_PERFCTR_VPC_SEL_{}", + "counter_lo": "RBBM_PERFCTR_VPC_{}_LO", + "counter_hi": "RBBM_PERFCTR_VPC_{}_HI", + "countable_type": "a5xx_vpc_perfcounter_select" + }, + { + "name": "VSC", + "num": 2, + "select": "VSC_PERFCTR_VSC_SEL_{}", + "counter_lo": "RBBM_PERFCTR_VSC_{}_LO", + "counter_hi": "RBBM_PERFCTR_VSC_{}_HI", + "countable_type": "a5xx_vsc_perfcounter_select" + } + ] +} diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.json b/dri= vers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.json new file mode 100644 index 000000000000..ec303e0b9f28 --- /dev/null +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.json @@ -0,0 +1,112 @@ +{ + "chip": "A6XX", + "groups": [ + { + "name": "CP", + "num": 14, + "reserved": [ 0 ], + "select": "CP_PERFCTR_CP_SEL", + "counter": "RBBM_PERFCTR_CP", + "countable_type": "a6xx_cp_perfcounter_select" + }, + { + "name": "CCU", + "num": 5, + "select": "RB_PERFCTR_CCU_SEL", + "counter": "RBBM_PERFCTR_CCU", + "countable_type": "a6xx_ccu_perfcounter_select" + }, + { + "name": "TSE", + "num": 4, + "select": "GRAS_PERFCTR_TSE_SEL", + "counter": "RBBM_PERFCTR_TSE", + "countable_type": "a6xx_tse_perfcounter_select" + }, + { + "name": "RAS", + "num": 4, + "select": "GRAS_PERFCTR_RAS_SEL", + "counter": "RBBM_PERFCTR_RAS", + "countable_type": "a6xx_ras_perfcounter_select" + }, + { + "name": "LRZ", + "num": 4, + "select": "GRAS_PERFCTR_LRZ_SEL", + "counter": "RBBM_PERFCTR_LRZ", + "countable_type": "a6xx_lrz_perfcounter_select" + }, + { + "name": "CMP", + "num": 4, + "select": "RB_PERFCTR_CMP_SEL", + "counter": "RBBM_PERFCTR_CMP", + "countable_type": "a6xx_cmp_perfcounter_select" + }, + { + "name": "HLSQ", + "num": 6, + "select": "HLSQ_PERFCTR_HLSQ_SEL", + "counter": "RBBM_PERFCTR_HLSQ", + "countable_type": "a6xx_hlsq_perfcounter_select" + }, + { + "name": "PC", + "num": 8, + "select": "PC_PERFCTR_PC_SEL", + "counter": "RBBM_PERFCTR_PC", + "countable_type": "a6xx_pc_perfcounter_select" + }, + { + "name": "RB", + "num": 8, + "select": "RB_PERFCTR_RB_SEL", + "counter": "RBBM_PERFCTR_RB", + "countable_type": "a6xx_rb_perfcounter_select" + }, + { + "name": "SP", + "num": 24, + "reserved": [ 0 ], + "select": "SP_PERFCTR_SP_SEL", + "counter": "RBBM_PERFCTR_SP", + "countable_type": "a6xx_sp_perfcounter_select" + }, + { + "name": "TP", + "num": 12, + "select": "TPL1_PERFCTR_TP_SEL", + "counter": "RBBM_PERFCTR_TP", + "countable_type": "a6xx_tp_perfcounter_select" + }, + { + "name": "UCHE", + "num": 12, + "select": "UCHE_PERFCTR_UCHE_SEL", + "counter": "RBBM_PERFCTR_UCHE", + "countable_type": "a6xx_uche_perfcounter_select" + }, + { + "name": "VFD", + "num": 8, + "select": "VFD_PERFCTR_VFD_SEL", + "counter": "RBBM_PERFCTR_VFD", + "countable_type": "a6xx_vfd_perfcounter_select" + }, + { + "name": "VPC", + "num": 6, + "select": "VPC_PERFCTR_VPC_SEL", + "counter": "RBBM_PERFCTR_VPC", + "countable_type": "a6xx_vpc_perfcounter_select" + }, + { + "name": "VSC", + "num": 2, + "select": "VSC_PERFCTR_VSC_SEL", + "counter": "RBBM_PERFCTR_VSC", + "countable_type": "a6xx_vsc_perfcounter_select" + } + ] +} diff --git a/drivers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.json b/dri= vers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.json new file mode 100644 index 000000000000..e60aab1862ec --- /dev/null +++ b/drivers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.json @@ -0,0 +1,228 @@ +{ + "chip": "A7XX", + "groups": [ + { + "name": "CP", + "num": 14, + "reserved": [ 0 ], + "select": "CP_PERFCTR_CP_SEL", + "counter": "RBBM_PERFCTR_CP", + "countable_type": "a7xx_cp_perfcounter_select" + }, + { + "name": "RBBM", + "num": 4, + "select": "RBBM_PERFCTR_RBBM_SEL", + "counter": "RBBM_PERFCTR_RBBM", + "countable_type": "a7xx_rbbm_perfcounter_select" + }, + { + "name": "PC", + "pipe": "BR", + "num": 8, + "select": "PC_PERFCTR_PC_SEL", + "counter": "RBBM_PERFCTR_PC", + "countable_type": "a7xx_pc_perfcounter_select" + }, + { + "name": "VFD", + "pipe": "BR", + "num": 8, + "select": "VFD_PERFCTR_VFD_SEL", + "counter": "RBBM_PERFCTR_VFD", + "countable_type": "a7xx_vfd_perfcounter_select" + }, + { + "name": "HLSQ", + "pipe": "BR", + "num": 6, + "select": "SP_PERFCTR_HLSQ_SEL", + "counter": "RBBM_PERFCTR_HLSQ", + "countable_type": "a7xx_hlsq_perfcounter_select" + }, + { + "name": "VPC", + "pipe": "BR", + "num": 6, + "select": "VPC_PERFCTR_VPC_SEL", + "counter": "RBBM_PERFCTR_VPC", + "countable_type": "a7xx_vpc_perfcounter_select" + }, + { + "name": "TSE", + "pipe": "BR", + "num": 4, + "select": "GRAS_PERFCTR_TSE_SEL", + "counter": "RBBM_PERFCTR_TSE", + "countable_type": "a7xx_tse_perfcounter_select" + }, + { + "name": "RAS", + "pipe": "BR", + "num": 4, + "select": "GRAS_PERFCTR_RAS_SEL", + "counter": "RBBM_PERFCTR_RAS", + "countable_type": "a7xx_ras_perfcounter_select" + }, + { + "name": "UCHE", + "num": 12, + "select": "UCHE_PERFCTR_UCHE_SEL", + "counter": "RBBM_PERFCTR_UCHE", + "countable_type": "a7xx_uche_perfcounter_select" + }, + { + "name": "TP", + "pipe": "BR", + "num": 12, + "select": "TPL1_PERFCTR_TP_SEL", + "counter": "RBBM_PERFCTR_TP", + "countable_type": "a7xx_tp_perfcounter_select" + }, + { + "name": "SP", + "pipe": "BR", + "num": 24, + "select": "SP_PERFCTR_SP_SEL", + "counter": "RBBM_PERFCTR_SP", + "countable_type": "a7xx_sp_perfcounter_select" + }, + { + "name": "RB", + "num": 8, + "select": "RB_PERFCTR_RB_SEL", + "counter": "RBBM_PERFCTR_RB", + "countable_type": "a7xx_rb_perfcounter_select" + }, + { + "name": "VSC", + "num": 2, + "select": "VSC_PERFCTR_VSC_SEL", + "counter": "RBBM_PERFCTR_VSC", + "countable_type": "a7xx_vsc_perfcounter_select" + }, + { + "name": "CCU", + "num": 5, + "select": "RB_PERFCTR_CCU_SEL", + "counter": "RBBM_PERFCTR_CCU", + "countable_type": "a7xx_ccu_perfcounter_select" + }, + { + "name": "LRZ", + "pipe": "BR", + "num": 4, + "select": "GRAS_PERFCTR_LRZ_SEL", + "counter": "RBBM_PERFCTR_LRZ", + "countable_type": "a7xx_lrz_perfcounter_select" + }, + { + "name": "CMP", + "num": 4, + "select": "RB_PERFCTR_CMP_SEL", + "counter": "RBBM_PERFCTR_CMP", + "countable_type": "a7xx_cmp_perfcounter_select" + }, + { + "name": "UFC", + "pipe": "BR", + "num": 4, + "select": "RB_PERFCTR_UFC_SEL", + "counter": "RBBM_PERFCTR_UFC", + "countable_type": "a7xx_ufc_perfcounter_select" + }, + { + "name": "BV_CP", + "num": 7, + "select": "CP_BV_PERFCTR_CP_SEL", + "counter": "RBBM_PERFCTR2_CP", + "countable_type": "a7xx_cp_perfcounter_select" + }, + { + "name": "BV_PC", + "pipe": "BV", + "num": 8, + "select_offset": 8, + "select": "PC_PERFCTR_PC_SEL", + "counter": "RBBM_PERFCTR_BV_PC", + "countable_type": "a7xx_pc_perfcounter_select" + }, + { + "name": "BV_VFD", + "pipe": "BV", + "num": 8, + "select_offset": 8, + "select": "VFD_PERFCTR_VFD_SEL", + "counter": "RBBM_PERFCTR_BV_VFD", + "countable_type": "a7xx_vfd_perfcounter_select" + }, + { + "name": "BV_VPC", + "pipe": "BV", + "num": 6, + "select_offset": 6, + "select": "VPC_PERFCTR_VPC_SEL", + "counter": "RBBM_PERFCTR_BV_VPC", + "countable_type": "a7xx_vpc_perfcounter_select" + }, + { + "name": "BV_TP", + "pipe": "BV", + "num": 6, + "select_offset": 12, + "select": "TPL1_PERFCTR_TP_SEL", + "counter": "RBBM_PERFCTR2_TP", + "countable_type": "a7xx_tp_perfcounter_select" + }, + { + "name": "BV_SP", + "pipe": "BV", + "num": 12, + "select_offset": 24, + "select": "SP_PERFCTR_SP_SEL", + "counter": "RBBM_PERFCTR2_SP", + "countable_type": "a7xx_sp_perfcounter_select" + }, + { + "name": "BV_UFC", + "pipe": "BV", + "num": 2, + "select_offset": 4, + "select": "RB_PERFCTR_UFC_SEL", + "counter": "RBBM_PERFCTR2_UFC", + "countable_type": "a7xx_ufc_perfcounter_select" + }, + { + "name": "BV_TSE", + "pipe": "BV", + "num": 4, + "select": "GRAS_PERFCTR_TSE_SEL", + "counter": "RBBM_PERFCTR_BV_TSE", + "countable_type": "a7xx_tse_perfcounter_select" + }, + { + "name": "BV_RAS", + "pipe": "BV", + "num": 4, + "select": "GRAS_PERFCTR_RAS_SEL", + "counter": "RBBM_PERFCTR_BV_RAS", + "countable_type": "a7xx_ras_perfcounter_select" + }, + { + "name": "BV_LRZ", + "pipe": "BV", + "num": 4, + "select": "GRAS_PERFCTR_LRZ_SEL", + "counter": "RBBM_PERFCTR_BV_LRZ", + "countable_type": "a7xx_lrz_perfcounter_select" + }, + { + "name": "BV_HLSQ", + "pipe": "BV", + "num": 6, + "select": "SP_PERFCTR_HLSQ_SEL", + "counter": "RBBM_PERFCTR2_HLSQ", + "countable_type": "a7xx_hlsq_perfcounter_select" + } + ] +} diff --git a/drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.json b/dri= vers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.json new file mode 100644 index 000000000000..fe4d01f10ff8 --- /dev/null +++ b/drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.json @@ -0,0 +1,240 @@ +{ + "chip": "A8XX", + "groups": [ + { + "name": "CP", + "num": 14, + "reserved": [ 0 ], + "select": "CP_PERFCTR_CP_SEL", + "counter": "RBBM_PERFCTR_CP", + "countable_type": "a8xx_cp_perfcounter_select" + }, + { + "name": "RBBM", + "num": 4, + "select": "RBBM_PERFCTR_RBBM_SEL", + "slice_select": [ "RBBM_SLICE_PERFCTR_RBBM_SEL" ], + "counter": "RBBM_PERFCTR_RBBM", + "countable_type": "a8xx_rbbm_perfcounter_select" + }, + { + "name": "PC", + "pipe": "BR", + "num": 8, + "select": "PC_PERFCTR_PC_SEL", + "slice_select": [ "PC_SLICE_PERFCTR_PC_SEL" ], + "counter": "RBBM_PERFCTR_PC", + "countable_type": "a8xx_pc_perfcounter_select" + }, + { + "name": "VFD", + "pipe": "BR", + "num": 8, + "select": "VFD_PERFCTR_VFD_SEL", + "counter": "RBBM_PERFCTR_VFD", + "countable_type": "a8xx_vfd_perfcounter_select" + }, + { + "name": "HLSQ", + "pipe": "BR", + "num": 6, + "select": "SP_PERFCTR_HLSQ_SEL", + "slice_select": [ "SP_PERFCTR_HLSQ_SEL_2" ], + "counter": "RBBM_PERFCTR_HLSQ", + "countable_type": "a8xx_hlsq_perfcounter_select" + }, + { + "name": "VPC", + "pipe": "BR", + "num": 6, + "select": "VPC_PERFCTR_VPC_SEL", + "slice_select": [ "VPC_PERFCTR_VPC_SEL_1", "VPC_PERFCTR_VPC_SE= L_2" ], + "counter": "RBBM_PERFCTR_VPC", + "countable_type": "a8xx_vpc_perfcounter_select" + }, + { + "name": "TSE", + "pipe": "BR", + "num": 4, + "select": "GRAS_PERFCTR_TSE_SEL", + "slice_select": [ "GRAS_PERFCTR_TSEFE_SEL" ], + "counter": "RBBM_PERFCTR_TSE", + "countable_type": "a8xx_tse_perfcounter_select" + }, + { + "name": "RAS", + "pipe": "BR", + "num": 4, + "select": "GRAS_PERFCTR_RAS_SEL", + "counter": "RBBM_PERFCTR_RAS", + "countable_type": "a8xx_ras_perfcounter_select" + }, + { + "name": "UCHE", + "num": 24, + "select": "UCHE_PERFCTR_UCHE_SEL", + "counter": "RBBM_PERFCTR_UCHE", + "countable_type": "a8xx_uche_perfcounter_select" + }, + { + "name": "TP", + "pipe": "BR", + "num": 12, + "select": "TPL1_PERFCTR_TP_SEL", + "counter": "RBBM_PERFCTR_TP", + "countable_type": "a8xx_tp_perfcounter_select" + }, + { + "name": "SP", + "pipe": "BR", + "num": 24, + "select": "SP_PERFCTR_SP_SEL", + "counter": "RBBM_PERFCTR_SP", + "countable_type": "a8xx_sp_perfcounter_select" + }, + { + "name": "RB", + "pipe": "BR", + "num": 8, + "select": "RB_PERFCTR_RB_SEL", + "counter": "RBBM_PERFCTR_RB", + "countable_type": "a8xx_rb_perfcounter_select" + }, + { + "name": "VSC", + "num": 2, + "select": "VSC_PERFCTR_VSC_SEL", + "counter": "RBBM_PERFCTR_VSC", + "countable_type": "a8xx_vsc_perfcounter_select" + }, + { + "name": "CCU", + "pipe": "BR", + "num": 5, + "select": "RB_PERFCTR_CCU_SEL", + "counter": "RBBM_PERFCTR_CCU", + "countable_type": "a8xx_ccu_perfcounter_select" + }, + { + "name": "LRZ", + "pipe": "BR", + "num": 4, + "select": "GRAS_PERFCTR_LRZ_SEL", + "counter": "RBBM_PERFCTR_LRZ", + "countable_type": "a8xx_lrz_perfcounter_select" + }, + { + "name": "CMP", + "num": 4, + "select": "RB_PERFCTR_CMP_SEL", + "counter": "RBBM_PERFCTR_CMP", + "countable_type": "a8xx_cmp_perfcounter_select" + }, + { + "name": "UFC", + "pipe": "BR", + "num": 4, + "select": "RB_PERFCTR_UFC_SEL", + "counter": "RBBM_PERFCTR_UFC", + "countable_type": "a8xx_ufc_perfcounter_select" + }, + { + "name": "BV_CP", + "num": 7, + "select_offset": 14, + "select": "CP_PERFCTR_CP_SEL", + "counter": "RBBM_PERFCTR2_CP", + "countable_type": "a8xx_cp_perfcounter_select" + }, + { + "name": "BV_PC", + "pipe": "BV", + "num": 8, + "select_offset": 8, + "select": "PC_PERFCTR_PC_SEL", + "slice_select": [ "PC_SLICE_PERFCTR_PC_SEL" ], + "counter": "RBBM_PERFCTR_BV_PC", + "countable_type": "a8xx_pc_perfcounter_select" + }, + { + "name": "BV_VFD", + "pipe": "BV", + "num": 8, + "select_offset": 8, + "select": "VFD_PERFCTR_VFD_SEL", + "counter": "RBBM_PERFCTR_BV_VFD", + "countable_type": "a8xx_vfd_perfcounter_select" + }, + { + "name": "BV_VPC", + "pipe": "BV", + "num": 6, + "select_offset": 6, + "select": "VPC_PERFCTR_VPC_SEL", + "slice_select": [ "VPC_PERFCTR_VPC_SEL_1", "VPC_PERFCTR_VPC_SE= L_2" ], + "counter": "RBBM_PERFCTR_BV_VPC", + "countable_type": "a8xx_vpc_perfcounter_select" + }, + { + "name": "BV_TP", + "pipe": "BV", + "num": 8, + "select_offset": 12, + "select": "TPL1_PERFCTR_TP_SEL", + "counter": "RBBM_PERFCTR2_TP", + "countable_type": "a8xx_tp_perfcounter_select" + }, + { + "name": "BV_SP", + "pipe": "BV", + "num": 12, + "select_offset": 24, + "select": "SP_PERFCTR_SP_SEL", + "counter": "RBBM_PERFCTR2_SP", + "countable_type": "a8xx_sp_perfcounter_select" + }, + { + "name": "BV_UFC", + "pipe": "BV", + "num": 2, + "select_offset": 4, + "select": "RB_PERFCTR_UFC_SEL", + "counter": "RBBM_PERFCTR2_UFC", + "countable_type": "a8xx_ufc_perfcounter_select" + }, + { + "name": "BV_TSE", + "pipe": "BV", + "num": 4, + "select": "GRAS_PERFCTR_TSE_SEL", + "slice_select": [ "GRAS_PERFCTR_TSEFE_SEL" ], + "counter": "RBBM_PERFCTR_BV_TSE", + "countable_type": "a8xx_tse_perfcounter_select" + }, + { + "name": "BV_RAS", + "pipe": "BV", + "num": 4, + "select": "GRAS_PERFCTR_RAS_SEL", + "counter": "RBBM_PERFCTR_BV_RAS", + "countable_type": "a8xx_ras_perfcounter_select" + }, + { + "name": "BV_LRZ", + "pipe": "BV", + "num": 4, + "select": "GRAS_PERFCTR_LRZ_SEL", + "counter": "RBBM_PERFCTR_BV_LRZ", + "countable_type": "a8xx_lrz_perfcounter_select" + }, + { + "name": "BV_HLSQ", + "pipe": "BV", + "num": 6, + "select": "SP_PERFCTR_HLSQ_SEL", + "slice_select": [ "SP_PERFCTR_HLSQ_SEL_2" ], + "counter": "RBBM_PERFCTR2_HLSQ", + "countable_type": "a8xx_hlsq_perfcounter_select" + } + ] +} --=20 2.54.0 From nobody Sun May 24 19:33:39 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EDBA3655EA for ; Fri, 22 May 2026 17:34:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779471291; cv=none; b=INnQOIQSpP6/TEkpSkUgk+xg4PGC1/DKlLAf02sL/hHiVxdbrpYhAButBOzwjl2EJlgwj9LkQLLDIWilTrEgcx6/bHg6jJkf1Y5VB4OfxY2CeCqxh9ax7Tu9pVldJtphAi3hDvRjOX8sAO6NCC/2aV9KevXqv/OkGoDxpmLebgQ= ARC-Message-Signature: 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d9443c01a7336-2beb56f9100sm21464675ad.37.2026.05.22.10.34.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 May 2026 10:34:46 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Akhil P Oommen , Rob Clark , Dmitry Baryshkov , Anna Maniscalco , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v9 06/16] drm/msm: Add a6xx+ perfcntr tables Date: Fri, 22 May 2026 10:32:52 -0700 Message-ID: <20260522173349.55491-7-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260522173349.55491-1-robin.clark@oss.qualcomm.com> References: <20260522173349.55491-1-robin.clark@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 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The PERFCNTR_CONFIG ioctl will use this information to assign counters. Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov Reviewed-by: Anna Maniscalco Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 +++++++++++++++ drivers/gpu/drm/msm/msm_gpu.h | 4 ++++ drivers/gpu/drm/msm/msm_perfcntr.h | 9 +++++++++ 3 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index e578417a4949..727281fbef36 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -5,6 +5,7 @@ #include "msm_gem.h" #include "msm_mmu.h" #include "msm_gpu_trace.h" +#include "msm_perfcntr.h" #include "a6xx_gpu.h" #include "a6xx_gmu.xml.h" =20 @@ -2637,6 +2638,20 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_devi= ce *dev) adreno_gpu =3D &a6xx_gpu->base; gpu =3D &adreno_gpu->base; =20 + if ((ADRENO_6XX_GEN1 <=3D config->info->family) && + (config->info->family <=3D ADRENO_6XX_GEN4)) { + gpu->perfcntr_groups =3D a6xx_perfcntr_groups; + gpu->num_perfcntr_groups =3D a6xx_num_perfcntr_groups; + } else if ((ADRENO_7XX_GEN1 <=3D config->info->family) && + (config->info->family <=3D ADRENO_7XX_GEN3)) { + gpu->perfcntr_groups =3D a7xx_perfcntr_groups; + gpu->num_perfcntr_groups =3D a7xx_num_perfcntr_groups; + } else if ((ADRENO_8XX_GEN1 <=3D config->info->family) && + (config->info->family <=3D ADRENO_8XX_GEN2)) { + gpu->perfcntr_groups =3D a8xx_perfcntr_groups; + gpu->num_perfcntr_groups =3D a8xx_num_perfcntr_groups; + } + mutex_init(&a6xx_gpu->gmu.lock); spin_lock_init(&a6xx_gpu->aperture_lock); =20 diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 78e1478669be..8c08dc065372 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -24,6 +24,7 @@ struct msm_gem_submit; struct msm_gem_vm_log_entry; struct msm_gpu_state; struct msm_context; +struct msm_perfcntr_group; =20 struct msm_gpu_config { const char *ioname; @@ -262,6 +263,9 @@ struct msm_gpu { bool allow_relocs; =20 struct thermal_cooling_device *cooling; + + const struct msm_perfcntr_group *perfcntr_groups; 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charset="utf-8" Currently the sysprof param serves two functions, (a) disabling perfcntr clearing on context switch/preemption, and (b) disabling IFPC. In the future, with kernel side global perfcntr collection/stream, the decision about disabling IFPC will change. To prepare for this, split out two helpers/accessors for the two different cases. For now, they are the same thing, but this will change. Signed-off-by: Rob Clark Reviewed-by: Anna Maniscalco Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 +++----- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 +++-- drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 2 +- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a8xx_preempt.c | 2 +- drivers/gpu/drm/msm/msm_gpu.h | 18 ++++++++++++++++++ 6 files changed, 27 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 1b44b9e21ad8..aba08fb76249 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -2036,10 +2036,10 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, s= truct platform_device *pdev, =20 void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu) { + bool sysprof =3D msm_gpu_sysprof_no_ifpc(gpu); struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; - unsigned int sysprof_active; =20 /* Nothing to do if GPU is suspended. We will handle this during GMU resu= me */ if (!pm_runtime_get_if_active(&gpu->pdev->dev)) @@ -2047,15 +2047,13 @@ void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu) =20 mutex_lock(&gmu->lock); =20 - sysprof_active =3D refcount_read(&gpu->sysprof_active); - /* * 'Perfcounter select' register values are lost during IFPC collapse. To= avoid that, * use the currently unused perfcounter oob vote to block IFPC when syspr= of is active */ - if ((sysprof_active > 1) && !test_and_set_bit(GMU_STATUS_OOB_PERF_SET, &g= mu->status)) + if (sysprof && !test_and_set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET); - else if ((sysprof_active =3D=3D 1) && test_and_clear_bit(GMU_STATUS_OOB_P= ERF_SET, &gmu->status)) + else if (!sysprof && test_and_clear_bit(GMU_STATUS_OOB_PERF_SET, &gmu->st= atus)) a6xx_gmu_clear_oob(gmu, GMU_OOB_PERFCOUNTER_SET); =20 mutex_unlock(&gmu->lock); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 727281fbef36..71f54ab5425d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -203,7 +203,7 @@ static void get_stats_counter(struct msm_ringbuffer *ri= ng, u32 counter, static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, struct msm_ringbuffer *ring, struct msm_gem_submit *submit) { - bool sysprof =3D refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1; + bool sysprof =3D msm_gpu_sysprof_no_perfcntr_zap(&a6xx_gpu->base.base); struct msm_context *ctx =3D submit->queue->ctx; struct drm_gpuvm *vm =3D msm_context_vm(submit->dev, ctx); struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; @@ -1608,7 +1608,7 @@ static int hw_init(struct msm_gpu *gpu) a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER); } =20 - if (!ret && (refcount_read(&gpu->sysprof_active) > 1)) { + if (!ret && msm_gpu_sysprof_no_ifpc(gpu)) { ret =3D a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET); if (!ret) set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status); @@ -2854,6 +2854,7 @@ const struct adreno_gpu_funcs a8xx_gpu_funcs =3D { .create_private_vm =3D a6xx_create_private_vm, .get_rptr =3D a6xx_get_rptr, .progress =3D a8xx_progress, + .sysprof_setup =3D a6xx_gmu_sysprof_setup, }, .init =3D a6xx_gpu_init, .get_timestamp =3D a8xx_gmu_get_timestamp, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_preempt.c b/drivers/gpu/drm/ms= m/adreno/a6xx_preempt.c index df4cbf42e9a4..1e599d4ddea1 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_preempt.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_preempt.c @@ -261,7 +261,7 @@ void a6xx_preempt_trigger(struct msm_gpu *gpu) mod_timer(&a6xx_gpu->preempt_timer, jiffies + msecs_to_jiffies(10000)); =20 /* Enable or disable postamble as needed */ - sysprof =3D refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1; + sysprof =3D msm_gpu_sysprof_no_perfcntr_zap(gpu); =20 if (!sysprof && !a6xx_gpu->postamble_enabled) preempt_prepare_postamble(a6xx_gpu); diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a8xx_gpu.c index ccfccc45133f..e022c9a162a4 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -849,7 +849,7 @@ static int hw_init(struct msm_gpu *gpu) */ a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); =20 - if (!ret && (refcount_read(&gpu->sysprof_active) > 1)) { + if (!ret && msm_gpu_sysprof_no_perfcntr_zap(gpu)) { ret =3D a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET); if (!ret) set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status); diff --git a/drivers/gpu/drm/msm/adreno/a8xx_preempt.c b/drivers/gpu/drm/ms= m/adreno/a8xx_preempt.c index 3d8c33ba722e..6cb53a071801 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_preempt.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_preempt.c @@ -242,7 +242,7 @@ void a8xx_preempt_trigger(struct msm_gpu *gpu) mod_timer(&a6xx_gpu->preempt_timer, jiffies + msecs_to_jiffies(10000)); =20 /* Enable or disable postamble as needed */ - sysprof =3D refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1; + sysprof =3D msm_gpu_sysprof_no_perfcntr_zap(gpu); =20 if (!sysprof && !a6xx_gpu->postamble_enabled) preempt_prepare_postamble(a6xx_gpu); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 8c08dc065372..9e5c753437c2 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -311,6 +311,24 @@ static inline bool msm_gpu_active(struct msm_gpu *gpu) return false; } =20 +static inline bool +msm_gpu_sysprof_no_perfcntr_zap(struct msm_gpu *gpu) +{ + return refcount_read(&gpu->sysprof_active) > 1; +} + +static inline bool +msm_gpu_sysprof_no_ifpc(struct msm_gpu *gpu) +{ + /* + * For now, this is the same condition as disabling perfcntr clears + * on context switch. But once kernel perfcntr IFPC support is in + * place, we will only need to disable IFPC for legacy userspace + * setting SYSPROF param. + */ + return msm_gpu_sysprof_no_perfcntr_zap(gpu); +} + /* * The number of priority levels provided by drm gpu scheduler. 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charset="utf-8" It's a common pattern, needing to insert a yield packet before flushing the rb. And we'll need this once again for configuring perfcntr SEL regs. So add a helper. Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov Reviewed-by: Anna Maniscalco Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 55 +++++++++++++-------------- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 10 +---- 3 files changed, 28 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 71f54ab5425d..415902f6e5d7 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -189,6 +189,30 @@ void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbu= ffer *ring) spin_unlock_irqrestore(&ring->preempt_lock, flags); } =20 +void +a6xx_flush_yield(struct msm_gpu *gpu, struct msm_ringbuffer *ring) +{ + /* If preemption is enabled */ + if (gpu->nr_rings > 1) { + /* Yield the floor on command completion */ + OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); + + /* + * If dword[2:1] are non zero, they specify an address for + * the CP to write the value of dword[3] to on preemption + * complete. Write 0 to skip the write + */ + OUT_RING(ring, 0x00); + OUT_RING(ring, 0x00); + /* Data value - not used if the address above is 0 */ + OUT_RING(ring, 0x01); + /* generate interrupt on preemption completion */ + OUT_RING(ring, 0x00); + } + + a6xx_flush(gpu, ring); +} + static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, u64 iova) { @@ -597,28 +621,9 @@ static void a7xx_submit(struct msm_gpu *gpu, struct ms= m_gem_submit *submit) OUT_PKT7(ring, CP_SET_MARKER, 1); OUT_RING(ring, 0x100); /* IFPC enable */ =20 - /* If preemption is enabled */ - if (gpu->nr_rings > 1) { - /* Yield the floor on command completion */ - OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); - - /* - * If dword[2:1] are non zero, they specify an address for - * the CP to write the value of dword[3] to on preemption - * complete. Write 0 to skip the write - */ - OUT_RING(ring, 0x00); - OUT_RING(ring, 0x00); - /* Data value - not used if the address above is 0 */ - OUT_RING(ring, 0x01); - /* generate interrupt on preemption completion */ - OUT_RING(ring, 0x00); - } - - trace_msm_gpu_submit_flush(submit, adreno_gpu->funcs->get_timestamp(gpu)); =20 - a6xx_flush(gpu, ring); + a6xx_flush_yield(gpu, ring); =20 /* Check to see if we need to start preemption */ if (adreno_is_a8xx(adreno_gpu)) @@ -958,15 +963,7 @@ static int a7xx_preempt_start(struct msm_gpu *gpu) =20 a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, NULL); =20 - /* Yield the floor on command completion */ - OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); - OUT_RING(ring, 0x00); - OUT_RING(ring, 0x00); - OUT_RING(ring, 0x00); - /* Generate interrupt on preemption completion */ - OUT_RING(ring, 0x00); - - a6xx_flush(gpu, ring); + a6xx_flush_yield(gpu, ring); =20 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index eb431e5e00b1..99c3e55f5ca8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -317,6 +317,7 @@ void a6xx_bus_clear_pending_transactions(struct adreno_= gpu *adreno_gpu, bool gx_ void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert); int a6xx_fenced_write(struct a6xx_gpu *gpu, u32 offset, u64 value, u32 mas= k, bool is_64b); void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring); +void a6xx_flush_yield(struct msm_gpu *gpu, struct msm_ringbuffer *ring); int a6xx_zap_shader_init(struct msm_gpu *gpu); =20 void a8xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bo= ol gx_off); diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a8xx_gpu.c index e022c9a162a4..124d315b2469 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -488,15 +488,7 @@ static int a8xx_preempt_start(struct msm_gpu *gpu) =20 a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, NULL); =20 - /* Yield the floor on command completion */ - OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); - OUT_RING(ring, 0x00); - OUT_RING(ring, 0x00); - OUT_RING(ring, 0x00); - /* Generate interrupt on preemption completion */ - OUT_RING(ring, 0x00); - - a6xx_flush(gpu, ring); + a6xx_flush_yield(gpu, ring); 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charset="utf-8" The upcoming PERFCNTR_CONFIG ioctl will allow for both global counter collection, and per-context counter reservation for local (ie. within a single GEM_SUBMIT ioctl) counter collection. Any number of contexts can reserve the same counters, but we will need to ensure that counters reserved for local counter collection do not conflict with counters used for global counter collection. So add tracking for per-context local counter reservations. Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov Reviewed-by: Anna Maniscalco Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/msm_gpu.h | 5 +++++ drivers/gpu/drm/msm/msm_perfcntr.h | 21 +++++++++++++++++++++ drivers/gpu/drm/msm/msm_submitqueue.c | 1 + 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 9e5c753437c2..19484774f369 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -434,6 +434,11 @@ struct msm_context { * this context. */ atomic64_t ctx_mem; + + /** + * @perfcntrs: Per-context reserved perfcntrs state + */ + struct msm_perfcntr_context_state *perfctx; }; =20 struct drm_gpuvm *msm_context_vm(struct drm_device *dev, struct msm_contex= t *ctx); diff --git a/drivers/gpu/drm/msm/msm_perfcntr.h b/drivers/gpu/drm/msm/msm_p= erfcntr.h index 64a5d29feba1..7f0654182496 100644 --- a/drivers/gpu/drm/msm/msm_perfcntr.h +++ b/drivers/gpu/drm/msm/msm_perfcntr.h @@ -35,6 +35,27 @@ struct msm_perfcntr_group { const struct msm_perfcntr_counter *counters; }; =20 +/** + * struct msm_perfcntr_context_state - per-msm_context counter state + * + * A given counter can either be unused, reserved for global counter + * collection exclusively, or reserved for local per-context counter + * collection inclusively. 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charset="utf-8" Add the basic infrastructure for tracking assigned perfcntrs. Signed-off-by: Rob Clark Reviewed-by: Anna Maniscalco Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/adreno/adreno_device.c | 8 +- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 5 +- drivers/gpu/drm/msm/msm_drv.h | 6 + drivers/gpu/drm/msm/msm_gpu.c | 12 ++ drivers/gpu/drm/msm/msm_gpu.h | 57 ++++++++- drivers/gpu/drm/msm/msm_perfcntr.c | 133 +++++++++++++++++++++ drivers/gpu/drm/msm/msm_perfcntr.h | 23 ++++ 8 files changed, 239 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/msm/msm_perfcntr.c diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 337634e7e247..2466cb32dac5 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -122,6 +122,7 @@ msm-y +=3D \ msm_gpu_devfreq.o \ msm_io_utils.o \ msm_iommu.o \ + msm_perfcntr.o \ msm_rd.o \ msm_ringbuffer.o \ msm_submitqueue.o \ diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index fc38331ce640..7f20320ef66a 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -307,8 +307,10 @@ MODULE_DEVICE_TABLE(of, dt_match); static int adreno_runtime_resume(struct device *dev) { struct msm_gpu *gpu =3D dev_to_gpu(dev); - - return gpu->funcs->pm_resume(gpu); + int ret =3D gpu->funcs->pm_resume(gpu); + if (!ret) + ret =3D msm_perfcntr_resume(gpu); + return ret; } =20 static int adreno_runtime_suspend(struct device *dev) @@ -322,6 +324,8 @@ static int adreno_runtime_suspend(struct device *dev) */ WARN_ON_ONCE(gpu->active_submits); =20 + msm_perfcntr_suspend(gpu); + return gpu->funcs->pm_suspend(gpu); } =20 diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/= adreno/adreno_gpu.c index 72b71e9e44f0..ee0bcf985934 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -702,11 +702,10 @@ void adreno_recover(struct msm_gpu *gpu) struct drm_device *dev =3D gpu->dev; int ret; =20 - // XXX pm-runtime?? we *need* the device to be off after this - // so maybe continuing to call ->pm_suspend/resume() is better? - + msm_perfcntr_suspend(gpu); gpu->funcs->pm_suspend(gpu); gpu->funcs->pm_resume(gpu); + msm_perfcntr_resume(gpu); =20 ret =3D msm_gpu_hw_init(gpu); if (ret) { diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index e53e4f220bed..f00b2e7aeb91 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -235,6 +235,12 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void = *data, int msm_ioctl_vm_bind(struct drm_device *dev, void *data, struct drm_file *file); =20 +int msm_perfcntr_resume(struct msm_gpu *gpu); +void msm_perfcntr_suspend(struct msm_gpu *gpu); + +struct msm_perfcntr_state * msm_perfcntr_init(struct msm_gpu *gpu); +void msm_perfcntr_cleanup(struct msm_gpu *gpu); + #ifdef CONFIG_DEBUG_FS unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned lon= g nr_to_scan); #endif diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 1bac70473f80..bf6845e5719e 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -1028,6 +1028,17 @@ int msm_gpu_init(struct drm_device *drm, struct plat= form_device *pdev, =20 refcount_set(&gpu->sysprof_active, 1); =20 + mutex_init(&gpu->perfcntr_lock); + + if (gpu->num_perfcntr_groups > 0) { + gpu->perfcntrs =3D msm_perfcntr_init(gpu); + if (IS_ERR(gpu->perfcntrs)) { + ret =3D PTR_ERR(gpu->perfcntrs); + gpu->perfcntrs =3D NULL; + goto fail; + } + } + return 0; =20 fail: @@ -1066,6 +1077,7 @@ void msm_gpu_cleanup(struct msm_gpu *gpu) } =20 msm_devfreq_cleanup(gpu); + msm_perfcntr_cleanup(gpu); =20 platform_set_drvdata(gpu->pdev, NULL); } diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 19484774f369..dc2eaada18cb 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -25,6 +25,7 @@ struct msm_gem_vm_log_entry; struct msm_gpu_state; struct msm_context; struct msm_perfcntr_group; +struct msm_perfcntr_stream; =20 struct msm_gpu_config { const char *ioname; @@ -93,6 +94,13 @@ struct msm_gpu_funcs { */ bool (*progress)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); void (*sysprof_setup)(struct msm_gpu *gpu); + + /* Configure perfcntr SELect regs: */ + void (*perfcntr_configure)(struct msm_gpu *gpu, struct msm_ringbuffer *ri= ng, + const struct msm_perfcntr_stream *stream); + + /* Flush perfcntrs before reading (optional): */ + void (*perfcntr_flush)(struct msm_gpu *gpu); }; =20 /* Additional state for iommu faults: */ @@ -266,6 +274,11 @@ struct msm_gpu { =20 const struct msm_perfcntr_group *perfcntr_groups; unsigned num_perfcntr_groups; + + struct msm_perfcntr_state *perfcntrs; + + /** @perfcntr_lock: protects perfcntr related state */ + struct mutex perfcntr_lock; }; =20 static inline struct msm_gpu *dev_to_gpu(struct device *dev) @@ -311,10 +324,52 @@ static inline bool msm_gpu_active(struct msm_gpu *gpu) return false; } =20 +/** + * struct msm_perfcntr_group_state - Tracking for the currently allocated = counter state + */ +struct msm_perfcntr_group_state { + /** + * @allocated_counters: + * + * allocated counters for global counter collection. The + * corresponding counters are allocated from highest to + * lowest, to minimize chance of conflict with old userspace + * allocating from lowest to highest. + */ + unsigned allocated_counters; + + /** + * @countables: + * + * The corresponding SELect reg values for the allocated counters + */ + uint32_t countables[]; +}; + +/** + * struct msm_perfcntr_state - overall global perfcntr state + */ +struct msm_perfcntr_state { + /** @stream: current global counter stream if active */ + struct msm_perfcntr_stream *stream; + + /** + * @groups: Global perfcntr stream group state. + * + * Conceptually this is part of msm_perfcntr_stream state, but is + * statically pre-allocated when the gpu is initialized to simplify + * error path cleanup in PERFCNTR_CONFIG ioctl. (__free(kfree) + * doesn't really help with variable length arrays of allocated + * pointers.) + */ + struct msm_perfcntr_group_state *groups[]; +}; + static inline bool msm_gpu_sysprof_no_perfcntr_zap(struct msm_gpu *gpu) { - return refcount_read(&gpu->sysprof_active) > 1; + return (refcount_read(&gpu->sysprof_active) > 1) || + (gpu->perfcntrs && READ_ONCE(gpu->perfcntrs->stream)); } =20 static inline bool diff --git a/drivers/gpu/drm/msm/msm_perfcntr.c b/drivers/gpu/drm/msm/msm_p= erfcntr.c new file mode 100644 index 000000000000..aeea60cd002e --- /dev/null +++ b/drivers/gpu/drm/msm/msm_perfcntr.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include "msm_drv.h" +#include "msm_gpu.h" +#include "msm_perfcntr.h" + +static int +msm_perfcntr_resume_locked(struct msm_perfcntr_stream *stream) +{ + return 0; +} + +int +msm_perfcntr_resume(struct msm_gpu *gpu) +{ + if (!gpu->perfcntrs) + return 0; + guard(mutex)(&gpu->perfcntr_lock); + return msm_perfcntr_resume_locked(gpu->perfcntrs->stream); +} + +static void +msm_perfcntr_suspend_locked(struct msm_perfcntr_stream *stream) +{ +} + +void +msm_perfcntr_suspend(struct msm_gpu *gpu) +{ + if (!gpu->perfcntrs) + return; + guard(mutex)(&gpu->perfcntr_lock); + msm_perfcntr_suspend_locked(gpu->perfcntrs->stream); +} + +/** + * msm_perfcntr_group_idx - map idx of perfcntr group to group_idx + * @stream: The global perfcntr stream + * @n: The requested group_idx + * + * The PERFCNTR_CONFIG ioctl requested N counters/countables per perfcntr + * group, but the order of groups is not required to match the order they + * are defined in the perfcntr tables (which is not stable/UABI, only the + * group names are UABI). + * + * But the order samples are returned in the stream should match the + * order they are requested in the PERFCNTR_CONFIG ioctl. This helper + * handles the order remapping. + * + * Returns an index into gpu->perfcntr_groups[] and perfcntrs->groups[]. + */ +uint32_t +msm_perfcntr_group_idx(const struct msm_perfcntr_stream *stream, uint32_t = n) +{ + WARN_ON_ONCE(n >=3D stream->nr_groups); + return stream->group_idx[n]; +} + +/** + * msm_perfcntr_counter_base - get idx of the first counter in group + * @stream: The global perfcntr stream + * @group_idx: the index of the counter group + * + * For global counter collection, counters are allocated from the end + * (last counter) while UMD allocates them from the start (0..N-1). + * Since UMD always allocated them from the start this also minimizes + * the chance of conflict when using old UMD which predates + * PERFCNTR_CONFIG ioctl. + * + * Returns the index of first counter to use. An index into + * msm_perfcntr_group::counters[]. + */ +uint32_t +msm_perfcntr_counter_base(const struct msm_perfcntr_stream *stream, uint32= _t group_idx) +{ + struct msm_gpu *gpu =3D stream->gpu; + struct msm_perfcntr_state *perfcntrs =3D gpu->perfcntrs; + unsigned num_counters =3D gpu->perfcntr_groups[group_idx].num_counters; + unsigned allocated_counters =3D perfcntrs->groups[group_idx]->allocated_c= ounters; + + return num_counters - allocated_counters; +} + +static void +__msm_perfcntr_cleanup(struct msm_gpu *gpu, struct msm_perfcntr_state *per= fcntrs) +{ + struct device *dev =3D &gpu->pdev->dev; + + for (unsigned i =3D 0; i < gpu->num_perfcntr_groups; i++) + devm_kfree(dev, perfcntrs->groups[i]); + + devm_kfree(dev, perfcntrs); +} + +void +msm_perfcntr_cleanup(struct msm_gpu *gpu) +{ + if (!gpu->perfcntrs) + return; + + __msm_perfcntr_cleanup(gpu, gpu->perfcntrs); + gpu->perfcntrs =3D NULL; +} + +struct msm_perfcntr_state * +msm_perfcntr_init(struct msm_gpu *gpu) +{ + struct msm_perfcntr_state *perfcntrs; + struct device *dev =3D &gpu->pdev->dev; + size_t sz; + + sz =3D struct_size(perfcntrs, groups, gpu->num_perfcntr_groups); + perfcntrs =3D devm_kzalloc(dev, sz, GFP_KERNEL); + if (!perfcntrs) + return ERR_PTR(-ENOMEM); + + for (unsigned i =3D 0; i < gpu->num_perfcntr_groups; i++) { + const struct msm_perfcntr_group *group =3D + &gpu->perfcntr_groups[i]; + + sz =3D struct_size(perfcntrs->groups[i], countables, group->num_counters= ); + perfcntrs->groups[i] =3D devm_kzalloc(dev, sz, GFP_KERNEL); + if (!perfcntrs->groups[i]) { + __msm_perfcntr_cleanup(gpu, perfcntrs); + return ERR_PTR(-ENOMEM); + } + } + + return perfcntrs; +} diff --git a/drivers/gpu/drm/msm/msm_perfcntr.h b/drivers/gpu/drm/msm/msm_p= erfcntr.h index 7f0654182496..bfda19e01535 100644 --- a/drivers/gpu/drm/msm/msm_perfcntr.h +++ b/drivers/gpu/drm/msm/msm_perfcntr.h @@ -35,6 +35,29 @@ struct msm_perfcntr_group { const struct msm_perfcntr_counter *counters; }; =20 +/** + * struct msm_perfcntr_stream - state for a single open stream fd + */ +struct msm_perfcntr_stream { + /** @gpu: Back-link to the GPU */ + struct msm_gpu *gpu; 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charset="utf-8" Add support to configure counter SELect regs. In some cases the reg writes need to happen while the GPU is idle. And for a7xx+, in some cases SEL regs need to be configured from BV or BR aperture. The easiest way to deal with this is to configure from the RB. Signed-off-by: Rob Clark Reviewed-by: Anna Maniscalco Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 69 +++++++++++++++++++++++++++ drivers/gpu/drm/msm/msm_perfcntr.h | 3 ++ drivers/gpu/drm/msm/msm_ringbuffer.h | 2 + 3 files changed, 74 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 415902f6e5d7..30df9bfa9ef8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2535,6 +2535,71 @@ static bool a6xx_progress(struct msm_gpu *gpu, struc= t msm_ringbuffer *ring) return progress; } =20 +static void +a6xx_perfcntr_configure(struct msm_gpu *gpu, struct msm_ringbuffer *ring, + const struct msm_perfcntr_stream *stream) +{ + enum adreno_pipe pipe =3D PIPE_NONE; + + for (unsigned i =3D 0; i < stream->nr_groups; i++) { + unsigned group_idx =3D msm_perfcntr_group_idx(stream, i); + unsigned base =3D msm_perfcntr_counter_base(stream, group_idx); + + const struct msm_perfcntr_group *group =3D + &gpu->perfcntr_groups[group_idx]; + + struct msm_perfcntr_group_state *group_state =3D + gpu->perfcntrs->groups[group_idx]; + + if (group->pipe !=3D pipe) { + pipe =3D group->pipe; + + OUT_PKT7(ring, CP_THREAD_CONTROL, 1); + + if (pipe =3D=3D PIPE_BR) { + OUT_RING(ring, CP_SET_THREAD_BR); + } else if (pipe =3D=3D PIPE_BV) { + OUT_RING(ring, CP_SET_THREAD_BV); + } else { + OUT_RING(ring, CP_SET_THREAD_BOTH); + } + } + + const struct msm_perfcntr_counter *counter =3D &group->counters[base]; + unsigned nr =3D group_state->allocated_counters; + OUT_PKT4(ring, counter->select_reg, nr); + for (unsigned c =3D 0; c < nr; c++) + OUT_RING(ring, group_state->countables[c]); + + for (unsigned s =3D 0; s < ARRAY_SIZE(counter->slice_select_regs); s++) { + if (!counter->slice_select_regs[s]) + break; + + OUT_PKT4(ring, counter->slice_select_regs[s], nr); + for (unsigned c =3D 0; c < nr; c++) + OUT_RING(ring, group_state->countables[c]); + } + } + + if (pipe !=3D PIPE_NONE) { + OUT_PKT7(ring, CP_THREAD_CONTROL, 1); + OUT_RING(ring, CP_SET_THREAD_BOTH); + } + + OUT_PKT7(ring, CP_MEM_WRITE, 3); + OUT_RING(ring, lower_32_bits(rbmemptr(ring, perfcntr_fence))); + OUT_RING(ring, upper_32_bits(rbmemptr(ring, perfcntr_fence))); + OUT_RING(ring, stream->sel_fence); + + a6xx_flush_yield(gpu, ring); + + /* Check to see if we need to start preemption */ + if (adreno_is_a8xx(to_adreno_gpu(gpu))) + a8xx_preempt_trigger(gpu); + else + a6xx_preempt_trigger(gpu); +} + static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) { if (!info->speedbins) @@ -2753,6 +2818,7 @@ const struct adreno_gpu_funcs a6xx_gpu_funcs =3D { .get_rptr =3D a6xx_get_rptr, .progress =3D a6xx_progress, .sysprof_setup =3D a6xx_gmu_sysprof_setup, + .perfcntr_configure =3D a6xx_perfcntr_configure, }, .init =3D a6xx_gpu_init, .get_timestamp =3D a6xx_gmu_get_timestamp, @@ -2786,6 +2852,7 @@ const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs = =3D { .create_private_vm =3D a6xx_create_private_vm, .get_rptr =3D a6xx_get_rptr, .progress =3D a6xx_progress, + .perfcntr_configure =3D a6xx_perfcntr_configure, }, .init =3D a6xx_gpu_init, .get_timestamp =3D a6xx_get_timestamp, @@ -2822,6 +2889,7 @@ const struct adreno_gpu_funcs a7xx_gpu_funcs =3D { .get_rptr =3D a6xx_get_rptr, .progress =3D a6xx_progress, .sysprof_setup =3D a6xx_gmu_sysprof_setup, + .perfcntr_configure =3D a6xx_perfcntr_configure, }, .init =3D a6xx_gpu_init, .get_timestamp =3D a6xx_gmu_get_timestamp, @@ -2852,6 +2920,7 @@ const struct adreno_gpu_funcs a8xx_gpu_funcs =3D { .get_rptr =3D a6xx_get_rptr, .progress =3D a8xx_progress, .sysprof_setup =3D a6xx_gmu_sysprof_setup, + .perfcntr_configure =3D a6xx_perfcntr_configure, }, .init =3D a6xx_gpu_init, .get_timestamp =3D a8xx_gmu_get_timestamp, diff --git a/drivers/gpu/drm/msm/msm_perfcntr.h b/drivers/gpu/drm/msm/msm_p= erfcntr.h index bfda19e01535..14506bc37d05 100644 --- a/drivers/gpu/drm/msm/msm_perfcntr.h +++ b/drivers/gpu/drm/msm/msm_perfcntr.h @@ -45,6 +45,9 @@ struct msm_perfcntr_stream { /** @nr_groups: # of counter groups with enabled counters */ uint32_t nr_groups; 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charset="utf-8" With the slice architecture, we need to flush the slice and unslice counters to perf RAM before reading counters. Signed-off-by: Rob Clark Reviewed-by: Anna Maniscalco Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 1 + drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 20 ++++++++++++++++++++ 3 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 30df9bfa9ef8..a329d20033d7 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2921,6 +2921,7 @@ const struct adreno_gpu_funcs a8xx_gpu_funcs =3D { .progress =3D a8xx_progress, .sysprof_setup =3D a6xx_gmu_sysprof_setup, .perfcntr_configure =3D a6xx_perfcntr_configure, + .perfcntr_flush =3D a8xx_perfcntr_flush, }, .init =3D a6xx_gpu_init, .get_timestamp =3D a8xx_gmu_get_timestamp, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index 99c3e55f5ca8..3491a24a9320 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -334,5 +334,6 @@ void a8xx_preempt_hw_init(struct msm_gpu *gpu); void a8xx_preempt_trigger(struct msm_gpu *gpu); void a8xx_preempt_irq(struct msm_gpu *gpu); bool a8xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring); +void a8xx_perfcntr_flush(struct msm_gpu *gpu); void a8xx_recover(struct msm_gpu *gpu); #endif /* __A6XX_GPU_H__ */ diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a8xx_gpu.c index 124d315b2469..6c040f718176 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -1345,3 +1345,23 @@ bool a8xx_progress(struct msm_gpu *gpu, struct msm_r= ingbuffer *ring) { return true; } + +void a8xx_perfcntr_flush(struct msm_gpu *gpu) +{ + u32 val; + + /* + * Flush delta counters (both perf counters and pipe stats) present in + * RBBM_S and RBBM_US to perf RAM logic to get the latest data. + */ + gpu_write(gpu, REG_A8XX_RBBM_PERFCTR_FLUSH_HOST_CMD, BIT(0)); + gpu_write(gpu, REG_A8XX_RBBM_SLICE_PERFCTR_FLUSH_HOST_CMD, BIT(0)); + + /* Ensure all writes are posted before polling status register */ + wmb(); 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charset="utf-8" Add new UABI and implementation of PERFCNTR_CONFIG ioctl. A bit more work is required to configure the pwrup_reglist for the GMU to restore SELect regs on exit of IFPC, before we can stop disabling IFPC while global counter collection. This will follow in a later commit, but will be transparent to userspace. Signed-off-by: Rob Clark Reviewed-by: Anna Maniscalco Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/msm_drv.c | 1 + drivers/gpu/drm/msm/msm_drv.h | 2 + drivers/gpu/drm/msm/msm_gpu.h | 3 + drivers/gpu/drm/msm/msm_perfcntr.c | 526 +++++++++++++++++++++++++++++ drivers/gpu/drm/msm/msm_perfcntr.h | 51 +++ include/uapi/drm/msm_drm.h | 48 +++ 6 files changed, 631 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 3066547f319b..0a7fc06113e0 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -801,6 +801,7 @@ static const struct drm_ioctl_desc msm_ioctls[] =3D { DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM= _RENDER_ALLOW), DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM= _RENDER_ALLOW), DRM_IOCTL_DEF_DRV(MSM_VM_BIND, msm_ioctl_vm_bind, DRM_RENDER_AL= LOW), + DRM_IOCTL_DEF_DRV(MSM_PERFCNTR_CONFIG, msm_ioctl_perfcntr_config, DR= M_RENDER_ALLOW), }; =20 static void msm_show_fdinfo(struct drm_printer *p, struct drm_file *file) diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index f00b2e7aeb91..204e140ac8e9 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -237,6 +237,8 @@ int msm_ioctl_vm_bind(struct drm_device *dev, void *dat= a, =20 int msm_perfcntr_resume(struct msm_gpu *gpu); void msm_perfcntr_suspend(struct msm_gpu *gpu); +int msm_ioctl_perfcntr_config(struct drm_device *dev, void *data, + struct drm_file *file); =20 struct msm_perfcntr_state * msm_perfcntr_init(struct msm_gpu *gpu); void msm_perfcntr_cleanup(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index dc2eaada18cb..22cbafe75a07 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -353,6 +353,9 @@ struct msm_perfcntr_state { /** @stream: current global counter stream if active */ struct msm_perfcntr_stream *stream; =20 + /** @sel_seqno: counter for sel_fence */ + uint32_t sel_seqno; + /** * @groups: Global perfcntr stream group state. * diff --git a/drivers/gpu/drm/msm/msm_perfcntr.c b/drivers/gpu/drm/msm/msm_p= erfcntr.c index aeea60cd002e..419e797478e8 100644 --- a/drivers/gpu/drm/msm/msm_perfcntr.c +++ b/drivers/gpu/drm/msm/msm_perfcntr.c @@ -3,13 +3,44 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 +#include "drm/drm_file.h" +#include "drm/msm_drm.h" + +#include "linux/anon_inodes.h" +#include "linux/gfp_types.h" +#include "linux/poll.h" +#include "linux/slab.h" + #include "msm_drv.h" #include "msm_gpu.h" #include "msm_perfcntr.h" =20 +#include "adreno/adreno_gpu.h" + +/* space used: */ +#define fifo_count(stream) \ + (CIRC_CNT((stream)->fifo.head, (stream)->fifo.tail, (stream)->fifo_size)) +#define fifo_count_to_end(stream) \ + (CIRC_CNT_TO_END(smp_load_acquire(&(stream)->fifo.head), (stream)->fifo.t= ail, (stream)->fifo_size)) +/* space available: */ +#define fifo_space(stream) \ + (CIRC_SPACE((stream)->fifo.head, (stream)->fifo.tail, (stream)->fifo_size= )) + static int msm_perfcntr_resume_locked(struct msm_perfcntr_stream *stream) { + if (!stream) + return 0; + + /* Reprogram SEL regs on highest priority rb: */ + struct msm_ringbuffer *ring =3D stream->gpu->rb[0]; + + queue_work(ring->sched.submit_wq, &stream->sel_work); + + hrtimer_start(&stream->sample_timer, + ns_to_ktime(stream->sample_period_ns), + HRTIMER_MODE_REL_PINNED); + return 0; } =20 @@ -25,6 +56,22 @@ msm_perfcntr_resume(struct msm_gpu *gpu) static void msm_perfcntr_suspend_locked(struct msm_perfcntr_stream *stream) { + if (!stream) + return; + + hrtimer_cancel(&stream->sample_timer); + kthread_cancel_work_sync(&stream->sample_work); + + /* + * We can't use cancel_work_sync() here, since sel_work acquires + * gpu->lock which (a) in suspend path can already be held, or + * (b) in release path would invert the order of gpu->lock and + * gpu->perfcntr_lock. Either would cause deadlock. + */ + cancel_work(&stream->sel_work); + + stream->sel_fence =3D ++stream->gpu->perfcntrs->sel_seqno; + stream->seqno =3D 0; } =20 void @@ -36,6 +83,485 @@ msm_perfcntr_suspend(struct msm_gpu *gpu) msm_perfcntr_suspend_locked(gpu->perfcntrs->stream); } =20 +static int +msm_perfcntrs_stream_release(struct inode *inode, struct file *file) +{ + struct msm_perfcntr_stream *stream =3D file->private_data; + struct msm_gpu *gpu =3D stream->gpu; + + scoped_guard (mutex, &gpu->perfcntr_lock) { + struct msm_perfcntr_state *perfcntrs =3D gpu->perfcntrs; + + msm_perfcntr_suspend_locked(stream); + perfcntrs->stream =3D NULL; + + /* release previously allocated counters: */ + for (unsigned i =3D 0; i < gpu->num_perfcntr_groups; i++) + perfcntrs->groups[i]->allocated_counters =3D 0; + } + + /* + * In the suspend path we use async cancel_work(), to avoid blocking + * on sel_work, which acquires gpu->lock (which could deadlock since + * other paths acquire gpu->lock before perfcntr_lock) or already + * hold gpu->lock. + * + * But since we are freeing the stream, after dropping perfcntr_lock + * we need to block until sel_work is done: + */ + cancel_work_sync(&stream->sel_work); + + kfree(stream->group_idx); + kfree(stream->fifo.buf); + kfree(stream); + + return 0; +} + +static __poll_t +msm_perfcntrs_stream_poll(struct file *file, poll_table *wait) +{ + struct msm_perfcntr_stream *stream =3D file->private_data; + __poll_t events =3D 0; + + poll_wait(file, &stream->poll_wq, wait); + + /* Are there samples to read? */ + if (fifo_count(stream) > 0) + events |=3D EPOLLIN; + + return events; +} + +static ssize_t +msm_perfcntrs_stream_read(struct file *file, char __user *buf, + size_t count, loff_t *ppos) +{ + struct msm_perfcntr_stream *stream =3D file->private_data; + int ret; + + if (!(file->f_flags & O_NONBLOCK)) { + ret =3D wait_event_interruptible(stream->poll_wq, + fifo_count(stream) > 0); + if (ret) + return ret; + } + + guard(mutex)(&stream->read_lock); + + struct circ_buf *fifo =3D &stream->fifo; + const char *fptr =3D &fifo->buf[fifo->tail]; + + count =3D min_t(size_t, count, fifo_count_to_end(stream)); + if (copy_to_user(buf, fptr, count)) + return -EFAULT; + + smp_store_release(&fifo->tail, (fifo->tail + count) & (stream->fifo_size = - 1)); + *ppos +=3D count; + + return count; +} + +static const struct file_operations stream_fops =3D { + .owner =3D THIS_MODULE, + .release =3D msm_perfcntrs_stream_release, + .poll =3D msm_perfcntrs_stream_poll, + .read =3D msm_perfcntrs_stream_read, +}; + +static void +sel_worker(struct work_struct *w) +{ + struct msm_perfcntr_stream *stream =3D + container_of(w, typeof(*stream), sel_work); + struct msm_gpu *gpu =3D stream->gpu; + /* Reprogram SEL regs on highest priority rb: */ + struct msm_ringbuffer *ring =3D stream->gpu->rb[0]; + + /* + * If in the process of resuming, wait for that. Otherwise sel_worker + * which is enqueued in the resume path can be scheduled before the + * resume completes. + */ + pm_runtime_barrier(&gpu->pdev->dev); + + /* + * sel_work could end up scheduled before suspend, but running + * after. See msm_perfcntr_suspend_locked() + * + * So if we end up running sel_work after the GPU is already + * suspended, just bail. It will be scheduled again after + * the GPU is resumed. + */ + if (!pm_runtime_get_if_active(&gpu->pdev->dev)) + return; + + scoped_guard (mutex, &gpu->lock) { + guard(mutex)(&gpu->perfcntr_lock); + + if (stream =3D=3D gpu->perfcntrs->stream) { + msm_gpu_hw_init(gpu); + gpu->funcs->perfcntr_configure(gpu, ring, stream); + } + } + + pm_runtime_put_autosuspend(&gpu->pdev->dev); +} + +static void +sample_write(struct msm_perfcntr_stream *stream, int *head, const void *bu= f, size_t sz) +{ + /* + * FIFO size is power-of-two, and guaranteed to have enough space to + * fit what we are writing. So we should not hit the wrap-around + * point writing things that are power-of-two sized + */ + WARN_ON(CIRC_SPACE_TO_END(*head, stream->fifo.tail, stream->fifo_size) < = sz); + + memcpy(&stream->fifo.buf[*head], buf, sz); + + /* Advance head, wrapping around if necessary: */ + *head =3D (*head + sz) & (stream->fifo_size - 1); +} + +static void +sample_write_u32(struct msm_perfcntr_stream *stream, int *head, uint32_t v= al) +{ + sample_write(stream, head, &val, sizeof(val)); +} + +static void +sample_write_u64(struct msm_perfcntr_stream *stream, int *head, uint64_t v= al) +{ + sample_write(stream, head, &val, sizeof(val)); +} + +static void +sample_worker(struct kthread_work *work) +{ + struct msm_perfcntr_stream *stream =3D + container_of(work, typeof(*stream), sample_work); + struct msm_gpu *gpu =3D stream->gpu; + struct msm_rbmemptrs *memptrs =3D gpu->rb[0]->memptrs; + + if (memptrs->perfcntr_fence !=3D stream->sel_fence) + return; + + /* + * Ensure we have enough space to capture a sample period's + * worth of data: + */ + if (stream->period_size > fifo_space(stream)) { + stream->seqno =3D 0; + return; + } + + if (gpu->funcs->perfcntr_flush) + gpu->funcs->perfcntr_flush(gpu); + + /* Keep local copy of head to avoid updating fifo until the end: */ + int head =3D stream->fifo.head; + + /* + * We expect the GPU to be powered at this point, as the timer + * and kthread work are canceled/flushed in the suspend path: + */ + sample_write_u64(stream, &head, + to_adreno_gpu(gpu)->funcs->get_timestamp(gpu)); + sample_write_u32(stream, &head, stream->seqno++); + sample_write_u32(stream, &head, 0); + + for (unsigned i =3D 0; i < stream->nr_groups; i++) { + unsigned group_idx =3D msm_perfcntr_group_idx(stream, i); + unsigned base =3D msm_perfcntr_counter_base(stream, group_idx); + + const struct msm_perfcntr_group *group =3D + &gpu->perfcntr_groups[group_idx]; + + struct msm_perfcntr_group_state *group_state =3D + gpu->perfcntrs->groups[group_idx]; + + unsigned nr =3D group_state->allocated_counters; + for (unsigned j =3D 0; j < nr; j++) { + const struct msm_perfcntr_counter *counter =3D + &group->counters[j + base]; + uint64_t val =3D gpu_read64(gpu, counter->counter_reg_lo); + sample_write_u64(stream, &head, val); + } + } + + smp_store_release(&stream->fifo.head, head); + wake_up_all(&stream->poll_wq); +} + +static enum hrtimer_restart +sample_timer(struct hrtimer *hrtimer) +{ + struct msm_perfcntr_stream *stream =3D + container_of(hrtimer, typeof(*stream), sample_timer); + + kthread_queue_work(stream->gpu->worker, &stream->sample_work); + + hrtimer_forward_now(hrtimer, ns_to_ktime(stream->sample_period_ns)); + + return HRTIMER_RESTART; +} + +static int +get_group_idx(struct msm_gpu *gpu, const char *name, size_t len) +{ + for (unsigned i =3D 0; i < gpu->num_perfcntr_groups; i++) { + const struct msm_perfcntr_group *group =3D + &gpu->perfcntr_groups[i]; + if (!strncmp(group->name, name, len)) + return i; + } + + return -1; +} + +static int +get_available_counters(struct msm_gpu *gpu, int group_idx, uint32_t flags) +{ + struct msm_perfcntr_state *perfcntrs =3D gpu->perfcntrs; + + /* + * For local counter reservation, anything that is not used by + * global perfcntr stream is available: + */ + if (!(flags & MSM_PERFCNTR_STREAM)) { + return gpu->perfcntr_groups[group_idx].num_counters - + perfcntrs->groups[group_idx]->allocated_counters; + } + + /* + * For global counter collection, anything that is not reserved by + * one or more contexts is available: + */ + guard(mutex)(&gpu->dev->filelist_mutex); + + unsigned reserved_counters =3D 0; + struct drm_file *file; + + list_for_each_entry (file, &gpu->dev->filelist, lhead) { + struct msm_context *ctx =3D file->driver_priv; + + if (!ctx || !ctx->perfctx) + continue; + + unsigned n =3D ctx->perfctx->reserved_counters[group_idx]; + reserved_counters =3D max(reserved_counters, n); + } + + return gpu->perfcntr_groups[group_idx].num_counters - reserved_counters; +} + +int +msm_ioctl_perfcntr_config(struct drm_device *dev, void *data, struct drm_f= ile *file) +{ + struct msm_drm_private *priv =3D dev->dev_private; + const struct drm_msm_perfcntr_config *args =3D data; + struct msm_context *ctx =3D file->driver_priv; + struct msm_gpu *gpu =3D priv->gpu; + int stream_fd =3D 0; + + if (!gpu || !gpu->num_perfcntr_groups) + return -ENXIO; + + struct msm_perfcntr_state *perfcntrs =3D gpu->perfcntrs; + + /* + * Validate args that don't require locks/power first: + */ + + if (args->flags & ~MSM_PERFCNTR_FLAGS) + return UERR(EINVAL, dev, "invalid flags"); + + if (args->nr_groups && !args->group_stride) + return UERR(EINVAL, dev, "invalid group_stride"); + + if (args->nr_groups > gpu->num_perfcntr_groups) + return UERR(EINVAL, dev, "too many groups"); + + if (args->nr_groups && !args->groups) + return UERR(EINVAL, dev, "no groups"); + + if (args->flags & MSM_PERFCNTR_STREAM) { + if (!perfmon_capable()) + return UERR(EPERM, dev, "invalid permissions"); + if (!args->nr_groups) + return UERR(EINVAL, dev, "invalid nr_groups"); + if (!args->period) + return UERR(EINVAL, dev, "invalid sampling period"); + if (args->bufsz_shift > const_ilog2(SZ_128M)) + return UERR(EINVAL, dev, "buffer size too big (>128M)"); + } else { + if (args->period) + return UERR(EINVAL, dev, "sampling period not allowed"); + if (args->bufsz_shift) + return UERR(EINVAL, dev, "sample buf size not allowed"); + } + + /* + * To avoid iterating over the groups multiple times, allocate and setup + * both a ctx and global stream object. Only one of the two will be + * kept in the end. + */ + + struct msm_perfcntr_context_state *perfctx __free(kfree) =3D kzalloc( + struct_size(perfctx, reserved_counters, gpu->num_perfcntr_groups), + GFP_KERNEL); + if (!perfctx) + return -ENOMEM; + + struct msm_perfcntr_stream *stream __free(kfree) =3D kzalloc_obj(*stream); + if (!stream) + return -ENOMEM; + + uint8_t *nr_counters __free(kfree) =3D kzalloc_objs(uint8_t, gpu->num_per= fcntr_groups); + if (!nr_counters) + return -ENOMEM; + + uint32_t *group_idx __free(kfree) =3D kzalloc_objs(uint32_t, args->nr_gro= ups); + if (!group_idx) + return -ENOMEM; + + stream->gpu =3D gpu; + stream->sample_period_ns =3D args->period; + stream->nr_groups =3D args->nr_groups; + stream->fifo_size =3D 1ull << args->bufsz_shift; + + mutex_init(&stream->read_lock); + + guard(mutex)(&gpu->perfcntr_lock); + + if (args->flags & MSM_PERFCNTR_STREAM) { + if (perfcntrs->stream) + return UERR(EBUSY, dev, "perfcntr stream already open"); + } + + size_t bufsz =3D 16; /* header size includes seqno and 64b timestamp: */ + int ret =3D 0; + + for (unsigned i =3D 0; i < args->nr_groups; i++) { + struct drm_msm_perfcntr_group g =3D {0}; + size_t sz =3D min_t(size_t, args->group_stride, sizeof(g)); + void __user *userptr =3D + u64_to_user_ptr(args->groups + (i * args->group_stride)); + + if (copy_from_user(&g, userptr, sz)) + return -EFAULT; + + if (g.pad) + return UERR(EINVAL, dev, "groups[%d]: invalid pad", i); + + int idx =3D get_group_idx(gpu, g.group_name, sizeof(g.group_name)); + + if (idx < 0) + return UERR(EINVAL, dev, "groups[%d]: unknown group", i); + + if (nr_counters[idx]) + return UERR(EINVAL, dev, "groups[%d]: duplicate group", i); + + if (g.nr_countables > gpu->perfcntr_groups[idx].num_counters) + return UERR(EINVAL, dev, "groups[%d]: too many counters", i); + + if (args->flags & MSM_PERFCNTR_STREAM) { + if (g.nr_countables && !g.countables) + return UERR(EINVAL, dev, "groups[%d]: no countables", i); + } else { + if (g.countables) + return UERR(EINVAL, dev, "groups[%d]: countables should be NULL", i); + } + + int avail_counters =3D get_available_counters(gpu, idx, args->flags); + if (g.nr_countables > avail_counters) { + /* + * Defer error return until we process all groups, in + * case there are other E2BIG groups: + */ + ret =3D UERR(E2BIG, dev, "groups[%d]: too few counters available", i); + + if (args->flags & MSM_PERFCNTR_UPDATE) { + /* Let userspace know how many counters are actually avail: */ + g.nr_countables =3D avail_counters; + if (copy_to_user(userptr, &g, sz)) + return -EFAULT; + } + } + + group_idx[i] =3D idx; + perfctx->reserved_counters[idx] =3D g.nr_countables; + + nr_counters[idx] =3D g.nr_countables; + + if (args->flags & MSM_PERFCNTR_STREAM) { + size_t sz =3D sizeof(uint32_t) * g.nr_countables; + void __user *userptr =3D u64_to_user_ptr(g.countables); + + if (copy_from_user(perfcntrs->groups[idx]->countables, userptr, sz)) + return -EFAULT; + + /* Samples are 64b per countable: */ + bufsz +=3D 2 * sz; + } + } + + if (ret) + return ret; + + if (args->flags & MSM_PERFCNTR_STREAM) { + /* + * Validate requested buffer size is large enough for at least + * a single sample period. + * + * Note the circ_buf implementation needs to be 1 byte larger + * than max it can hold (see CIRC_SPACE()). + */ + if (stream->fifo_size <=3D bufsz) + return UERR(EINVAL, dev, "required buffer size: %zu", bufsz); + + /* There aren't enough counters to hit this limit: */ + WARN_ON(bufsz > SZ_128M); + + stream->period_size =3D bufsz; + + void *buf __free(kfree) =3D kmalloc(stream->fifo_size, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + FD_PREPARE(fdf, O_CLOEXEC, + anon_inode_getfile("[msm_perfcntrs]", &stream_fops, stream, 0)); + if (fdf.err) + return fdf.err; + + INIT_WORK(&stream->sel_work, sel_worker); + kthread_init_work(&stream->sample_work, sample_worker); + init_waitqueue_head(&stream->poll_wq); + hrtimer_setup(&stream->sample_timer, sample_timer, + CLOCK_MONOTONIC, HRTIMER_MODE_REL); + + stream->sel_fence =3D ++perfcntrs->sel_seqno; + stream->group_idx =3D no_free_ptr(group_idx); + stream->fifo.buf =3D no_free_ptr(buf); + + /* commit the allocated counters: */ + for (unsigned i =3D 0; i < gpu->num_perfcntr_groups; i++) + perfcntrs->groups[i]->allocated_counters =3D nr_counters[i]; + + perfcntrs->stream =3D no_free_ptr(stream); + + msm_perfcntr_resume_locked(perfcntrs->stream); + + stream_fd =3D fd_publish(fdf); + } else { + kfree(ctx->perfctx); + ctx->perfctx =3D no_free_ptr(perfctx); + } + + return stream_fd; +} + /** * msm_perfcntr_group_idx - map idx of perfcntr group to group_idx * @stream: The global perfcntr stream diff --git a/drivers/gpu/drm/msm/msm_perfcntr.h b/drivers/gpu/drm/msm/msm_p= erfcntr.h index 14506bc37d05..198856b18445 100644 --- a/drivers/gpu/drm/msm/msm_perfcntr.h +++ b/drivers/gpu/drm/msm/msm_perfcntr.h @@ -7,6 +7,11 @@ #define __MSM_PERFCNTR_H__ =20 #include "linux/array_size.h" +#include "linux/circ_buf.h" +#include "linux/hrtimer.h" +#include "linux/kthread.h" +#include "linux/wait.h" +#include "linux/workqueue.h" =20 #include "adreno_common.xml.h" =20 @@ -42,12 +47,49 @@ struct msm_perfcntr_stream { /** @gpu: Back-link to the GPU */ struct msm_gpu *gpu; =20 + /** @sample_timer: Timer to sample counters */ + struct hrtimer sample_timer; + + /** @poll_wq: Wait queue for waiting for OA data to be available */ + wait_queue_head_t poll_wq; + + /** @sample_period_ns: Sampling period */ + uint64_t sample_period_ns; + /** @nr_groups: # of counter groups with enabled counters */ uint32_t nr_groups; =20 + /** @seqno: counter for collected samples */ + uint32_t seqno; + /** @sel_fence: Fence for SEL reg programming */ uint32_t sel_fence; =20 + /** + * @sel_work: Worker for SEL reg programming + * + * Initial SEL reg programming (as opposed to restoring the SEL + * regs on runpm resume) must run on the same ordered wq as is + * used by drm_sched, to serialize it with GEM_SUBMITs written + * into the same ringbuffer. + */ + struct work_struct sel_work; + + /** + * @sample_work: Worker for collecting samples + */ + struct kthread_work sample_work; + + /** + * @read_lock: + * + * Fifo access is synchronied on the producer side by virtue + * of there being a single timer collecting samples and writing + * into the fifo. It is protected on the consumer side by + * @read_lock. + */ + struct mutex read_lock; + /** * @group_idx: array of nr_groups * @@ -56,6 +98,15 @@ struct msm_perfcntr_stream { * the ioctl call that setup the stream */ uint32_t *group_idx; + + /** @fifo: circular buffer for samples */ + struct circ_buf fifo; + + /** @fifo_size: circular buffer size */ + size_t fifo_size; + + /** @period_size: size of data for single sampling period */ + size_t period_size; }; =20 uint32_t msm_perfcntr_group_idx(const struct msm_perfcntr_stream *stream, = uint32_t n); diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h index b99098792371..7f2e594be4eb 100644 --- a/include/uapi/drm/msm_drm.h +++ b/include/uapi/drm/msm_drm.h @@ -491,6 +491,52 @@ struct drm_msm_submitqueue_query { __u32 pad; }; =20 +#define MSM_PERFCNTR_STREAM 0x00000001 +#define MSM_PERFCNTR_UPDATE 0x00000002 +#define MSM_PERFCNTR_FLAGS ( \ + MSM_PERFCNTR_STREAM | \ + MSM_PERFCNTR_UPDATE | \ + 0) + +struct drm_msm_perfcntr_group { + char group_name[16]; + __u32 nr_countables; + __u32 pad; /* mbz */ + __u64 countables; /* pointer to an array of nr_countables u32 */ +}; + +/* + * Note, for MSM_PERFCNTR_STREAM, the ioctl returns an fd to read recorded + * counters. This only works because the ioctl is DRM_IOW(), if we return= ed + * a out param in the ioctl struct the copy_to_user() (in drm_ioctl()) + * could fault, causing us to leak the fd. + * + * If the ioctl returns with error E2BIG, that means more counters/countab= les + * are requested than are currently available. If MSM_PERFCNTR_UPDATE flag + * is set, drm_msm_perfcntr_group::nr_countables will be updated to return + * the actual # of counters available. + * + * The data read from the has the following format for each sampling perio= d: + * + * uint64_t timestamp; // CP_ALWAYS_ON_COUNTER captured at sample time + * uint32_t seqno; // increments by 1 each period, reset to 0 on = discontinuity + * uint32_t mbz; // pad out counters to 64b + * struct { + * uint64_t counter[nr_countables]; + * } groups[nr_groups]; + * + * The ordering of groups and counters matches the order in PERFCNTR_CONFIG + * ioctl. + */ +struct drm_msm_perfcntr_config { + __u32 flags; /* bitmask of MSM_PERFCNTR_x */ + __u32 nr_groups; /* # of entries in groups array */ + __u64 groups; /* pointer to array of drm_msm_perfcntr_group */ + __u64 period; /* sampling period in ns */ + __u32 bufsz_shift; /* sample buffer size in bytes is 1<; Fri, 22 May 2026 17:35:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; 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charset="utf-8" To make room for appending SEL reg programming. Without increasing the size, we would overflow the pwrup_reglist at ~190 counters on gen8. Or possibly fewer, considering that some gen8 counter groups also have separate slice vs unslice SELectors. Signed-off-by: Rob Clark Reviewed-by: Anna Maniscalco Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index a329d20033d7..e6c362c55dee 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1183,7 +1183,7 @@ static int a6xx_ucode_load(struct msm_gpu *gpu) msm_gem_object_set_name(a6xx_gpu->shadow_bo, "shadow"); } =20 - a6xx_gpu->pwrup_reglist_ptr =3D msm_gem_kernel_new(gpu->dev, PAGE_SIZE, + a6xx_gpu->pwrup_reglist_ptr =3D msm_gem_kernel_new(gpu->dev, PWRUP_REGLIS= T_SIZE, MSM_BO_WC | MSM_BO_MAP_PRIV, gpu->vm, &a6xx_gpu->pwrup_reglist_bo, &a6xx_gpu->pwrup_reglist_iova); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index 3491a24a9320..d3f0b40787db 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -96,6 +96,7 @@ struct a6xx_gpu { uint32_t *shadow; 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charset="utf-8" This is needed so that SEL reg values are restored on exit from IFPC. Signed-off-by: Rob Clark Reviewed-by: Anna Maniscalco Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 84 +++++++++++++++++++++++++-- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 11 +++- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 1 + 3 files changed, 89 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index e6c362c55dee..af524130d5c4 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -946,6 +946,7 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gp= u) A7XX_CP_APERTURE_CNTL_HOST_PIPE(PIPE_NONE)); } lock->dynamic_list_len =3D dyn_pwrup_reglist_count; + a6xx_gpu->dynamic_sel_reglist_offset =3D dyn_pwrup_reglist_count; } =20 static int a7xx_preempt_start(struct msm_gpu *gpu) @@ -2535,11 +2536,60 @@ static bool a6xx_progress(struct msm_gpu *gpu, stru= ct msm_ringbuffer *ring) return progress; } =20 +static void +perfcntr_select(struct msm_ringbuffer *ring, enum adreno_pipe pipe, + uint32_t regidx, uint32_t *countables, uint32_t nr, + uint32_t **reglist) +{ + OUT_PKT4(ring, regidx, nr); + for (unsigned i =3D 0; i < nr; i++) + OUT_RING(ring, countables[i]); + + if (!*reglist) + return; + + for (unsigned i =3D 0; i < nr; i++) { + /* + * Bitfield is in same position on a7xx, but only 2 bits.. + * which is sufficient for NONE/BR/BV: + */ + *(*reglist)++ =3D A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe); + *(*reglist)++ =3D regidx + i; + *(*reglist)++ =3D countables[i]; + } +} + static void a6xx_perfcntr_configure(struct msm_gpu *gpu, struct msm_ringbuffer *ring, const struct msm_perfcntr_stream *stream) { + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); enum adreno_pipe pipe =3D PIPE_NONE; + uint32_t *reglist =3D NULL; + uint32_t *reglist_sel_start; + + if (to_adreno_gpu(gpu)->info->family >=3D ADRENO_7XX_GEN1) { + WARN_ON(!a6xx_gpu->pwrup_reglist_emitted); + + struct cpu_gpu_lock *lock =3D a6xx_gpu->pwrup_reglist_ptr; + int off =3D (2 * lock->ifpc_list_len) + + (2 * lock->preemption_list_len) + + (3 * a6xx_gpu->dynamic_sel_reglist_offset); + + reglist =3D (uint32_t *)&lock->regs[0]; + reglist +=3D off; + reglist_sel_start =3D reglist; + + /* Clear any previously configured SEL reg entries: */ + lock->dynamic_list_len =3D a6xx_gpu->dynamic_sel_reglist_offset; + + /* + * Ensure CP sees the dynamic_list_len update before we + * start modifying the SEL entries: + */ + dma_wmb(); + } =20 for (unsigned i =3D 0; i < stream->nr_groups; i++) { unsigned group_idx =3D msm_perfcntr_group_idx(stream, i); @@ -2567,17 +2617,15 @@ a6xx_perfcntr_configure(struct msm_gpu *gpu, struct= msm_ringbuffer *ring, =20 const struct msm_perfcntr_counter *counter =3D &group->counters[base]; unsigned nr =3D group_state->allocated_counters; - OUT_PKT4(ring, counter->select_reg, nr); - for (unsigned c =3D 0; c < nr; c++) - OUT_RING(ring, group_state->countables[c]); + perfcntr_select(ring, pipe, counter->select_reg, + group_state->countables, nr, ®list); =20 for (unsigned s =3D 0; s < ARRAY_SIZE(counter->slice_select_regs); s++) { if (!counter->slice_select_regs[s]) break; =20 - OUT_PKT4(ring, counter->slice_select_regs[s], nr); - for (unsigned c =3D 0; c < nr; c++) - OUT_RING(ring, group_state->countables[c]); + perfcntr_select(ring, pipe, counter->slice_select_regs[s], + group_state->countables, nr, ®list); } } =20 @@ -2591,6 +2639,30 @@ a6xx_perfcntr_configure(struct msm_gpu *gpu, struct = msm_ringbuffer *ring, OUT_RING(ring, upper_32_bits(rbmemptr(ring, perfcntr_fence))); OUT_RING(ring, stream->sel_fence); =20 + /* + * Update the pwrup reglist size before flushing. Kgsl does a shared- + * memory spinlock dance with SQE to avoid racing with IFPC exit. But + * we can skip that since the ringbuffer programming will be executed + * by SQE after dynamic reglist size is updated. So even if we lose + * the race, the register programming in the rb will overwrite/correct + * the SEL regs restored by SQE on IFPC exit, before sampling begins. + */ + if (reglist) { + struct cpu_gpu_lock *lock =3D a6xx_gpu->pwrup_reglist_ptr; + unsigned nr_regs =3D (reglist - reglist_sel_start) / 3; + + /* + * Ensure CP sees updates to the pwrup_reglist before it + * sees the new (increased) length: + */ + dma_wmb(); + + /* Update dynamic reglist len to include new SEL reg programming: */ + lock->dynamic_list_len =3D a6xx_gpu->dynamic_sel_reglist_offset + nr_reg= s; + + WARN_ON_ONCE(reglist > (uint32_t *)((uint8_t *)lock + PWRUP_REGLIST_SIZE= )); + } + a6xx_flush_yield(gpu, ring); =20 /* Check to see if we need to start preemption */ diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index d3f0b40787db..b72fb58bf223 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -21,17 +21,19 @@ struct cpu_gpu_lock { uint32_t cpu_req; uint32_t turn; union { + /* a6xx: */ struct { uint16_t list_length; uint16_t list_offset; }; + /* a7xx+: */ struct { uint8_t ifpc_list_len; uint8_t preemption_list_len; uint16_t dynamic_list_len; }; }; - uint64_t regs[62]; + uint64_t regs[]; }; =20 /** @@ -101,6 +103,13 @@ struct a6xx_gpu { uint64_t pwrup_reglist_iova; bool pwrup_reglist_emitted; =20 + /* + * Offset of start of SEL regs appended to pwrup_reglist. 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charset="utf-8" Now that the dynamic pwrup reglist has SEL reg values to restore appended, so that SEL regs are restored on IFPC exit, we can stop completely disabling IFPC while global counter sampling is active. To accomplish this, we re-use sysprof_setup() with a force_on param to inhibit IFPC specifically while the counter regs are being read, while leaving IFPC enabled the rest of the time. Signed-off-by: Rob Clark Reviewed-by: Anna Maniscalco Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 ++-- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 +- drivers/gpu/drm/msm/msm_gpu.h | 10 ++-------- drivers/gpu/drm/msm/msm_perfcntr.c | 8 ++++++++ drivers/gpu/drm/msm/msm_submitqueue.c | 2 +- 5 files changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index aba08fb76249..0a7d49a2c877 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -2034,9 +2034,9 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, str= uct platform_device *pdev, return irq; } =20 -void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu) +void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu, bool force_on) { - bool sysprof =3D msm_gpu_sysprof_no_ifpc(gpu); + bool sysprof =3D msm_gpu_sysprof_no_ifpc(gpu) || force_on; struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index b72fb58bf223..f60a0801a62d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -281,7 +281,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx= _gmu_oob_state state); int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *n= ode); void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); -void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu); +void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu, bool force_on); =20 void a6xx_preempt_init(struct msm_gpu *gpu); void a6xx_preempt_hw_init(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 22cbafe75a07..3d8f1ea5335b 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -93,7 +93,7 @@ struct msm_gpu_funcs { * for cmdstream that is buffered in this FIFO upstream of the CP fw. */ bool (*progress)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); - void (*sysprof_setup)(struct msm_gpu *gpu); + void (*sysprof_setup)(struct msm_gpu *gpu, bool force_on); =20 /* Configure perfcntr SELect regs: */ void (*perfcntr_configure)(struct msm_gpu *gpu, struct msm_ringbuffer *ri= ng, @@ -378,13 +378,7 @@ msm_gpu_sysprof_no_perfcntr_zap(struct msm_gpu *gpu) static inline bool msm_gpu_sysprof_no_ifpc(struct msm_gpu *gpu) { - /* - * For now, this is the same condition as disabling perfcntr clears - * on context switch. But once kernel perfcntr IFPC support is in - * place, we will only need to disable IFPC for legacy userspace - * setting SYSPROF param. - */ - return msm_gpu_sysprof_no_perfcntr_zap(gpu); + return refcount_read(&gpu->sysprof_active) > 1; } =20 /* diff --git a/drivers/gpu/drm/msm/msm_perfcntr.c b/drivers/gpu/drm/msm/msm_p= erfcntr.c index 419e797478e8..fbcf8822ce61 100644 --- a/drivers/gpu/drm/msm/msm_perfcntr.c +++ b/drivers/gpu/drm/msm/msm_perfcntr.c @@ -256,6 +256,10 @@ sample_worker(struct kthread_work *work) return; } =20 + /* Inhibit IFPC while accessing registers: */ + if (gpu->funcs->sysprof_setup) + gpu->funcs->sysprof_setup(gpu, true); + if (gpu->funcs->perfcntr_flush) gpu->funcs->perfcntr_flush(gpu); =20 @@ -290,6 +294,10 @@ sample_worker(struct kthread_work *work) } } =20 + /* Re-enable IFPC: */ + if (gpu->funcs->sysprof_setup) + gpu->funcs->sysprof_setup(gpu, false); + smp_store_release(&stream->fifo.head, head); wake_up_all(&stream->poll_wq); } diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/ms= m_submitqueue.c index a58fe41602c6..1a5a77b28016 100644 --- a/drivers/gpu/drm/msm/msm_submitqueue.c +++ b/drivers/gpu/drm/msm/msm_submitqueue.c @@ -42,7 +42,7 @@ int msm_context_set_sysprof(struct msm_context *ctx, stru= ct msm_gpu *gpu, int sy =20 /* Some gpu families require additional setup for sysprof */ if (gpu->funcs->sysprof_setup) - gpu->funcs->sysprof_setup(gpu); + gpu->funcs->sysprof_setup(gpu, false); =20 ctx->sysprof =3D sysprof; =20 --=20 2.54.0