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Fri, 22 May 2026 15:27:54 +0000 (GMT) Received: from localhost.localdomain (unknown [9.124.216.126]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 22 May 2026 15:27:54 +0000 (GMT) From: Amit Machhiwal To: linuxppc-dev@lists.ozlabs.org, Madhavan Srinivasan Cc: Vaibhav Jain , Amit Machhiwal , Anushree Mathur , Paolo Bonzini , Nicholas Piggin , Michael Ellerman , "Christophe Leroy (CS GROUP)" , Jonathan Corbet , Shuah Khan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, lkp@intel.com Subject: [PATCH v3 1/5] KVM: PPC: Book3S HV: Validate arch_compat against host compatibility mode Date: Fri, 22 May 2026 20:57:40 +0530 Message-ID: <20260522152744.55251-2-amachhiw@linux.ibm.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260522152744.55251-1-amachhiw@linux.ibm.com> References: <20260522152744.55251-1-amachhiw@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIyMDE1MCBTYWx0ZWRfX73H+plhK0DSS 25I0LFmmYg/XwN8fhNwjRzvKrKrYffjKUbBNoJzbhSO8fZ/iuJAMju3F51Q6JPcjedYPorn1hrt VhnNizNaSI+85OBssAQFvku7nxrHDCJBAClFsVTKnTZiq172Rx+395bdoWnsQWh9vw5v6g7MFcd MfMVRtJ+l3uzDb7cWD1kFDXKazeOIiUrzfhl3tHhBbfFheo/qW7uVpYkSywrZwTDBrvgLt4Ir7d zEG3m173nZY7CYxZAlO3O3Nh+aR7g75bnieowcGlQVlADwv/HXbGYjpKNetrEST7CMdhNMF6iNc 7zsmJVWzonoKaqlx9yiUzZF1ujXpk302tU6Uv4iQaGryWJYtSyzkuuj/Js7LXUJ7iqrI9yNJCwa rpU5GiwK6I2RSOErx5RUclvJXGJ5sRw26ryLLuJ3J+HB78EI1PajED2qmVpqAtUV/V0vXf+OQxa G+cgWurXIw1wmW12efQ== X-Authority-Analysis: v=2.4 cv=Np/htcdJ c=1 sm=1 tr=0 ts=6a107603 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VnNF1IyMAAAA:8 a=9nGdcix9NZkGgJ1vRr8A:9 X-Proofpoint-ORIG-GUID: zLJ0M6e0kG7nOLGPJiPkVAOcvDIPBuIh X-Proofpoint-GUID: Ovko6TasHuGv4yj1U_3ln28ygmsd6Zc1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-22_04,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 clxscore=1011 priorityscore=1501 impostorscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605220150 Content-Type: text/plain; charset="utf-8" On IBM POWER systems, newer processor generations can operate in compatibility modes corresponding to earlier generations. This becomes relevant for nested virtualization, where nested KVM guests may need to run with a specific processor compatibility level. Currently, when running a nested KVM guest (L2) inside a Power11 pSeries logical partition (L1) booted in Power10 compatibility mode, the guest fails to boot while setting 'arch_compat'. This happens because the CPU class is derived from the hardware PVR (via mfspr()), which reflects the physical processor generation (Power11), rather than the effective compatibility mode (Power10). As a result, userspace may request a Power11 arch_compat for the L2 guest. However, the L1 partition, running in Power10 compatibility, has only negotiated support up to Power10 with the Power Hypervisor (L0). When H_SET_STATE is invoked with a Power11 Logical PVR, the hypervisor rejects the request, leading to a late guest boot failure: KVM-NESTEDv2: couldn't set guest wide elements [..KVM reg dump..] This situation should be detected earlier. Rejecting unsupported 'arch_compat' values in 'kvmppc_set_arch_compat()' avoids issuing an invalid H_SET_STATE hcall and provides a clearer failure mode. Add a check to reject Power11 'arch_compat' requests when the host is running in Power10 compatibility mode, returning -EINVAL early instead of deferring the failure to the hypervisor. Suggested-by: Vaibhav Jain Tested-by: Anushree Mathur Signed-off-by: Amit Machhiwal --- arch/powerpc/kvm/book3s_hv.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c index 61dbeea317f3..249d1f2e4e2c 100644 --- a/arch/powerpc/kvm/book3s_hv.c +++ b/arch/powerpc/kvm/book3s_hv.c @@ -446,7 +446,19 @@ static int kvmppc_set_arch_compat(struct kvm_vcpu *vcp= u, u32 arch_compat) guest_pcr_bit =3D PCR_ARCH_300; break; case PVR_ARCH_31: + guest_pcr_bit =3D PCR_ARCH_31; + break; case PVR_ARCH_31_P11: + /* + * Need to check this for ISA 3.1, as Power10 and + * Power11 share the same PCR. For any subsequent ISA + * versions, this will be taken care of by the guest vs + * host PCR comparison below. + */ + if ((PVR_ARCH_31 & cur_cpu_spec->pvr_mask) =3D=3D + cur_cpu_spec->pvr_value) { + return -EINVAL; + } guest_pcr_bit =3D PCR_ARCH_31; break; default: --=20 2.50.1 (Apple Git-155) From nobody Sun May 24 19:33:39 2026 Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2BA8477E24; Fri, 22 May 2026 15:28:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.156.1 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779463713; cv=none; b=jpXNg/y0dXxMVsqMF3gs2wEtmRJ0Zwn19M5ajkz0nc/1z7+QKeVXARGMC5eqoZ+wxW4rNP1fjDkpgqJztADOM00uDDVZJe36nufoMJQKYVIZBZj0Pp8cyPRC/nhILytYfye7kb7DjO2kbFhuhBtzrcxSH42oMQeMOZhh/pCb+Rg= ARC-Message-Signature: i=1; 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charset="utf-8" Introduce a new capability and ioctl to expose CPU compatibility modes supported by the host processor for nested guests. On IBM POWER systems, newer processor generations (N) can operate in compatibility modes corresponding to earlier generations, like (N-1) and (N-2). This is particularly relevant for nested virtualization, where nested KVM guests may need to run with a specific processor compatibility level. Introduce KVM_CAP_PPC_COMPAT_CAPS capability and the corresponding KVM_PPC_GET_COMPAT_CAPS vm ioctl. The ioctl returns a bitmap describing the compatibility modes supported by the host in respective bit numbers, allowing userspace (e.g., QEMU) to select an appropriate compatibility level when configuring nested KVM guests. The ioctl handling is added in kvm_arch_vm_ioctl() and retrieves host CPU compatibility capabilities via a PowerPC-specific backend implementation when available. If the capability is not supported, the ioctl returns success with no capabilities set, allowing userspace to fall back gracefully. Suggested-by: Vaibhav Jain Tested-by: Anushree Mathur Signed-off-by: Amit Machhiwal --- arch/powerpc/include/asm/kvm_ppc.h | 1 + arch/powerpc/include/uapi/asm/kvm.h | 6 ++++++ arch/powerpc/kvm/powerpc.c | 21 +++++++++++++++++++++ include/uapi/linux/kvm.h | 4 ++++ 4 files changed, 32 insertions(+) diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/= kvm_ppc.h index 0953f2daa466..cadfb839e836 100644 --- a/arch/powerpc/include/asm/kvm_ppc.h +++ b/arch/powerpc/include/asm/kvm_ppc.h @@ -319,6 +319,7 @@ struct kvmppc_ops { bool (*hash_v3_possible)(void); int (*create_vm_debugfs)(struct kvm *kvm); int (*create_vcpu_debugfs)(struct kvm_vcpu *vcpu, struct dentry *debugfs_= dentry); + int (*get_compat_cpu_ver)(struct kvm_ppc_compat_caps *host_caps); }; =20 extern struct kvmppc_ops *kvmppc_hv_ops; diff --git a/arch/powerpc/include/uapi/asm/kvm.h b/arch/powerpc/include/uap= i/asm/kvm.h index 077c5437f521..081d6c7f7f70 100644 --- a/arch/powerpc/include/uapi/asm/kvm.h +++ b/arch/powerpc/include/uapi/asm/kvm.h @@ -437,6 +437,12 @@ struct kvm_ppc_cpu_char { __u64 behaviour_mask; /* valid bits in behaviour */ }; =20 +/* For KVM_PPC_GET_COMPAT_CAPS */ +struct kvm_ppc_compat_caps { + __u64 flags; /* Reserved for future use */ + __u64 compat_capabilities; /* Capabilities supported by the host */ +}; + /* * Values for character and character_mask. * These are identical to the values used by H_GET_CPU_CHARACTERISTICS. diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c index 00302399fc37..02b834ebd8d3 100644 --- a/arch/powerpc/kvm/powerpc.c +++ b/arch/powerpc/kvm/powerpc.c @@ -697,6 +697,13 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long= ext) } } break; +#if defined(CONFIG_KVM_BOOK3S_HV_POSSIBLE) + case KVM_CAP_PPC_COMPAT_CAPS: + r =3D 0; + if (kvmhv_on_pseries()) + r =3D 1; + break; +#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */ default: r =3D 0; break; @@ -2463,6 +2470,20 @@ int kvm_arch_vm_ioctl(struct file *filp, unsigned in= t ioctl, unsigned long arg) r =3D kvm->arch.kvm_ops->svm_off(kvm); break; } + case KVM_PPC_GET_COMPAT_CAPS: { + struct kvm_ppc_compat_caps host_caps; + + r =3D -ENOTTY; + memset(&host_caps, 0, sizeof(host_caps)); + if (!kvm->arch.kvm_ops->get_compat_cpu_ver) + goto out; + + r =3D kvm->arch.kvm_ops->get_compat_cpu_ver(&host_caps); + if (!r && copy_to_user(argp, &host_caps, + sizeof(host_caps))) + r =3D -EFAULT; + break; + } default: { struct kvm *kvm =3D filp->private_data; r =3D kvm->arch.kvm_ops->arch_vm_ioctl(filp, ioctl, arg); diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 6c8afa2047bf..1788a0068662 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -996,6 +996,7 @@ struct kvm_enable_cap { #define KVM_CAP_S390_USER_OPEREXEC 246 #define KVM_CAP_S390_KEYOP 247 #define KVM_CAP_S390_VSIE_ESAMODE 248 +#define KVM_CAP_PPC_COMPAT_CAPS 249 =20 struct kvm_irq_routing_irqchip { __u32 irqchip; @@ -1349,6 +1350,9 @@ struct kvm_s390_keyop { #define KVM_GET_DEVICE_ATTR _IOW(KVMIO, 0xe2, struct kvm_device_attr) #define KVM_HAS_DEVICE_ATTR _IOW(KVMIO, 0xe3, struct kvm_device_attr) =20 +/* Available with KVM_CAP_PPC_COMPAT_CAPS */ +#define KVM_PPC_GET_COMPAT_CAPS _IOR(KVMIO, 0xe4, struct kvm_ppc_compat_c= aps) + /* * ioctls for vcpu fds */ --=20 2.50.1 (Apple Git-155) From nobody Sun May 24 19:33:39 2026 Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF8BB37C912; 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charset="utf-8" On POWER systems, the host CPU may run in a compatibility mode (e.g., a Power11 processor operating in Power10 compatibility mode). In such cases, the effective CPU level exposed to guests differs from the physical processor generation. When running nested KVM guests, QEMU derives the host CPU type using mfpvr(), which reflects the physical processor version. This can result in a mismatch between the CPU model selected by QEMU and the compatibility mode enforced by the host, leading to guest boot failures. For example, booting a nested guest on a Power11 LPAR configured in Power10 compatibility mode fails with: KVM-NESTEDv2: couldn't set guest wide elements [..KVM reg dump..] This occurs because QEMU selects a CPU model corresponding to the physical processor (via mfpvr()), while the host operates in a lower compatibility mode. As a result, KVM rejects the requested compatibility level during guest initialization. Add support for retrieving host CPU compatibility capabilities for nested guests on PowerVM (PAPR nested API v2). The hypervisor provides the effective compatibility levels via the H_GUEST_GET_CAPABILITIES hcall, which reflects the processor modes negotiated between the Power hypervisor (L0) and the host partition (L1). On pseries systems, obtain the capability bitmap using plpar_guest_get_capabilities() and return it via struct kvm_ppc_compat_caps. This information is then exposed to userspace through the KVM_PPC_GET_COMPAT_CAPS ioctl. Hook the implementation into the Book3S HV kvmppc_ops so that it can be invoked by the generic KVM ioctl handling code. Suggested-by: Vaibhav Jain Tested-by: Anushree Mathur Signed-off-by: Amit Machhiwal --- arch/powerpc/kvm/book3s_hv.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c index 249d1f2e4e2c..38de7040e2b7 100644 --- a/arch/powerpc/kvm/book3s_hv.c +++ b/arch/powerpc/kvm/book3s_hv.c @@ -6522,6 +6522,21 @@ static bool kvmppc_hash_v3_possible(void) return true; } =20 + +static int kvmppc_get_compat_cpu_caps(struct kvm_ppc_compat_caps *host_cap= s) +{ + unsigned long capabilities =3D 0; + long rc =3D -EINVAL; + + if (kvmhv_on_pseries()) { + if (kvmhv_is_nestedv2()) + rc =3D plpar_guest_get_capabilities(0, &capabilities); + host_caps->compat_capabilities =3D capabilities; + } + + return rc; +} + static struct kvmppc_ops kvm_ops_hv =3D { .get_sregs =3D kvm_arch_vcpu_ioctl_get_sregs_hv, .set_sregs =3D kvm_arch_vcpu_ioctl_set_sregs_hv, @@ -6564,6 +6579,7 @@ static struct kvmppc_ops kvm_ops_hv =3D { .hash_v3_possible =3D kvmppc_hash_v3_possible, .create_vcpu_debugfs =3D kvmppc_arch_create_vcpu_debugfs_hv, .create_vm_debugfs =3D kvmppc_arch_create_vm_debugfs_hv, + .get_compat_cpu_ver =3D kvmppc_get_compat_cpu_caps, }; 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Fri, 22 May 2026 15:28:09 +0000 (GMT) Received: from localhost.localdomain (unknown [9.124.216.126]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 22 May 2026 15:28:08 +0000 (GMT) From: Amit Machhiwal To: linuxppc-dev@lists.ozlabs.org, Madhavan Srinivasan Cc: Vaibhav Jain , Amit Machhiwal , Anushree Mathur , Paolo Bonzini , Nicholas Piggin , Michael Ellerman , "Christophe Leroy (CS GROUP)" , Jonathan Corbet , Shuah Khan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, lkp@intel.com Subject: [PATCH v3 4/5] KVM: PPC: Book3S HV: Add support for compat CPU capabilities for KVM on PowerNV Date: Fri, 22 May 2026 20:57:43 +0530 Message-ID: <20260522152744.55251-5-amachhiw@linux.ibm.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260522152744.55251-1-amachhiw@linux.ibm.com> References: <20260522152744.55251-1-amachhiw@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIyMDE1MCBTYWx0ZWRfX4FXsjy0P3w8q gYhrNFFzJA8f2Id/DJtt5yPBT9tBrwmZuycxHbkG6TvME6K61U81jOH3OwHd9/Ih927WAtsVrvI wiHPz1B/PvIY7RTjKgxU6rOf0t/J1d9v7elM/o1xnvM0wTUrd2qlocj0eYV4WTlhB8KP3/2a4Hh 3aQSJmDkCcoblV5DaJIh97dERK1MbyI2RmxcuPC77NOGPSn0MFSDz2MxDT7o9OFL+nawbFoLmhn 1AASSESeAx0zaIJjhlHQc2yzBIalSEyqDkOqJdPpRCpMfdLBTU4h0G6wgrXDGg9dzZNtq6DbnTq cYwKq5fy7q7fmZBL/87fFPvNAi+QowL8ZpEhFe4u9x7dPEJ0879TeVGXl7CqxpMeImaVNONCskY LKi8qyxmsOl5GN+xbcENF1GTko+ipL/5UdONCD8XQDMBr6ogX0OTA4qdXUlTtCTaABjV9qPgLk4 WyqOuPtvISk8Phl1sVw== X-Authority-Analysis: v=2.4 cv=Np/htcdJ c=1 sm=1 tr=0 ts=6a107611 cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VnNF1IyMAAAA:8 a=LbGGMz8L2r-vpTRwWUsA:9 X-Proofpoint-ORIG-GUID: ejG69M8c7fHnpUbCL9umDKHTMqYjUOUx X-Proofpoint-GUID: gqHWUPu5-2Tz1rzU0Dr2IZXkpWdtsI7- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-22_04,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 clxscore=1011 priorityscore=1501 impostorscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605220150 Content-Type: text/plain; charset="utf-8" Currently, when booting a compatibility-mode KVM guest (L1) on a PowerNV hypervisor (L0), the guest runs with the expected processor compatibility level. However, when booting a nested KVM guest (L2) inside the L1, QEMU derives the CPU model from the raw host PVR and attempts to run the nested guest at that level, instead of honoring the compatibility mode of the L1. Extend host CPU compatibility capability reporting to support nested virtualization on PowerNV systems (PAPR nested API v1). For nested API v2 (PowerVM), compatibility capabilities are obtained from the hypervisor via the H_GUEST_GET_CAPABILITIES hcall. This information is not available on PowerNV systems. For nested API v1, derive the compatibility capabilities from the L1 guest by reading the "cpu-version" property from the device tree, which reflects the effective (logical) processor compatibility level. Map this value to the corresponding compatibility capability bitmap. Introduce a helper to translate CPU version values into compatibility capability bits and integrate it into kvmppc_get_compat_cpu_caps(). This allows userspace to query host CPU compatibility modes on both PowerVM and PowerNV platforms via the KVM_PPC_GET_COMPAT_CAPS ioctl. Suggested-by: Vaibhav Jain Tested-by: Anushree Mathur Signed-off-by: Amit Machhiwal --- arch/powerpc/kvm/book3s_hv.c | 37 +++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c index 38de7040e2b7..18774c49af85 100644 --- a/arch/powerpc/kvm/book3s_hv.c +++ b/arch/powerpc/kvm/book3s_hv.c @@ -6522,15 +6522,50 @@ static bool kvmppc_hash_v3_possible(void) return true; } =20 +static int kvmppc_map_compat_capabilities(const __be32 cpu_version, + unsigned long *capabilities) +{ + switch (cpu_version) { + case PVR_ARCH_31_P11: + *capabilities |=3D H_GUEST_CAP_POWER11; + break; + case PVR_ARCH_31: + *capabilities |=3D H_GUEST_CAP_POWER10; + break; + case PVR_ARCH_300: + *capabilities |=3D H_GUEST_CAP_POWER9; + break; + default: + return -EINVAL; + } + + return 0; +} =20 static int kvmppc_get_compat_cpu_caps(struct kvm_ppc_compat_caps *host_cap= s) { + struct device_node *np; unsigned long capabilities =3D 0; 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charset="utf-8" Add documentation for the KVM_PPC_GET_COMPAT_CAPS ioctl to the KVM API documentation. The ioctl exposes host processor compatibility modes supported for nested KVM guests on PowerPC systems. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202605140717.W1StD3Ke-lkp@int= el.com/ Tested-by: Anushree Mathur Signed-off-by: Amit Machhiwal --- Documentation/virt/kvm/api.rst | 35 ++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index 52bbbb553ce1..d11e054e6665 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -6555,6 +6555,41 @@ KVM_S390_KEYOP_SSKE =20 .. _kvm_run: =20 +4.145 KVM_PPC_GET_COMPAT_CAPS +----------------------------- +:Capability: KVM_CAP_PPC_COMPAT_CAPS +:Architectures: powerpc +:Type: vm ioctl +:Parameters: struct kvm_ppc_compat_caps (out) +:Returns: + 0 on successful completion, + -EFAULT if ``struct kvm_ppc_compat_caps`` cannot be written + +IBM POWER system server-based processors provide a compatibility mode feat= ure +where an Nth generation processor can operate in modes consistent with ear= lier +generations such as (N-1) and (N-2). + +This ioctl provides userspace with information about the CPU compatibility= modes +supported by the current host processor for booting the nested KVM guests = on +PowerNV (KVM nested APIv1) and PowerVM (KVM nested APIv2) platforms. + +:: + + struct kvm_ppc_compat_caps { + __u64 flags; /* Reserved for future use */ + __u64 compat_capabilities; /* Capabilities supported by the host */ + }; + +The ``compat_capabilities`` bit field describes the processor compatibility +modes supported by the host. For example, the following bits indicate supp= ort +for specific processor modes. + +:: + + H_GUEST_CAP_POWER9 (bit 1): KVM guests can run in Power9 processor mode + H_GUEST_CAP_POWER10 (bit 2): KVM guests can run in Power10 processor mode + H_GUEST_CAP_POWER11 (bit 3): KVM guests can run in Power11 processor mode + 5. The kvm_run structure =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 --=20 2.50.1 (Apple Git-155)