From nobody Sun May 24 20:33:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 615E1425CE5 for ; Fri, 22 May 2026 14:20:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779459639; cv=none; b=oVT/LcbKjoIo0IYFVNSAVn103F5dHfnYWrjyRgA6bXDxW5yTPUZrxloO5pqW3fWq09+Rscdz6xIqLvQaHAjrPbYV/scRcjMdBihIBImO68D6/dnesRRv8wKf91ymwex0ajKbXl8FT8Q1D+wBlK/v3lS9+DFdLrAA3gKJmDHFtyM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779459639; c=relaxed/simple; bh=6kkH39uuAMnHK9EhOy4eLoqT875Q+QcCAUdLA0htJzY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=O8BtaM6XIOfpZV3JICRua8UygXYdJkZxh0JveNkJJiVQQZUNf+ZXaAqY/fthATTjMrip8x8p3hSxBSMjlvcajwdgvttkGO2I0Eb6jjruJljHUE+PVTzbMzIRpKqbRAc66bYiEwXfKpeveJ+YTowde2qwDxyRhM9zJNydHi9hNFU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JHUAIfg1; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JHUAIfg1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CBBD11F00A3D; Fri, 22 May 2026 14:20:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779459628; bh=iAR6XZ0NwmzxFQ6ob0tLdxPMuUoGCRZoWa9wBuuArgg=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=JHUAIfg1fz0IVFsbHfUu3d1pJBVX9e+Tn997vZHtF45vXGmP9CezjC3H7MlSucT0F /7q1+3VCqNyZRy6YwmLvZKFjSK/wV1RctZXGWeXpjvEMFmuluYLFaXeK9JBdMHUYdR vXjBaraNzMlGj96GOq8DW70//OSW8WUm3qM4FfpGOQnd6MCTTPk65LyQNCB21U6YNQ 9Ja/XVsIkVB1zV+8D5dZzYYMfZBZYwS3N1FeOqn0kJlxs036ZztlFVmWsGfZV+1dPG VMSz1CvWIQdPXKB7lv+w7Vwh+hBVXjLFI/3bwd5XZwAyEYP2seHCOsDOUPPfgpqApZ 1cTyqJiWn0htg== From: Arnd Bergmann To: Ingo Molnar Cc: Arnd Bergmann , Richard Weinberger , Anton Ivanov , Johannes Berg , Thomas Gleixner , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Peter Zijlstra , Will Deacon , Boqun Feng , Gary Guo , Yury Norov , Rasmus Villemoes , Boris Ostrovsky , Alexander Usyskin , Tony Nguyen , Przemek Kitszel , x86@kernel.org, linux-kernel@vger.kernel.org, linux-um@lists.infradead.org, "Savoir-faire Linux Inc." Subject: [PATCH 1/8] x86: remove ts5500 platforms support Date: Fri, 22 May 2026 16:19:52 +0200 Message-Id: <20260522141959.1071595-2-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260522141959.1071595-1-arnd@kernel.org> References: <20260522141959.1071595-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Arnd Bergmann Support for =C3=89lan was removed in 7.1, but the ts5500 platform still depends on it. Remove this one as well, not that it cannot be used any more. Cc: "Savoir-faire Linux Inc." Signed-off-by: Arnd Bergmann --- .../ABI/testing/sysfs-platform-ts5500 | 54 --- MAINTAINERS | 5 - arch/x86/Kconfig | 9 - arch/x86/platform/Makefile | 1 - arch/x86/platform/ts5500/Makefile | 2 - arch/x86/platform/ts5500/ts5500.c | 341 ------------------ 6 files changed, 412 deletions(-) delete mode 100644 Documentation/ABI/testing/sysfs-platform-ts5500 delete mode 100644 arch/x86/platform/ts5500/Makefile delete mode 100644 arch/x86/platform/ts5500/ts5500.c diff --git a/Documentation/ABI/testing/sysfs-platform-ts5500 b/Documentatio= n/ABI/testing/sysfs-platform-ts5500 deleted file mode 100644 index e685957caa12..000000000000 --- a/Documentation/ABI/testing/sysfs-platform-ts5500 +++ /dev/null @@ -1,54 +0,0 @@ -What: /sys/devices/platform/ts5500/adc -Date: January 2013 -KernelVersion: 3.7 -Contact: "Savoir-faire Linux Inc." -Description: - Indicates the presence of an A/D Converter. If it is present, - it will display "1", otherwise "0". - -What: /sys/devices/platform/ts5500/ereset -Date: January 2013 -KernelVersion: 3.7 -Contact: "Savoir-faire Linux Inc." -Description: - Indicates the presence of an external reset. If it is present, - it will display "1", otherwise "0". - -What: /sys/devices/platform/ts5500/id -Date: January 2013 -KernelVersion: 3.7 -Contact: "Savoir-faire Linux Inc." -Description: - Product ID of the TS board. TS-5500 ID is 0x60. - -What: /sys/devices/platform/ts5500/jumpers -Date: January 2013 -KernelVersion: 3.7 -Contact: "Savoir-faire Linux Inc." -Description: - Bitfield showing the jumpers' state. If a jumper is present, - the corresponding bit is set. For instance, 0x0e means jumpers - 2, 3 and 4 are set. - -What: /sys/devices/platform/ts5500/name -Date: July 2014 -KernelVersion: 3.16 -Contact: "Savoir-faire Linux Inc." -Description: - Model name of the TS board, e.g. "TS-5500". - -What: /sys/devices/platform/ts5500/rs485 -Date: January 2013 -KernelVersion: 3.7 -Contact: "Savoir-faire Linux Inc." -Description: - Indicates the presence of the RS485 option. If it is present, - it will display "1", otherwise "0". - -What: /sys/devices/platform/ts5500/sram -Date: January 2013 -KernelVersion: 3.7 -Contact: "Savoir-faire Linux Inc." -Description: - Indicates the presence of the SRAM option. If it is present, - it will display "1", otherwise "0". diff --git a/MAINTAINERS b/MAINTAINERS index e706b468a53f..dd3fceaa78d6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -26402,11 +26402,6 @@ S: Maintained F: Documentation/process/contribution-maturity-model.rst F: Documentation/process/researcher-guidelines.rst =20 -TECHNOLOGIC SYSTEMS TS-5500 PLATFORM SUPPORT -M: "Savoir-faire Linux Inc." -S: Maintained -F: arch/x86/platform/ts5500/ - TECHNOTREND USB IR RECEIVER M: Sean Young L: linux-media@vger.kernel.org diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index f24810015234..a188ed90b1ca 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -3056,15 +3056,6 @@ config GEOS help This option enables system support for the Traverse Technologies GEOS. =20 -config TS5500 - bool "Technologic Systems TS-5500 platform support" - depends on MELAN - select CHECK_SIGNATURE - select NEW_LEDS - select LEDS_CLASS - help - This option enables system support for the Technologic Systems TS-5500. - endif # X86_32 =20 config AMD_NB diff --git a/arch/x86/platform/Makefile b/arch/x86/platform/Makefile index 3ed03a2552d0..727b92d0ca25 100644 --- a/arch/x86/platform/Makefile +++ b/arch/x86/platform/Makefile @@ -10,5 +10,4 @@ obj-y +=3D intel-mid/ obj-y +=3D intel-quark/ obj-y +=3D olpc/ obj-y +=3D scx200/ -obj-y +=3D ts5500/ obj-y +=3D uv/ diff --git a/arch/x86/platform/ts5500/Makefile b/arch/x86/platform/ts5500/M= akefile deleted file mode 100644 index 910fe9e3ffb4..000000000000 --- a/arch/x86/platform/ts5500/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_TS5500) +=3D ts5500.o diff --git a/arch/x86/platform/ts5500/ts5500.c b/arch/x86/platform/ts5500/t= s5500.c deleted file mode 100644 index 0b67da056fd9..000000000000 --- a/arch/x86/platform/ts5500/ts5500.c +++ /dev/null @@ -1,341 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Technologic Systems TS-5500 Single Board Computer support - * - * Copyright (C) 2013-2014 Savoir-faire Linux Inc. - * Vivien Didelot - * - * This driver registers the Technologic Systems TS-5500 Single Board Comp= uter - * (SBC) and its devices, and exposes information to userspace such as jum= pers' - * state or available options. For further information about sysfs entries= , see - * Documentation/ABI/testing/sysfs-platform-ts5500. - * - * This code may be extended to support similar x86-based platforms. - * Actually, the TS-5500 and TS-5400 are supported. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* Product code register */ -#define TS5500_PRODUCT_CODE_ADDR 0x74 -#define TS5500_PRODUCT_CODE 0x60 /* TS-5500 product code */ -#define TS5400_PRODUCT_CODE 0x40 /* TS-5400 product code */ - -/* SRAM/RS-485/ADC options, and RS-485 RTS/Automatic RS-485 flags register= */ -#define TS5500_SRAM_RS485_ADC_ADDR 0x75 -#define TS5500_SRAM BIT(0) /* SRAM option */ -#define TS5500_RS485 BIT(1) /* RS-485 option */ -#define TS5500_ADC BIT(2) /* A/D converter option */ -#define TS5500_RS485_RTS BIT(6) /* RTS for RS-485 */ -#define TS5500_RS485_AUTO BIT(7) /* Automatic RS-485 */ - -/* External Reset/Industrial Temperature Range options register */ -#define TS5500_ERESET_ITR_ADDR 0x76 -#define TS5500_ERESET BIT(0) /* External Reset option */ -#define TS5500_ITR BIT(1) /* Indust. Temp. Range option */ - -/* LED/Jumpers register */ -#define TS5500_LED_JP_ADDR 0x77 -#define TS5500_LED BIT(0) /* LED flag */ -#define TS5500_JP1 BIT(1) /* Automatic CMOS */ -#define TS5500_JP2 BIT(2) /* Enable Serial Console */ -#define TS5500_JP3 BIT(3) /* Write Enable Drive A */ -#define TS5500_JP4 BIT(4) /* Fast Console (115K baud) */ -#define TS5500_JP5 BIT(5) /* User Jumper */ -#define TS5500_JP6 BIT(6) /* Console on COM1 (req. JP2) */ -#define TS5500_JP7 BIT(7) /* Undocumented (Unused) */ - -/* A/D Converter registers */ -#define TS5500_ADC_CONV_BUSY_ADDR 0x195 /* Conversion state register */ -#define TS5500_ADC_CONV_BUSY BIT(0) -#define TS5500_ADC_CONV_INIT_LSB_ADDR 0x196 /* Start conv. / LSB register = */ -#define TS5500_ADC_CONV_MSB_ADDR 0x197 /* MSB register */ -#define TS5500_ADC_CONV_DELAY 12 /* usec */ - -/** - * struct ts5500_sbc - TS-5500 board description - * @name: Board model name. - * @id: Board product ID. - * @sram: Flag for SRAM option. - * @rs485: Flag for RS-485 option. - * @adc: Flag for Analog/Digital converter option. - * @ereset: Flag for External Reset option. - * @itr: Flag for Industrial Temperature Range option. - * @jumpers: Bitfield for jumpers' state. - */ -struct ts5500_sbc { - const char *name; - int id; - bool sram; - bool rs485; - bool adc; - bool ereset; - bool itr; - u8 jumpers; -}; - -/* Board signatures in BIOS shadow RAM */ -static const struct { - const char * const string; - const ssize_t offset; -} ts5500_signatures[] __initconst =3D { - { "TS-5x00 AMD Elan", 0xb14 }, -}; - -static int __init ts5500_check_signature(void) -{ - void __iomem *bios; - int i, ret =3D -ENODEV; - - bios =3D ioremap(0xf0000, 0x10000); - if (!bios) - return -ENOMEM; - - for (i =3D 0; i < ARRAY_SIZE(ts5500_signatures); i++) { - if (check_signature(bios + ts5500_signatures[i].offset, - ts5500_signatures[i].string, - strlen(ts5500_signatures[i].string))) { - ret =3D 0; - break; - } - } - - iounmap(bios); - return ret; -} - -static int __init ts5500_detect_config(struct ts5500_sbc *sbc) -{ - u8 tmp; - int ret =3D 0; - - if (!request_region(TS5500_PRODUCT_CODE_ADDR, 4, "ts5500")) - return -EBUSY; - - sbc->id =3D inb(TS5500_PRODUCT_CODE_ADDR); - if (sbc->id =3D=3D TS5500_PRODUCT_CODE) { - sbc->name =3D "TS-5500"; - } else if (sbc->id =3D=3D TS5400_PRODUCT_CODE) { - sbc->name =3D "TS-5400"; - } else { - pr_err("ts5500: unknown product code 0x%x\n", sbc->id); - ret =3D -ENODEV; - goto cleanup; - } - - tmp =3D inb(TS5500_SRAM_RS485_ADC_ADDR); - sbc->sram =3D tmp & TS5500_SRAM; - sbc->rs485 =3D tmp & TS5500_RS485; - sbc->adc =3D tmp & TS5500_ADC; - - tmp =3D inb(TS5500_ERESET_ITR_ADDR); - sbc->ereset =3D tmp & TS5500_ERESET; - sbc->itr =3D tmp & TS5500_ITR; - - tmp =3D inb(TS5500_LED_JP_ADDR); - sbc->jumpers =3D tmp & ~TS5500_LED; - -cleanup: - release_region(TS5500_PRODUCT_CODE_ADDR, 4); - return ret; -} - -static ssize_t name_show(struct device *dev, struct device_attribute *attr, - char *buf) -{ - struct ts5500_sbc *sbc =3D dev_get_drvdata(dev); - - return sprintf(buf, "%s\n", sbc->name); -} -static DEVICE_ATTR_RO(name); - -static ssize_t id_show(struct device *dev, struct device_attribute *attr, - char *buf) -{ - struct ts5500_sbc *sbc =3D dev_get_drvdata(dev); - - return sprintf(buf, "0x%.2x\n", sbc->id); -} -static DEVICE_ATTR_RO(id); - -static ssize_t jumpers_show(struct device *dev, struct device_attribute *a= ttr, - char *buf) -{ - struct ts5500_sbc *sbc =3D dev_get_drvdata(dev); - - return sprintf(buf, "0x%.2x\n", sbc->jumpers >> 1); -} -static DEVICE_ATTR_RO(jumpers); - -#define TS5500_ATTR_BOOL(_field) \ - static ssize_t _field##_show(struct device *dev, \ - struct device_attribute *attr, char *buf) \ - { \ - struct ts5500_sbc *sbc =3D dev_get_drvdata(dev); \ - \ - return sprintf(buf, "%d\n", sbc->_field); \ - } \ - static DEVICE_ATTR_RO(_field) - -TS5500_ATTR_BOOL(sram); -TS5500_ATTR_BOOL(rs485); -TS5500_ATTR_BOOL(adc); -TS5500_ATTR_BOOL(ereset); -TS5500_ATTR_BOOL(itr); - -static struct attribute *ts5500_attributes[] =3D { - &dev_attr_id.attr, - &dev_attr_name.attr, - &dev_attr_jumpers.attr, - &dev_attr_sram.attr, - &dev_attr_rs485.attr, - &dev_attr_adc.attr, - &dev_attr_ereset.attr, - &dev_attr_itr.attr, - NULL -}; - -static const struct attribute_group ts5500_attr_group =3D { - .attrs =3D ts5500_attributes, -}; - -static struct resource ts5500_dio1_resource[] =3D { - DEFINE_RES_IRQ_NAMED(7, "DIO1 interrupt"), -}; - -static struct platform_device ts5500_dio1_pdev =3D { - .name =3D "ts5500-dio1", - .id =3D -1, - .resource =3D ts5500_dio1_resource, - .num_resources =3D 1, -}; - -static struct resource ts5500_dio2_resource[] =3D { - DEFINE_RES_IRQ_NAMED(6, "DIO2 interrupt"), -}; - -static struct platform_device ts5500_dio2_pdev =3D { - .name =3D "ts5500-dio2", - .id =3D -1, - .resource =3D ts5500_dio2_resource, - .num_resources =3D 1, -}; - -static void ts5500_led_set(struct led_classdev *led_cdev, - enum led_brightness brightness) -{ - outb(!!brightness, TS5500_LED_JP_ADDR); -} - -static enum led_brightness ts5500_led_get(struct led_classdev *led_cdev) -{ - return (inb(TS5500_LED_JP_ADDR) & TS5500_LED) ? LED_FULL : LED_OFF; -} - -static struct led_classdev ts5500_led_cdev =3D { - .name =3D "ts5500:green:", - .brightness_set =3D ts5500_led_set, - .brightness_get =3D ts5500_led_get, -}; - -static int ts5500_adc_convert(u8 ctrl) -{ - u8 lsb, msb; - - /* Start conversion (ensure the 3 MSB are set to 0) */ - outb(ctrl & 0x1f, TS5500_ADC_CONV_INIT_LSB_ADDR); - - /* - * The platform has CPLD logic driving the A/D converter. - * The conversion must complete within 11 microseconds, - * otherwise we have to re-initiate a conversion. - */ - udelay(TS5500_ADC_CONV_DELAY); - if (inb(TS5500_ADC_CONV_BUSY_ADDR) & TS5500_ADC_CONV_BUSY) - return -EBUSY; - - /* Read the raw data */ - lsb =3D inb(TS5500_ADC_CONV_INIT_LSB_ADDR); - msb =3D inb(TS5500_ADC_CONV_MSB_ADDR); - - return (msb << 8) | lsb; -} - -static struct max197_platform_data ts5500_adc_pdata =3D { - .convert =3D ts5500_adc_convert, -}; - -static struct platform_device ts5500_adc_pdev =3D { - .name =3D "max197", - .id =3D -1, - .dev =3D { - .platform_data =3D &ts5500_adc_pdata, - }, -}; - -static int __init ts5500_init(void) -{ - struct platform_device *pdev; - struct ts5500_sbc *sbc; - int err; - - /* - * There is no DMI available or PCI bridge subvendor info, - * only the BIOS provides a 16-bit identification call. - * It is safer to find a signature in the BIOS shadow RAM. - */ - err =3D ts5500_check_signature(); - if (err) - return err; - - pdev =3D platform_device_register_simple("ts5500", -1, NULL, 0); - if (IS_ERR(pdev)) - return PTR_ERR(pdev); - - sbc =3D devm_kzalloc(&pdev->dev, sizeof(struct ts5500_sbc), GFP_KERNEL); - if (!sbc) { - err =3D -ENOMEM; - goto error; - } - - err =3D ts5500_detect_config(sbc); - if (err) - goto error; - - platform_set_drvdata(pdev, sbc); - - err =3D sysfs_create_group(&pdev->dev.kobj, &ts5500_attr_group); - if (err) - goto error; - - if (sbc->id =3D=3D TS5500_PRODUCT_CODE) { - ts5500_dio1_pdev.dev.parent =3D &pdev->dev; - if (platform_device_register(&ts5500_dio1_pdev)) - dev_warn(&pdev->dev, "DIO1 block registration failed\n"); - ts5500_dio2_pdev.dev.parent =3D &pdev->dev; - if (platform_device_register(&ts5500_dio2_pdev)) - dev_warn(&pdev->dev, "DIO2 block registration failed\n"); - } - - if (led_classdev_register(&pdev->dev, &ts5500_led_cdev)) - dev_warn(&pdev->dev, "LED registration failed\n"); - - if (sbc->adc) { - ts5500_adc_pdev.dev.parent =3D &pdev->dev; - if (platform_device_register(&ts5500_adc_pdev)) - dev_warn(&pdev->dev, "ADC registration failed\n"); - } - - return 0; -error: - platform_device_unregister(pdev); - return err; -} -device_initcall(ts5500_init); --=20 2.39.5 From nobody Sun May 24 20:33:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA1E5449EB6 for ; Fri, 22 May 2026 14:20:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779459642; cv=none; b=a3FOu6M+6kYuEHAcZ1Wbv1ctHE+us8igl/whr0ZfnISytQTxNO3ubuUoJd3AEiOrrAaVVg0JHKPLGYD26tnKGodP9QoxIsvKkh/gSUOxMAjWVmZU+pGqc6/ciPOicGUqHex6pYf8agvyMiRWeCxOOYG46PqMAjQmDQj9Czs7A+Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779459642; c=relaxed/simple; bh=rms8v8da6YwHU/fexmhwIaKhosdhS8a5enXtjSD9FEQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=AIhLux1CE4D7oVFokNFuZfuGQuRf+zqcwxCX63K1JOzlC5Si25mE/9Qq5nby1sjQE4qYgb3HGjXP6Z08nDADlpa8MC5w7Hzkb6YbI/+GEjjewZbtLhpscuytGzjzPiTJgs229nkOwOxvo9sf2tmGIySCUSN2tphxSyjby2pEaW4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=E+W7wlmM; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="E+W7wlmM" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C04131F00A3E; Fri, 22 May 2026 14:20:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779459633; bh=KMOg+jIFzKoR+MDQSP+sdqbBfrIpOv5CDMN5EJGNh5c=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=E+W7wlmM3XJVZwZz2XX9vHRsZGSo+lrXIM85vfaQ8xDGxQLgQSvEvXFpR/EbiLbPL hKhdIlR20CaaUl5QmgRrqgs8493yKARsqpG1gYSDCpzUFYBMwyVURUHzALAvI1moiO CdYQSIA3Qxag8kLJRJLlmqM1yN7S/cNsp8xzzpZcB64z3KJHsnOwF/mQYwyQvS3Vta 2Sl8eKoJfXHcAMaS4DpeWdUbcrNmQ804CxKHqC2NDHMoIv/fvbu1RjTsulE9rykjQo SqV5fYAu+miQFBNbXav4cqb6SIajfXfMoTQlz2QpyYwuOb2GJg1dcBnMM4S00VhWAc keuiPXXwjI2Eg== From: Arnd Bergmann To: Ingo Molnar Cc: Arnd Bergmann , Richard Weinberger , Anton Ivanov , Johannes Berg , Thomas Gleixner , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Peter Zijlstra , Will Deacon , Boqun Feng , Gary Guo , Yury Norov , Rasmus Villemoes , Boris Ostrovsky , Alexander Usyskin , Tony Nguyen , Przemek Kitszel , x86@kernel.org, linux-kernel@vger.kernel.org, linux-um@lists.infradead.org Subject: [PATCH 2/8] =?UTF-8?q?x86:=20remove=20AMD=20=C3=89lan=20remnants?= Date: Fri, 22 May 2026 16:19:53 +0200 Message-Id: <20260522141959.1071595-3-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260522141959.1071595-1-arnd@kernel.org> References: <20260522141959.1071595-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Arnd Bergmann There is one more leftover line in Kconfig and the detection for AMD Generation 4 CPUs (5k86 and =C3=89lan) that can now get removed following the increase of the minimum CPU level to 586TSC. Signed-off-by: Arnd Bergmann --- arch/x86/Kconfig.cpu | 1 - arch/x86/kernel/cpu/amd.c | 20 -------------------- 2 files changed, 21 deletions(-) diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 1377edd9a997..f4a12b74bed3 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -32,7 +32,6 @@ choice - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird). - "Crusoe" for the Transmeta Crusoe series. - "Efficeon" for the Transmeta Efficeon series. - - "AMD Elan" for the 32-bit AMD Elan embedded CPU. - "GeodeGX1" for Geode GX1 (Cyrix MediaGX). - "Geode GX/LX" For AMD Geode GX and LX processors. - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3. diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 62f74a7f2f8d..b04e1f6fe430 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -91,25 +91,6 @@ __asm__(".text\n" "vide: ret\n"); #endif =20 -static void init_amd_k5(struct cpuinfo_x86 *c) -{ -#ifdef CONFIG_X86_32 -/* - * General Systems BIOSen alias the cpu frequency registers - * of the Elan at 0x000df000. Unfortunately, one of the Linux - * drivers subsequently pokes it, and changes the CPU speed. - * Workaround : Remove the unneeded alias. - */ -#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ -#define CBAR_ENB (0x80000000) -#define CBAR_KEY (0X000000CB) - if (c->x86_model =3D=3D 9 || c->x86_model =3D=3D 10) { - if (inl(CBAR) & CBAR_ENB) - outl(0 | CBAR_KEY, CBAR); - } -#endif -} - static void init_amd_k6(struct cpuinfo_x86 *c) { #ifdef CONFIG_X86_32 @@ -1065,7 +1046,6 @@ static void init_amd(struct cpuinfo_x86 *c) clear_cpu_cap(c, X86_FEATURE_MCE); =20 switch (c->x86) { - case 4: init_amd_k5(c); break; case 5: init_amd_k6(c); break; case 6: init_amd_k7(c); break; case 0xf: init_amd_k8(c); break; --=20 2.39.5 From nobody Sun May 24 20:33:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37DC744B68D for ; Fri, 22 May 2026 14:20:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779459650; cv=none; b=lb9FKz2UkCPyYLrC275aHDO0LEozHbkTeU9BrMPGwIM9sFQ95hFfo7FIxNaA+yymN4HNgziiC/4QH1+xAeO9crXcjRLkF6MbWA1Mjn0Pl+FvODQTreoydtfEL9o87cK02JkvRJhHfXnMp2UUC28cw6vIStfPr5BBOuUVO3FzPMs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779459650; c=relaxed/simple; bh=WWarg/YJHDb+vebZbVa/3W4p4M3qNotBLCEkNfrt1aM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Wk+IWF/nGmWR330urs4u1v6JvEk97nI8hs32zfLO0dYu0YEHcMBeMJVy2UABsBRhopZyMNZXZTYMmL67GnXyvzD/usOc1X4jL4z6QLZfKwJrIYn8TUX/ywvHqtoG4uC4tf2yNXHxvLZMzmEPmmh0+UjerfkEIzGUAW+zDT2cLuQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eB3AKZw6; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eB3AKZw6" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 843971F00A3F; Fri, 22 May 2026 14:20:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779459637; bh=IwI+0IE7UYNHP6pLGdqMWIPaS64i6mHL5V4w1xLWQFk=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=eB3AKZw6fPVwL1oR8MQ6AsLdNMTptplxtUAU9pP23/eFcCeyJQ2zDYJCy2ZfHuSTw UGN/VYx2XGwb6LK2abVBD8GYomypffpLJZU2avsylWY5mOE6Jha9ZBjYPELVSDPL/O v0ODdbfYwX7gzzvzyoSj9HB1OsyvgMvVUvHvcGg/CUwjbN1Q86DmRHe0RV9SSnTXAR FiykGSt7eJHuEKLMtqrWcmwb1x+/dyE36cTVz6JG43zv/4GNup9tj9jJSwv5gVexJb EenkrIs7OwSKrc68EsbyMNt28vQRS0Nex4TkOdkFec1KmggjGXs+VARfs3yHvVrzdi RkllDLwugyBeQ== From: Arnd Bergmann To: Ingo Molnar Cc: Arnd Bergmann , Richard Weinberger , Anton Ivanov , Johannes Berg , Thomas Gleixner , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Peter Zijlstra , Will Deacon , Boqun Feng , Gary Guo , Yury Norov , Rasmus Villemoes , Boris Ostrovsky , Alexander Usyskin , Tony Nguyen , Przemek Kitszel , x86@kernel.org, linux-kernel@vger.kernel.org, linux-um@lists.infradead.org Subject: [PATCH 3/8] x86: make TSC usage unconditional Date: Fri, 22 May 2026 16:19:54 +0200 Message-Id: <20260522141959.1071595-4-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260522141959.1071595-1-arnd@kernel.org> References: <20260522141959.1071595-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann There are multiple levels of functionality of the TSC that are checked for: built into the kernel, present in the CPU, reliable and probably more. Since the TSC-less CPUs are no longer supported in the kernel, remove all checks for CONFIG_TSC and X86_FEATURE_TSC and assume it's always there. Unfortunately the tsc_clocksource_reliable checks are still required though. Signed-off-by: Arnd Bergmann --- Documentation/virt/kvm/x86/timekeeping.rst | 1 - arch/x86/Kconfig | 1 - arch/x86/Kconfig.cpu | 1 - arch/x86/events/msr.c | 5 ---- arch/x86/include/asm/timex.h | 3 --- arch/x86/include/asm/trace_clock.h | 8 ------- arch/x86/include/asm/tsc.h | 13 ---------- arch/x86/kernel/Makefile | 4 ++-- arch/x86/kernel/apic/apic.c | 23 +++++++----------- arch/x86/kernel/apic/io_apic.c | 22 +---------------- arch/x86/kernel/cpu/centaur.c | 2 -- arch/x86/kernel/cpu/common.c | 4 +--- arch/x86/kernel/cpu/proc.c | 15 +++++------- arch/x86/kernel/i8253.c | 3 --- arch/x86/kernel/tsc.c | 28 ++-------------------- arch/x86/lib/kaslr.c | 20 ++++------------ arch/x86/xen/time.c | 2 -- drivers/net/ethernet/intel/igc/igc_ptp.c | 4 ++-- drivers/ptp/Kconfig | 2 +- tools/power/cpupower/debug/kernel/Makefile | 5 +--- 20 files changed, 29 insertions(+), 137 deletions(-) diff --git a/Documentation/virt/kvm/x86/timekeeping.rst b/Documentation/vir= t/kvm/x86/timekeeping.rst index 21ae7efa29ba..e8519451000d 100644 --- a/Documentation/virt/kvm/x86/timekeeping.rst +++ b/Documentation/virt/kvm/x86/timekeeping.rst @@ -471,7 +471,6 @@ The following feature bits are used by Linux to signal = various TSC attributes, but they can only be taken to be meaningful for UP or single node systems. =20 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -X86_FEATURE_TSC The TSC is available in hardware X86_FEATURE_RDTSCP The RDTSCP instruction is available X86_FEATURE_CONSTANT_TSC The TSC rate is unchanged with P-states X86_FEATURE_NONSTOP_TSC The TSC does not stop in C-states diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index a188ed90b1ca..2fd99a5b4a68 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -683,7 +683,6 @@ config X86_INTEL_QUARK depends on X86_32 depends on X86_EXTENDED_PLATFORM depends on X86_PLATFORM_DEVICES - depends on X86_TSC depends on PCI depends on PCI_GOANY depends on X86_IO_APIC diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index f4a12b74bed3..fe0246477345 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -261,7 +261,6 @@ config X86_USE_PPRO_CHECKSUM =20 config X86_TSC def_bool y - depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6= || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX = || M586TSC || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MATOM) || X86= _64 =20 config X86_HAVE_PAE def_bool y diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 76d6418c5055..130f1a8c8800 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -229,11 +229,6 @@ static struct pmu pmu_msr =3D { =20 static int __init msr_init(void) { - if (!boot_cpu_has(X86_FEATURE_TSC)) { - pr_cont("no MSR PMU driver.\n"); - return 0; - } - msr_mask =3D perf_msr_probe(msr, PERF_MSR_EVENT_MAX, true, NULL); =20 perf_pmu_register(&pmu_msr, "msr", -1); diff --git a/arch/x86/include/asm/timex.h b/arch/x86/include/asm/timex.h index 956e4145311b..ec2e37c19760 100644 --- a/arch/x86/include/asm/timex.h +++ b/arch/x86/include/asm/timex.h @@ -7,9 +7,6 @@ =20 static inline unsigned long random_get_entropy(void) { - if (!IS_ENABLED(CONFIG_X86_TSC) && - !cpu_feature_enabled(X86_FEATURE_TSC)) - return random_get_entropy_fallback(); return rdtsc(); } #define random_get_entropy random_get_entropy diff --git a/arch/x86/include/asm/trace_clock.h b/arch/x86/include/asm/trac= e_clock.h index 7061a5650969..1efab284c32a 100644 --- a/arch/x86/include/asm/trace_clock.h +++ b/arch/x86/include/asm/trace_clock.h @@ -5,17 +5,9 @@ #include #include =20 -#ifdef CONFIG_X86_TSC - extern u64 notrace trace_clock_x86_tsc(void); =20 # define ARCH_TRACE_CLOCKS \ { trace_clock_x86_tsc, "x86-tsc", .in_ns =3D 0 }, =20 -#else /* !CONFIG_X86_TSC */ - -#define ARCH_TRACE_CLOCKS - -#endif - #endif /* _ASM_X86_TRACE_CLOCK_H */ diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h index 4f7f09f50552..88d9d2a22152 100644 --- a/arch/x86/include/asm/tsc.h +++ b/arch/x86/include/asm/tsc.h @@ -76,9 +76,6 @@ extern void disable_TSC(void); =20 static inline cycles_t get_cycles(void) { - if (!IS_ENABLED(CONFIG_X86_TSC) && - !cpu_feature_enabled(X86_FEATURE_TSC)) - return 0; return rdtsc(); } #define get_cycles get_cycles @@ -94,25 +91,15 @@ extern unsigned long native_calibrate_tsc(void); extern unsigned long long native_sched_clock_from_tsc(u64 tsc); =20 extern int tsc_clocksource_reliable; -#ifdef CONFIG_X86_TSC extern bool tsc_async_resets; -#else -# define tsc_async_resets false -#endif =20 /* * Boot-time check whether the TSCs are synchronized across * all CPUs/cores: */ -#ifdef CONFIG_X86_TSC extern bool tsc_store_and_check_tsc_adjust(bool bootcpu); extern void tsc_verify_tsc_adjust(bool resume); extern void check_tsc_sync_target(void); -#else -static inline bool tsc_store_and_check_tsc_adjust(bool bootcpu) { return f= alse; } -static inline void tsc_verify_tsc_adjust(bool resume) { } -static inline void check_tsc_sync_target(void) { } -#endif =20 extern int notsc_setup(char *); extern void tsc_save_sched_clock_state(void); diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index 47a32f583930..31f46fd00527 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -108,7 +108,7 @@ apm-y :=3D apm_32.o obj-$(CONFIG_APM) +=3D apm.o obj-$(CONFIG_SMP) +=3D smp.o obj-$(CONFIG_SMP) +=3D smpboot.o -obj-$(CONFIG_X86_TSC) +=3D tsc_sync.o +obj-y +=3D tsc_sync.o obj-$(CONFIG_SMP) +=3D setup_percpu.o obj-$(CONFIG_X86_MPPARSE) +=3D mpparse.o obj-y +=3D apic/ @@ -117,7 +117,7 @@ obj-$(CONFIG_DYNAMIC_FTRACE) +=3D ftrace.o obj-$(CONFIG_FUNCTION_TRACER) +=3D ftrace_$(BITS).o obj-$(CONFIG_FUNCTION_GRAPH_TRACER) +=3D ftrace.o obj-$(CONFIG_FTRACE_SYSCALLS) +=3D ftrace.o -obj-$(CONFIG_X86_TSC) +=3D trace_clock.o +obj-y +=3D trace_clock.o obj-$(CONFIG_TRACING) +=3D trace.o obj-$(CONFIG_RETHOOK) +=3D rethook.o obj-$(CONFIG_VMCORE_INFO) +=3D vmcore_info_$(BITS).o diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 8c614750a19b..254a6ce6487c 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -666,8 +666,7 @@ static void __init lapic_cal_handler(struct clock_event= _device *dev) long tapic =3D apic_read(APIC_TMCCT); u32 pm =3D acpi_pm_read_early(); =20 - if (boot_cpu_has(X86_FEATURE_TSC)) - tsc =3D rdtsc(); + tsc =3D rdtsc(); =20 switch (lapic_cal_loops++) { case 0: @@ -727,13 +726,11 @@ calibrate_by_pmtimer(u32 deltapm, long *delta, long *= deltatsc) *delta =3D (long)res; =20 /* Correct the tsc counter value */ - if (boot_cpu_has(X86_FEATURE_TSC)) { - res =3D (((u64)(*deltatsc)) * pm_100ms); - do_div(res, deltapm); - apic_pr_verbose("TSC delta adjusted to PM-Timer: %lu (%ld)\n", - (unsigned long)res, *deltatsc); - *deltatsc =3D (long)res; - } + res =3D (((u64)(*deltatsc)) * pm_100ms); + do_div(res, deltapm); + apic_pr_verbose("TSC delta adjusted to PM-Timer: %lu (%ld)\n", + (unsigned long)res, *deltatsc); + *deltatsc =3D (long)res; =20 return 0; } @@ -902,12 +899,10 @@ static int __init calibrate_APIC_clock(void) apic_pr_verbose("..... mult: %u\n", lapic_clockevent.mult); apic_pr_verbose("..... calibration result: %u\n", lapic_timer_period); =20 - if (boot_cpu_has(X86_FEATURE_TSC)) { - delta_tsc_khz =3D (deltatsc * HZ) / (1000 * LAPIC_CAL_LOOPS); + delta_tsc_khz =3D (deltatsc * HZ) / (1000 * LAPIC_CAL_LOOPS); =20 - apic_pr_verbose("..... CPU clock speed is %ld.%03ld MHz.\n", - delta_tsc_khz / 1000, delta_tsc_khz % 1000); - } + apic_pr_verbose("..... CPU clock speed is %ld.%03ld MHz.\n", + delta_tsc_khz / 1000, delta_tsc_khz % 1000); =20 bus_khz =3D (long)lapic_timer_period * HZ / 1000; apic_pr_verbose("..... host bus clock speed is %ld.%03ld MHz.\n", diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index 352ed5558cbc..e8eb18d859ef 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1491,23 +1491,6 @@ static void __init delay_with_tsc(void) } while ((now - start) < 40000000000ULL / HZ && time_before_eq(jiffies, e= nd)); } =20 -static void __init delay_without_tsc(void) -{ - unsigned long end =3D jiffies + 4; - int band =3D 1; - - /* - * We don't know any frequency yet, but waiting for - * 40940000000/HZ cycles is safe: - * 4 GHz =3D=3D 10 jiffies - * 1 GHz =3D=3D 40 jiffies - * 1 << 1 + 1 << 2 +...+ 1 << 11 =3D 4094 - */ - do { - __delay(((1U << band++) * 10000000UL) / HZ); - } while (band < 12 && time_before_eq(jiffies, end)); -} - /* * There is a nasty bug in some older SMP boards, their mptable lies * about the timer IRQ. We do the following to work around the situation: @@ -1524,10 +1507,7 @@ static int __init timer_irq_works(void) return 1; =20 local_irq_enable(); - if (boot_cpu_has(X86_FEATURE_TSC)) - delay_with_tsc(); - else - delay_without_tsc(); + delay_with_tsc(); =20 /* * Expect a few ticks at least, to be sure some possible diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c index 681d2da49341..75b4de9c4d44 100644 --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -140,8 +140,6 @@ static void init_centaur(struct cpuinfo_x86 *c) name =3D "C6"; fcr_set =3D ECX8|DSMC|EDCTLB|EMMX|ERETSTK; fcr_clr =3D DPDC; - pr_notice("Disabling bugged TSC.\n"); - clear_cpu_cap(c, X86_FEATURE_TSC); break; case 8: switch (c->x86_stepping) { diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index a3df21d26460..6943d3aff580 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2471,9 +2471,7 @@ void cpu_init(void) #endif pr_debug("Initializing CPU#%d\n", cpu); =20 - if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || - boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) - cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); + cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); =20 if (IS_ENABLED(CONFIG_X86_64)) { loadsegment(fs, 0); diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c index 6571d432cbe3..8086c39c2922 100644 --- a/arch/x86/kernel/cpu/proc.c +++ b/arch/x86/kernel/cpu/proc.c @@ -64,7 +64,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) { struct cpuinfo_x86 *c =3D v; unsigned int cpu; - int i; + int freq, i; =20 cpu =3D c->cpu_index; seq_printf(m, "processor\t: %u\n" @@ -85,14 +85,11 @@ static int show_cpuinfo(struct seq_file *m, void *v) if (c->microcode) seq_printf(m, "microcode\t: 0x%x\n", c->microcode); =20 - if (cpu_has(c, X86_FEATURE_TSC)) { - int freq =3D arch_freq_get_on_cpu(cpu); - - if (freq < 0) - seq_puts(m, "cpu MHz\t\t: Unknown\n"); - else - seq_printf(m, "cpu MHz\t\t: %u.%03u\n", freq / 1000, (freq % 1000)); - } + freq =3D arch_freq_get_on_cpu(cpu); + if (freq < 0) + seq_puts(m, "cpu MHz\t\t: Unknown\n"); + else + seq_printf(m, "cpu MHz\t\t: %u.%03u\n", freq / 1000, (freq % 1000)); =20 /* Cache size */ if (c->x86_cache_size) diff --git a/arch/x86/kernel/i8253.c b/arch/x86/kernel/i8253.c index cb9852ad6098..0c91426e4a08 100644 --- a/arch/x86/kernel/i8253.c +++ b/arch/x86/kernel/i8253.c @@ -31,9 +31,6 @@ struct clock_event_device *global_clock_event; */ static bool __init use_pit(void) { - if (!IS_ENABLED(CONFIG_X86_TSC) || !boot_cpu_has(X86_FEATURE_TSC)) - return true; - /* This also returns true when APIC is disabled */ return apic_needs_pit(); } diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index c5110eb554bc..e7a43471783f 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -305,23 +305,11 @@ int check_tsc_unstable(void) } EXPORT_SYMBOL_GPL(check_tsc_unstable); =20 -#ifdef CONFIG_X86_TSC int __init notsc_setup(char *str) { mark_tsc_unstable("boot parameter notsc"); return 1; } -#else -/* - * disable flag for tsc. Takes effect by clearing the TSC cpu flag - * in cpu/common.c - */ -int __init notsc_setup(char *str) -{ - setup_clear_cpu_cap(X86_FEATURE_TSC); - return 1; -} -#endif __setup("notsc", notsc_setup); =20 enum { @@ -942,9 +930,6 @@ void recalibrate_cpu_khz(void) #ifndef CONFIG_SMP unsigned long cpu_khz_old =3D cpu_khz; =20 - if (!boot_cpu_has(X86_FEATURE_TSC)) - return; - cpu_khz =3D x86_platform.calibrate_cpu(); tsc_khz =3D x86_platform.calibrate_tsc(); if (tsc_khz =3D=3D 0) @@ -1059,8 +1044,6 @@ static struct notifier_block time_cpufreq_notifier_bl= ock =3D { =20 static int __init cpufreq_register_tsc_scaling(void) { - if (!boot_cpu_has(X86_FEATURE_TSC)) - return 0; if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) return 0; cpufreq_register_notifier(&time_cpufreq_notifier_block, @@ -1266,7 +1249,7 @@ static void __init check_system_tsc_reliable(void) */ int unsynchronized_tsc(void) { - if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_unstable) + if (tsc_unstable) return 1; =20 #ifdef CONFIG_SMP @@ -1416,7 +1399,7 @@ static void tsc_refine_calibration_work(struct work_s= truct *work) =20 static int __init init_tsc_clocksource(void) { - if (!boot_cpu_has(X86_FEATURE_TSC) || !tsc_khz) + if (!tsc_khz) return 0; =20 if (tsc_unstable) { @@ -1515,8 +1498,6 @@ static void __init tsc_enable_sched_clock(void) =20 void __init tsc_early_init(void) { - if (!boot_cpu_has(X86_FEATURE_TSC)) - return; /* Don't change UV TSC multi-chassis synchronization */ if (is_early_uv_system()) return; @@ -1530,11 +1511,6 @@ void __init tsc_early_init(void) =20 void __init tsc_init(void) { - if (!cpu_feature_enabled(X86_FEATURE_TSC)) { - setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); - return; - } - /* * native_calibrate_cpu_early can only calibrate using methods that are * available early in boot. diff --git a/arch/x86/lib/kaslr.c b/arch/x86/lib/kaslr.c index 8c7cd115b484..9984eeeb1a7c 100644 --- a/arch/x86/lib/kaslr.c +++ b/arch/x86/lib/kaslr.c @@ -54,7 +54,6 @@ unsigned long kaslr_get_random_long(const char *purpose) const unsigned long mix_const =3D 0x3f39e593UL; #endif unsigned long raw, random =3D get_boot_seed(); - bool use_i8254 =3D true; =20 if (purpose) { debug_putstr(purpose); @@ -66,24 +65,13 @@ unsigned long kaslr_get_random_long(const char *purpose) debug_putstr(" RDRAND"); if (rdrand_long(&raw)) { random ^=3D raw; - use_i8254 =3D false; } } =20 - if (has_cpuflag(X86_FEATURE_TSC)) { - if (purpose) - debug_putstr(" RDTSC"); - raw =3D rdtsc(); - - random ^=3D raw; - use_i8254 =3D false; - } - - if (use_i8254) { - if (purpose) - debug_putstr(" i8254"); - random ^=3D i8254(); - } + if (purpose) + debug_putstr(" RDTSC"); + raw =3D rdtsc(); + random ^=3D raw; =20 /* Circular multiply for better bit diffusion */ asm(_ASM_MUL "%3" diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c index d62c14334b35..604fdc941468 100644 --- a/arch/x86/xen/time.c +++ b/arch/x86/xen/time.c @@ -541,8 +541,6 @@ static void __init xen_time_init(void) xen_read_wallclock(&tp); do_settimeofday64(&tp); =20 - setup_force_cpu_cap(X86_FEATURE_TSC); - /* * We check ahead on the primary time info if this * bit is supported hence speeding up Xen clocksource. diff --git a/drivers/net/ethernet/intel/igc/igc_ptp.c b/drivers/net/etherne= t/intel/igc/igc_ptp.c index 3d6b2264164a..3551a83ef90b 100644 --- a/drivers/net/ethernet/intel/igc/igc_ptp.c +++ b/drivers/net/ethernet/intel/igc/igc_ptp.c @@ -947,7 +947,7 @@ int igc_ptp_hwtstamp_get(struct net_device *netdev, */ static bool igc_is_crosststamp_supported(struct igc_adapter *adapter) { - if (!IS_ENABLED(CONFIG_X86_TSC)) + if (!IS_ENABLED(CONFIG_X86)) return false; =20 /* FIXME: it was noticed that enabling support for PCIe PTM in @@ -965,7 +965,7 @@ static bool igc_is_crosststamp_supported(struct igc_ada= pter *adapter) =20 static struct system_counterval_t igc_device_tstamp_to_system(u64 tstamp) { -#if IS_ENABLED(CONFIG_X86_TSC) && !defined(CONFIG_UML) +#if IS_ENABLED(CONFIG_X86) && !defined(CONFIG_UML) return (struct system_counterval_t) { .cs_id =3D CSID_X86_ART, .cycles =3D tstamp, diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig index b93640ca08b7..585cf98ae42f 100644 --- a/drivers/ptp/Kconfig +++ b/drivers/ptp/Kconfig @@ -133,7 +133,7 @@ config PTP_1588_CLOCK_KVM =20 config PTP_1588_CLOCK_VMCLOCK tristate "Virtual machine PTP clock" - depends on X86_TSC || ARM_ARCH_TIMER + depends on X86 || ARM_ARCH_TIMER depends on PTP_1588_CLOCK && ARCH_SUPPORTS_INT128 default PTP_1588_CLOCK_KVM help diff --git a/tools/power/cpupower/debug/kernel/Makefile b/tools/power/cpupo= wer/debug/kernel/Makefile index 7b5c43684be1..89954bba1453 100644 --- a/tools/power/cpupower/debug/kernel/Makefile +++ b/tools/power/cpupower/debug/kernel/Makefile @@ -1,12 +1,9 @@ # SPDX-License-Identifier: GPL-2.0 -obj-m :=3D +obj-m :=3D cpufreq-test_tsc.o =20 KDIR :=3D /lib/modules/$(shell uname -r)/build KMISC :=3D /lib/modules/$(shell uname -r)/cpufrequtils/ =20 -ifeq ("$(CONFIG_X86_TSC)", "y") - obj-m +=3D cpufreq-test_tsc.o -endif =20 default: $(MAKE) -C $(KDIR) M=3D$(CURDIR) --=20 2.39.5 From nobody Sun May 24 20:33:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0502B4028CA for ; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Z+jXO3fE" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5033D1F00ADE; Fri, 22 May 2026 14:20:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779459642; bh=5LHCEytlni2fA4ULXc5o7hIbHEl7DfX9pkgOfNSW8lw=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Z+jXO3fEG9v+jK/yfPyjHtkgUE6ypGpfnHIziKuOj9b61wQQwvMBmhVKyrfurN/ao gDz4qBDNi11sn/cb9mLP+c7BrWOrSS0u5W0lOvjpl62Gei8LDunJNEqKLiwtjMDT4G /LgqrCTV64Jmo8oWeNR4IYBcrf43QKOlgCrQO/z232NKjdhWOehJg2bqTfCwSpSdWP oTdMHWIwYmRGOtFn66Ly1Uor1kYT9IVvpsY6RXqnHTiduxnChN9yiq2hROuTOjIzWj Ev2JC0g/2xduiGU66epER0QCNxBtoPFhSSAT5TlkyrkVTRifeUUrKVcyJRIxFBv9Rd S9iX5mwshsRrQ== From: Arnd Bergmann To: Ingo Molnar Cc: Arnd Bergmann , Richard Weinberger , Anton Ivanov , Johannes Berg , Thomas Gleixner , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Peter Zijlstra , Will Deacon , Boqun Feng , Gary Guo , Yury Norov , Rasmus Villemoes , Boris Ostrovsky , Alexander Usyskin , Tony Nguyen , Przemek Kitszel , x86@kernel.org, linux-kernel@vger.kernel.org, linux-um@lists.infradead.org Subject: [PATCH 4/8] x86: make CX8 usage unconditional Date: Fri, 22 May 2026 16:19:55 +0200 Message-Id: <20260522141959.1071595-5-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260522141959.1071595-1-arnd@kernel.org> References: <20260522141959.1071595-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Arnd Bergmann All supported CPUs now provide the cmpxchg8b instruction, so remove all compile-time and runtime checks for its presence and the fallback implementation, to assume it just works. Signed-off-by: Arnd Bergmann --- arch/um/include/asm/asm-prototypes.h | 4 - arch/x86/Kconfig.cpu | 4 - arch/x86/Kconfig.cpufeatures | 7 +- arch/x86/include/asm/asm-prototypes.h | 4 - arch/x86/include/asm/atomic64_32.h | 15 -- arch/x86/include/asm/cmpxchg_32.h | 76 +--------- arch/x86/include/asm/percpu.h | 14 +- arch/x86/lib/Makefile | 4 - arch/x86/lib/atomic64_386_32.S | 195 -------------------------- arch/x86/lib/cmpxchg8b_emu.S | 97 ------------- arch/x86/um/Kconfig | 2 +- arch/x86/um/Makefile | 3 +- lib/atomic64_test.c | 7 +- 13 files changed, 13 insertions(+), 419 deletions(-) delete mode 100644 arch/x86/lib/atomic64_386_32.S delete mode 100644 arch/x86/lib/cmpxchg8b_emu.S diff --git a/arch/um/include/asm/asm-prototypes.h b/arch/um/include/asm/asm= -prototypes.h index 408b31d59127..b446eec98ed8 100644 --- a/arch/um/include/asm/asm-prototypes.h +++ b/arch/um/include/asm/asm-prototypes.h @@ -1,6 +1,2 @@ #include #include - -#ifdef CONFIG_UML_X86 -extern void cmpxchg8b_emu(void); -#endif diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index fe0246477345..65d887274dd8 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -266,10 +266,6 @@ config X86_HAVE_PAE def_bool y depends on MCRUSOE || MEFFICEON || MCYRIXIII || MPENTIUM4 || MPENTIUMM ||= MPENTIUMIII || MPENTIUMII || M686 || MVIAC7 || MATOM || X86_64 =20 -config X86_CX8 - def_bool y - depends on X86_HAVE_PAE || M586TSC || M586MMX || MK6 || MK7 || MGEODEGX1 = || MGEODE_LX - # this should be set for all -march=3D.. options where the compiler # generates cmov. config X86_CMOV diff --git a/arch/x86/Kconfig.cpufeatures b/arch/x86/Kconfig.cpufeatures index 89cbf8f572ae..e0f2ff65377d 100644 --- a/arch/x86/Kconfig.cpufeatures +++ b/arch/x86/Kconfig.cpufeatures @@ -40,10 +40,6 @@ config X86_REQUIRED_FEATURE_NOPL def_bool y depends on X86_64 =20 -config X86_REQUIRED_FEATURE_CX8 - def_bool y - depends on X86_CX8 - # this should be set for all -march=3D.. options where the compiler # generates cmov. config X86_REQUIRED_FEATURE_CMOV @@ -60,6 +56,9 @@ config X86_REQUIRED_FEATURE_SYSFAST32 def_bool y depends on X86_64 && !X86_FRED =20 +config X86_REQUIRED_FEATURE_CX8 + def_bool y + config X86_REQUIRED_FEATURE_CPUID def_bool y depends on X86_64 diff --git a/arch/x86/include/asm/asm-prototypes.h b/arch/x86/include/asm/a= sm-prototypes.h index 11c6fecc3ad7..6ec680a36dea 100644 --- a/arch/x86/include/asm/asm-prototypes.h +++ b/arch/x86/include/asm/asm-prototypes.h @@ -16,10 +16,6 @@ #include #include =20 -#ifndef CONFIG_X86_CX8 -extern void cmpxchg8b_emu(void); -#endif - #ifdef CONFIG_STACKPROTECTOR extern unsigned long __ref_stack_chk_guard; #endif diff --git a/arch/x86/include/asm/atomic64_32.h b/arch/x86/include/asm/atom= ic64_32.h index ab838205c1c6..e3da5d0094c4 100644 --- a/arch/x86/include/asm/atomic64_32.h +++ b/arch/x86/include/asm/atomic64_32.h @@ -48,7 +48,6 @@ static __always_inline s64 arch_atomic64_read_nonatomic(c= onst atomic64_t *v) ATOMIC64_EXPORT(atomic64_##sym) #endif =20 -#ifdef CONFIG_X86_CX8 #define __alternative_atomic64(f, g, out, in, clobbers...) \ asm volatile("call %c[func]" \ : ALT_OUTPUT_SP(out) \ @@ -57,20 +56,6 @@ static __always_inline s64 arch_atomic64_read_nonatomic(= const atomic64_t *v) : clobbers) =20 #define ATOMIC64_DECL(sym) ATOMIC64_DECL_ONE(sym##_cx8) -#else -#define __alternative_atomic64(f, g, out, in, clobbers...) \ - alternative_call(atomic64_##f##_386, atomic64_##g##_cx8, \ - X86_FEATURE_CX8, ASM_OUTPUT(out), \ - ASM_INPUT(in), clobbers) - -#define ATOMIC64_DECL(sym) ATOMIC64_DECL_ONE(sym##_cx8); \ - ATOMIC64_DECL_ONE(sym##_386) - -ATOMIC64_DECL_ONE(add_386); -ATOMIC64_DECL_ONE(sub_386); -ATOMIC64_DECL_ONE(inc_386); -ATOMIC64_DECL_ONE(dec_386); -#endif =20 #define alternative_atomic64(f, out, in, clobbers...) \ __alternative_atomic64(f, f, ASM_OUTPUT(out), ASM_INPUT(in), clobbers) diff --git a/arch/x86/include/asm/cmpxchg_32.h b/arch/x86/include/asm/cmpxc= hg_32.h index 1f80a62be969..1019c4bce620 100644 --- a/arch/x86/include/asm/cmpxchg_32.h +++ b/arch/x86/include/asm/cmpxchg_32.h @@ -68,8 +68,6 @@ static __always_inline bool __try_cmpxchg64_local(volatil= e u64 *ptr, u64 *oldp, return __arch_try_cmpxchg64(ptr, oldp, new,); } =20 -#ifdef CONFIG_X86_CX8 - #define arch_cmpxchg64 __cmpxchg64 =20 #define arch_cmpxchg64_local __cmpxchg64_local @@ -78,78 +76,6 @@ static __always_inline bool __try_cmpxchg64_local(volati= le u64 *ptr, u64 *oldp, =20 #define arch_try_cmpxchg64_local __try_cmpxchg64_local =20 -#else - -/* - * Building a kernel capable running on 80386 and 80486. It may be necessa= ry - * to simulate the cmpxchg8b on the 80386 and 80486 CPU. - */ - -#define __arch_cmpxchg64_emu(_ptr, _old, _new, _lock_loc, _lock) \ -({ \ - union __u64_halves o =3D { .full =3D (_old), }, \ - n =3D { .full =3D (_new), }; \ - \ - asm_inline volatile( \ - ALTERNATIVE(_lock_loc \ - "call cmpxchg8b_emu", \ - _lock "cmpxchg8b %a[ptr]", X86_FEATURE_CX8) \ - : ALT_OUTPUT_SP("+a" (o.low), "+d" (o.high)) \ - : "b" (n.low), "c" (n.high), \ - [ptr] "S" (_ptr) \ - : "memory"); \ - \ - o.full; \ -}) - -static __always_inline u64 arch_cmpxchg64(volatile u64 *ptr, u64 old, u64 = new) -{ - return __arch_cmpxchg64_emu(ptr, old, new, LOCK_PREFIX_HERE, "lock "); -} -#define arch_cmpxchg64 arch_cmpxchg64 - -static __always_inline u64 arch_cmpxchg64_local(volatile u64 *ptr, u64 old= , u64 new) -{ - return __arch_cmpxchg64_emu(ptr, old, new, ,); -} -#define arch_cmpxchg64_local arch_cmpxchg64_local - -#define __arch_try_cmpxchg64_emu(_ptr, _oldp, _new, _lock_loc, _lock) \ -({ \ - union __u64_halves o =3D { .full =3D *(_oldp), }, \ - n =3D { .full =3D (_new), }; \ - bool ret; \ - \ - asm_inline volatile( \ - ALTERNATIVE(_lock_loc \ - "call cmpxchg8b_emu", \ - _lock "cmpxchg8b %a[ptr]", X86_FEATURE_CX8) \ - : ALT_OUTPUT_SP("=3D@ccz" (ret), \ - "+a" (o.low), "+d" (o.high)) \ - : "b" (n.low), "c" (n.high), \ - [ptr] "S" (_ptr) \ - : "memory"); \ - \ - if (unlikely(!ret)) \ - *(_oldp) =3D o.full; \ - \ - likely(ret); \ -}) - -static __always_inline bool arch_try_cmpxchg64(volatile u64 *ptr, u64 *old= p, u64 new) -{ - return __arch_try_cmpxchg64_emu(ptr, oldp, new, LOCK_PREFIX_HERE, "lock "= ); -} -#define arch_try_cmpxchg64 arch_try_cmpxchg64 - -static __always_inline bool arch_try_cmpxchg64_local(volatile u64 *ptr, u6= 4 *oldp, u64 new) -{ - return __arch_try_cmpxchg64_emu(ptr, oldp, new, ,); -} -#define arch_try_cmpxchg64_local arch_try_cmpxchg64_local - -#endif - -#define system_has_cmpxchg64() boot_cpu_has(X86_FEATURE_CX8) +#define system_has_cmpxchg64() true =20 #endif /* _ASM_X86_CMPXCHG_32_H */ diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h index 409981468cba..6f45358cb091 100644 --- a/arch/x86/include/asm/percpu.h +++ b/arch/x86/include/asm/percpu.h @@ -335,11 +335,9 @@ do { \ old__.var =3D _oval; \ new__.var =3D _nval; \ \ - asm_inline qual ( \ - ALTERNATIVE("call this_cpu_cmpxchg8b_emu", \ - "cmpxchg8b " __percpu_arg([var]), X86_FEATURE_CX8) \ - : ALT_OUTPUT_SP([var] "+m" (__my_cpu_var(_var)), \ - "+a" (old__.low), "+d" (old__.high)) \ + asm_inline qual ("cmpxchg8b " __percpu_arg([var]) \ + : [var] "+m" (__my_cpu_var(_var)), \ + "+a" (old__.low), "+d" (old__.high) \ : "b" (new__.low), "c" (new__.high), \ "S" (&(_var)) \ : "memory"); \ @@ -364,10 +362,8 @@ do { \ old__.var =3D *_oval; \ new__.var =3D _nval; \ \ - asm_inline qual ( \ - ALTERNATIVE("call this_cpu_cmpxchg8b_emu", \ - "cmpxchg8b " __percpu_arg([var]), X86_FEATURE_CX8) \ - : ALT_OUTPUT_SP("=3D@ccz" (success), \ + asm_inline qual ("cmpxchg8b " __percpu_arg([var]) \ + : "=3D@ccz" (success), \ [var] "+m" (__my_cpu_var(_var)), \ "+a" (old__.low), "+d" (old__.high)) \ : "b" (new__.low), "c" (new__.high), \ diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 2dba7f83ef97..210af275f468 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -48,10 +48,6 @@ ifeq ($(CONFIG_X86_32),y) lib-y +=3D strstr_32.o lib-y +=3D string_32.o lib-y +=3D memmove_32.o - lib-y +=3D cmpxchg8b_emu.o -ifneq ($(CONFIG_X86_CX8),y) - lib-y +=3D atomic64_386_32.o -endif else ifneq ($(CONFIG_GENERIC_CSUM),y) lib-y +=3D csum-partial_64.o csum-copy_64.o csum-wrappers_64.o diff --git a/arch/x86/lib/atomic64_386_32.S b/arch/x86/lib/atomic64_386_32.S deleted file mode 100644 index e768815e58ae..000000000000 --- a/arch/x86/lib/atomic64_386_32.S +++ /dev/null @@ -1,195 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * atomic64_t for 386/486 - * - * Copyright =C2=A9 2010 Luca Barbieri - */ - -#include -#include - -/* if you want SMP support, implement these with real spinlocks */ -.macro IRQ_SAVE reg - pushfl - cli -.endm - -.macro IRQ_RESTORE reg - popfl -.endm - -#define BEGIN_IRQ_SAVE(op) \ -.macro endp; \ -SYM_FUNC_END(atomic64_##op##_386); \ -.purgem endp; \ -.endm; \ -SYM_FUNC_START(atomic64_##op##_386); \ - IRQ_SAVE v; - -#define ENDP endp - -#define RET_IRQ_RESTORE \ - IRQ_RESTORE v; \ - RET - -#define v %ecx -BEGIN_IRQ_SAVE(read) - movl (v), %eax - movl 4(v), %edx - RET_IRQ_RESTORE -ENDP -#undef v - -#define v %esi -BEGIN_IRQ_SAVE(set) - movl %ebx, (v) - movl %ecx, 4(v) - RET_IRQ_RESTORE -ENDP -#undef v - -#define v %esi -BEGIN_IRQ_SAVE(xchg) - movl (v), %eax - movl 4(v), %edx - movl %ebx, (v) - movl %ecx, 4(v) - RET_IRQ_RESTORE -ENDP -#undef v - -#define v %ecx -BEGIN_IRQ_SAVE(add) - addl %eax, (v) - adcl %edx, 4(v) - RET_IRQ_RESTORE -ENDP -#undef v - -#define v %ecx -BEGIN_IRQ_SAVE(add_return) - addl (v), %eax - adcl 4(v), %edx - movl %eax, (v) - movl %edx, 4(v) - RET_IRQ_RESTORE -ENDP -#undef v - -#define v %ecx -BEGIN_IRQ_SAVE(sub) - subl %eax, (v) - sbbl %edx, 4(v) - RET_IRQ_RESTORE -ENDP -#undef v - -#define v %ecx -BEGIN_IRQ_SAVE(sub_return) - negl %edx - negl %eax - sbbl $0, %edx - addl (v), %eax - adcl 4(v), %edx - movl %eax, (v) - movl %edx, 4(v) - RET_IRQ_RESTORE -ENDP -#undef v - -#define v %esi -BEGIN_IRQ_SAVE(inc) - addl $1, (v) - adcl $0, 4(v) - RET_IRQ_RESTORE -ENDP -#undef v - -#define v %esi -BEGIN_IRQ_SAVE(inc_return) - movl (v), %eax - movl 4(v), %edx - addl $1, %eax - adcl $0, %edx - movl %eax, (v) - movl %edx, 4(v) - RET_IRQ_RESTORE -ENDP -#undef v - -#define v %esi -BEGIN_IRQ_SAVE(dec) - subl $1, (v) - sbbl $0, 4(v) - RET_IRQ_RESTORE -ENDP -#undef v - -#define v %esi -BEGIN_IRQ_SAVE(dec_return) - movl (v), %eax - movl 4(v), %edx - subl $1, %eax - sbbl $0, %edx - movl %eax, (v) - movl %edx, 4(v) - RET_IRQ_RESTORE -ENDP -#undef v - -#define v %esi -BEGIN_IRQ_SAVE(add_unless) - addl %eax, %ecx - adcl %edx, %edi - addl (v), %eax - adcl 4(v), %edx - cmpl %eax, %ecx - je 3f -1: - movl %eax, (v) - movl %edx, 4(v) - movl $1, %eax -2: - RET_IRQ_RESTORE -3: - cmpl %edx, %edi - jne 1b - xorl %eax, %eax - jmp 2b -ENDP -#undef v - -#define v %esi -BEGIN_IRQ_SAVE(inc_not_zero) - movl (v), %eax - movl 4(v), %edx - testl %eax, %eax - je 3f -1: - addl $1, %eax - adcl $0, %edx - movl %eax, (v) - movl %edx, 4(v) - movl $1, %eax -2: - RET_IRQ_RESTORE -3: - testl %edx, %edx - jne 1b - jmp 2b -ENDP -#undef v - -#define v %esi -BEGIN_IRQ_SAVE(dec_if_positive) - movl (v), %eax - movl 4(v), %edx - subl $1, %eax - sbbl $0, %edx - js 1f - movl %eax, (v) - movl %edx, 4(v) -1: - RET_IRQ_RESTORE -ENDP -#undef v diff --git a/arch/x86/lib/cmpxchg8b_emu.S b/arch/x86/lib/cmpxchg8b_emu.S deleted file mode 100644 index d4bb24347ff8..000000000000 --- a/arch/x86/lib/cmpxchg8b_emu.S +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include - -.text - -#ifndef CONFIG_X86_CX8 - -/* - * Emulate 'cmpxchg8b (%esi)' on UP - * - * Inputs: - * %esi : memory location to compare - * %eax : low 32 bits of old value - * %edx : high 32 bits of old value - * %ebx : low 32 bits of new value - * %ecx : high 32 bits of new value - */ -SYM_FUNC_START(cmpxchg8b_emu) - - pushfl - cli - - cmpl (%esi), %eax - jne .Lnot_same - cmpl 4(%esi), %edx - jne .Lnot_same - - movl %ebx, (%esi) - movl %ecx, 4(%esi) - - orl $X86_EFLAGS_ZF, (%esp) - - popfl - RET - -.Lnot_same: - movl (%esi), %eax - movl 4(%esi), %edx - - andl $(~X86_EFLAGS_ZF), (%esp) - - popfl - RET - -SYM_FUNC_END(cmpxchg8b_emu) -EXPORT_SYMBOL(cmpxchg8b_emu) - -#endif - -#ifndef CONFIG_UML - -/* - * Emulate 'cmpxchg8b %fs:(%rsi)' - * - * Inputs: - * %esi : memory location to compare - * %eax : low 32 bits of old value - * %edx : high 32 bits of old value - * %ebx : low 32 bits of new value - * %ecx : high 32 bits of new value - * - * Notably this is not LOCK prefixed and is not safe against NMIs - */ -SYM_FUNC_START(this_cpu_cmpxchg8b_emu) - - pushfl - cli - - cmpl __percpu (%esi), %eax - jne .Lnot_same2 - cmpl __percpu 4(%esi), %edx - jne .Lnot_same2 - - movl %ebx, __percpu (%esi) - movl %ecx, __percpu 4(%esi) - - orl $X86_EFLAGS_ZF, (%esp) - - popfl - RET - -.Lnot_same2: - movl __percpu (%esi), %eax - movl __percpu 4(%esi), %edx - - andl $(~X86_EFLAGS_ZF), (%esp) - - popfl - RET - -SYM_FUNC_END(this_cpu_cmpxchg8b_emu) - -#endif diff --git a/arch/x86/um/Kconfig b/arch/x86/um/Kconfig index 44b12e45f9a0..5b78440a78b9 100644 --- a/arch/x86/um/Kconfig +++ b/arch/x86/um/Kconfig @@ -13,7 +13,7 @@ config UML_X86 select ARCH_USE_QUEUED_SPINLOCKS select DCACHE_WORD_ACCESS select HAVE_EFFICIENT_UNALIGNED_ACCESS - select UML_SUBARCH_SUPPORTS_SMP if X86_CX8 + select UML_SUBARCH_SUPPORTS_SMP =20 config 64BIT bool "64-bit kernel" if "$(SUBARCH)" =3D "x86" diff --git a/arch/x86/um/Makefile b/arch/x86/um/Makefile index f9ea75bf43ac..b89936fe503a 100644 --- a/arch/x86/um/Makefile +++ b/arch/x86/um/Makefile @@ -19,8 +19,7 @@ ifeq ($(CONFIG_X86_32),y) =20 obj-y +=3D syscalls_32.o =20 -subarch-y =3D ../lib/string_32.o ../lib/atomic64_32.o ../lib/atomic64_cx8_= 32.o -subarch-y +=3D ../lib/cmpxchg8b_emu.o ../lib/atomic64_386_32.o +subarch-y =3D ../lib/string_32.o ../lib/atomic64_32.o subarch-y +=3D ../lib/checksum_32.o subarch-y +=3D ../kernel/sys_ia32.o =20 diff --git a/lib/atomic64_test.c b/lib/atomic64_test.c index d726068358c7..37af41df3e6a 100644 --- a/lib/atomic64_test.c +++ b/lib/atomic64_test.c @@ -251,15 +251,12 @@ static __init int test_atomics_init(void) test_atomic64(); =20 #ifdef CONFIG_X86 - pr_info("passed for %s platform %s CX8 and %s SSE\n", + pr_info("passed for %s platform %s SSE\n", #ifdef CONFIG_X86_64 "x86-64", -#elif defined(CONFIG_X86_CX8) - "i586+", #else - "i386+", + "i586+", #endif - boot_cpu_has(X86_FEATURE_CX8) ? "with" : "without", boot_cpu_has(X86_FEATURE_XMM) ? "with" : "without"); #else pr_info("passed\n"); --=20 2.39.5 From nobody Sun May 24 20:33:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1560A3A5424 for ; Fri, 22 May 2026 14:20:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779459656; cv=none; b=Ne0FaZ8NVlAeRJ9f6YyK6ty2xGRtCy+35Mp4DzY0st92SV75sGE9lZ98G4wxmIm/KArcap8R1utMl8wUuXll1Qq9qCRwzR8FD1+SqgxoQ/E6FfuG33l+NW5yZm25abnjJwjCb+UnJCeaCRAhYUHvnW92bprBxuW1fhD1BYa5E2E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779459656; c=relaxed/simple; bh=mzT5RPd9Bi+ScLHLOYBVEYfphlaUbtu7jYGKrC+V9EU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pInAVTkz7Qxnbjklv0M47lq32B2lXmSvKarm6BLyodW5ppkE5nEYlGBXdxCSUQenf84wyiTckl6ZAqAvi+hCFcu5DxVq/Aw3N0DXI5/cGZm6JP1Rd+1fLyjRZs7OiBLkznIzRedRfSSCwlms1ohaSpm11tsGeCCTHkNpYV2zdX4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=D35guIUP; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="D35guIUP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 15CCA1F000E9; Fri, 22 May 2026 14:20:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779459647; bh=H+T5Xm2pme6Jcpih7VPFA5EZ9bN5jCyycTaeJz2Unis=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=D35guIUPEhT4eG7ItlkowbWJs8WBZz7vxTKCtrhnchfpIR0mk9FMHqtmbWaaUouh5 MuWu3h6iHSR6nfI8VdU9fzpsi4WmmLS5trO+6K/zSXhpJFQs2rUnr9Daqnmujyr77y cndftdziCKUQv1fGV5ue0i3W6P5Pdymg/F0tJ1nZpWNxFQTGFF2am4YGYulMtPatlM d6YRlBCMnwCOqdhJFrBaxjEWO11daXzIPVCitqWClQBtPx6HkLbbvK9rD5ceI7j99D inU1LeqeqpBZgdUhAxX8GA7/u5DIGzUgKt8a9lqTcR+aBM7Cx/w+1FSpV2g8Ct4xEZ 0t4h66WZQN3ug== From: Arnd Bergmann To: Ingo Molnar Cc: Arnd Bergmann , Richard Weinberger , Anton Ivanov , Johannes Berg , Thomas Gleixner , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Peter Zijlstra , Will Deacon , Boqun Feng , Gary Guo , Yury Norov , Rasmus Villemoes , Boris Ostrovsky , Alexander Usyskin , Tony Nguyen , Przemek Kitszel , x86@kernel.org, linux-kernel@vger.kernel.org, linux-um@lists.infradead.org Subject: [PATCH 5/8] x86: remove dependencies on CONFIG_M... CPU options Date: Fri, 22 May 2026 16:19:56 +0200 Message-Id: <20260522141959.1071595-6-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260522141959.1071595-1-arnd@kernel.org> References: <20260522141959.1071595-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann CPU specific features should generally be controlled by CPU_SUP_xxx options rather than CONFIG_Mxxx, to allow generic kernels to be built that work with all of them. Replace the few options that don't follow this scheme with checks on either CPU_SUP_xxx or X86_PAE by itself. Signed-off-by: Arnd Bergmann --- arch/x86/kernel/tsc.c | 2 +- arch/x86/xen/Kconfig | 3 +-- drivers/misc/mei/Kconfig | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index e7a43471783f..3d5d38035c52 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -1213,7 +1213,7 @@ static void __init tsc_disable_clocksource_watchdog(v= oid) =20 static void __init check_system_tsc_reliable(void) { -#if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONF= IG_X86_GENERIC) +#if defined(CONFIG_CPU_SUP_CYRIX_32) if (is_geode_lx()) { /* RTSC counts during suspend */ #define RTSC_SUSP 0x100 diff --git a/arch/x86/xen/Kconfig b/arch/x86/xen/Kconfig index aa4040fd9215..7e74db652215 100644 --- a/arch/x86/xen/Kconfig +++ b/arch/x86/xen/Kconfig @@ -10,8 +10,7 @@ config XEN select X86_HV_CALLBACK_VECTOR select HIBERNATE_CALLBACKS depends on X86_64 || (X86_32 && X86_PAE) - depends on X86_64 || (X86_GENERIC || MPENTIUM4 || MATOM) - depends on X86_LOCAL_APIC && X86_TSC + depends on X86_LOCAL_APIC help This is the Linux Xen port. Enabling this will allow the kernel to boot in a paravirtualized environment under the diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig index 2d1bc5b4d11b..faa451584002 100644 --- a/drivers/misc/mei/Kconfig +++ b/drivers/misc/mei/Kconfig @@ -4,7 +4,7 @@ config INTEL_MEI tristate "Intel Management Engine Interface" depends on PCI depends on X86 || DRM_XE!=3Dn || COMPILE_TEST - default X86_64 || MATOM + default X86_64 || CPU_SUP_INTEL help The Intel Management Engine (Intel ME) provides Manageability, Security and Media services for system containing Intel chipsets. --=20 2.39.5 From nobody Sun May 24 20:33:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87AC84508E4 for ; Fri, 22 May 2026 14:20:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779459663; cv=none; b=NRRj/7xvesuP3EevL+GRm8COFObtPzxGIW/7wxnH/unEUMU96T8CKgTavwL2oGY1xof536hxR2hb9Ev8qb5We9hQKDd6pxQ/THeHZc6Cyx5FjKNJF2p8VDZpnJ14kvna/15MxQvgy67+QQ/oREoQ35/ZacR9W7tFfU5+5ALHnc4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779459663; c=relaxed/simple; bh=y2zxQ139gHQI3Vzeq3Lsl53kLU/el/9mNHeoQaJgIb8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=T/QduTGoxPz0b2QGecw92fkiwan3MKH0mFtJmsgnfey1h38MgG40Z8Nv+grEZDUfJO+y7V1JDctKW8TpD8IOUFyUPmZQiOYyfnKY9gbJQ+00rjuRo8bRt0/l+FbBBrgCR4W92noBmbpLV0msrUe2HSQZEZjrKlbZYIxDBtXWEqw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=V7oxZJv+; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="V7oxZJv+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D0FAC1F00A3D; Fri, 22 May 2026 14:20:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779459652; bh=oXIK+cBu6urjvTGhsBL+5S0tHUK0ISof8qCbA0I9wM0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=V7oxZJv+MZWhFVDAePYoRiHd0Y1Z2pxNTc0iupY1Lbc5/AT3qsmjUeCUdYSBuBC7N Jsf3dRLSoaK3hrq2tjTAmQNsX7a1K2UHPDNG/pDNdrdAGbxfYCq3DDVqXLQiZjWZfh mSiVR0ltKpAwJV1d+7VNThin5o+u+c6yvB9uD2dI+bd1xGwXhXQL9x+la6GZREgmtk 5KMvsoc+gfF+5Sa7Og/wYYtSeZVHiJIQNcsYMkw1S0sdLQV8N0ngW/p2NR2vuHy97q M2l7UT8R3JtiSvwPxa45EgNhdLrDeN9ZMoED/CVnBLrqAsv7G7xHseP8nqMr9hCX67 H7u8j4b4IBAJQ== From: Arnd Bergmann To: Ingo Molnar Cc: Arnd Bergmann , Richard Weinberger , Anton Ivanov , Johannes Berg , Thomas Gleixner , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Peter Zijlstra , Will Deacon , Boqun Feng , Gary Guo , Yury Norov , Rasmus Villemoes , Boris Ostrovsky , Alexander Usyskin , Tony Nguyen , Przemek Kitszel , x86@kernel.org, linux-kernel@vger.kernel.org, linux-um@lists.infradead.org Subject: [PATCH 6/8] x86: require minimum 64 byte cache lines Date: Fri, 22 May 2026 16:19:57 +0200 Message-Id: <20260522141959.1071595-7-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260522141959.1071595-1-arnd@kernel.org> References: <20260522141959.1071595-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann Later x86-32 CPUs like Pentium-M, K7 and Atom use 64 byte cache lines and are incompatible with kernels built for smaller values of X86_L1_CACHE_SHIFT. Pentium-4 CPUs have 128 byte cache lines but are compatible with cache operations that expect the lines to be 64 bytes. Older CPUs have smaller cache lines of 16 or 32 bytes but work correctly when X86_L1_CACHE_SHIFT is set to a larger value. Remove the per-CPU tuning and always build for 64 or 128 byte cache lines that work correctly in any CPU. Signed-off-by: Arnd Bergmann --- arch/x86/Kconfig.cpu | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 65d887274dd8..4991b633047e 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -180,8 +180,8 @@ config MVIAC7 bool "VIA C7" depends on X86_32 help - Select this for a VIA C7. Selecting this uses the correct cache - shift and tells gcc to treat the CPU as a 686. + Select this for a VIA C7. Selecting this tells gcc to treat the + CPU as a 686. =20 config MATOM bool "Intel Atom" @@ -239,9 +239,7 @@ config X86_INTERNODE_CACHE_SHIFT config X86_L1_CACHE_SHIFT int default "7" if MPENTIUM4 - default "6" if MK7 || MPENTIUMM || MATOM || MVIAC7 || X86_GENERIC || X86_= 64 - default "4" if MGEODEGX1 - default "5" if MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII ||= MPENTIUMII || M686 || M586MMX || M586TSC || MVIAC3_2 || MGEODE_LX + default "6" =20 config X86_F00F_BUG def_bool y --=20 2.39.5 From nobody Sun May 24 20:33:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 678F1425CFF for ; Fri, 22 May 2026 14:21:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779459670; cv=none; b=mGsWXC58WwSpSsItY/fz1YRUEDu1D4XsBTxhafet0Q7jn+NtPnJ5sA4N8Q0RKXNNJODW9hE3uAy0b0jnr+ykxq+bP6IXZdc4MoQgxf0XAwCA/3obn3YWDTwlgNA30B0RsxhNvEr9d4c1C8en/bVeM3bPkhQdKtc7InafZroNEG8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779459670; c=relaxed/simple; bh=9JEldwOAPPMwKKIaYyCcro0nZ/IYBi2Hw9pLvQiC6QE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BdIeGydmTAhcx9P7Ge7meoZNgA7tp9cEKaqCKCFBvIUzeZeXHpsg7VCVZaYlkAVygHaJ6RbVkaWcPl6ZqerGVDyGK9yZ9iRBBCYT5M1Nl9l0ONdi5j3MS7xz8kzWahY7OSB6QDW4b7/YZLa0pRRZiS023qBQPP6DyFMYb+d2IO0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=c6o2aRHk; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="c6o2aRHk" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 99B091F00A3E; Fri, 22 May 2026 14:20:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779459656; bh=YLeNHXfk5ri37V6bCivr64eEC8uPp0jglG/OApryq3Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=c6o2aRHkwI7WVIfoVomiuiFHkB3hrzBNyVOpEcXKPmVTSDYbGyDqI53D3L/hjdgrU CNzd9VdnD6PHcFL973GMbWd9rBJ0yJjiIMfx6s6TPAPfbtHearZW/QHkLuBIJTYMc3 oMSHN8kSzBc4YoVsdxtbXR2+PN47g+Ttu25Mawyi+8bGcvurLCB//+rvRDrZz/6jjj T1gaiUNXbBJtmyhTPDCemAUdNANRjBMjiei5dsnNXOMhHqt90qmuASTg22UgvftA82 8LUf1ZmeObBE7BjDHUe/dPyeg1pEqe7b5w8oCFkWbWmcsbyvllHq7Qj4TgZdxlWVXs 9Dp34M6v9XU5w== From: Arnd Bergmann To: Ingo Molnar Cc: Arnd Bergmann , Richard Weinberger , Anton Ivanov , Johannes Berg , Thomas Gleixner , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Peter Zijlstra , Will Deacon , Boqun Feng , Gary Guo , Yury Norov , Rasmus Villemoes , Boris Ostrovsky , Alexander Usyskin , Tony Nguyen , Przemek Kitszel , x86@kernel.org, linux-kernel@vger.kernel.org, linux-um@lists.infradead.org Subject: [PATCH 7/8] x86: remove dependencies on per-CPU options Date: Fri, 22 May 2026 16:19:58 +0200 Message-Id: <20260522141959.1071595-8-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260522141959.1071595-1-arnd@kernel.org> References: <20260522141959.1071595-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann A few CPU feature options are defined in terms of CONFIG_Mxxx CPU selection options. This conflicts with the idea of CONFIG_X86_GENERIC allowing one to build a kernel that works with multiple slightly incompatible CPUs. As a simplification, change all of these to be enabled in terms of either 586-class or 686-class builds. Signed-off-by: Arnd Bergmann --- arch/x86/Kconfig.cpu | 14 ++++---------- arch/x86/Kconfig.cpufeatures | 8 +------- arch/x86/include/asm/bitops.h | 4 ++-- arch/x86/include/asm/debugreg.h | 10 ++++------ arch/x86/include/asm/ptrace.h | 6 +----- 5 files changed, 12 insertions(+), 30 deletions(-) diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 4991b633047e..979db473a41d 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -242,8 +242,7 @@ config X86_L1_CACHE_SHIFT default "6" =20 config X86_F00F_BUG - def_bool y - depends on M586MMX || M586TSC || M586 + def_bool X86_MINIMUM_CPU_FAMILY=3D5 && CPU_SUP_INTEL =20 config X86_ALIGNMENT_16 def_bool y @@ -264,12 +263,6 @@ config X86_HAVE_PAE def_bool y depends on MCRUSOE || MEFFICEON || MCYRIXIII || MPENTIUM4 || MPENTIUMM ||= MPENTIUMIII || MPENTIUMII || M686 || MVIAC7 || MATOM || X86_64 =20 -# this should be set for all -march=3D.. options where the compiler -# generates cmov. -config X86_CMOV - def_bool y - depends on (MK7 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII ||= M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || MATOM || MGEODE_LX |= | X86_64) - config X86_MINIMUM_CPU_FAMILY int default "64" if X86_64 @@ -278,7 +271,8 @@ config X86_MINIMUM_CPU_FAMILY =20 config X86_DEBUGCTLMSR def_bool y - depends on !(MK6 || MCYRIXIII || M586MMX || M586TSC || M586) && !UML + depends on !UML + depends on X86_MINIMUM_CPU_FAMILY=3D6 =20 config IA32_FEAT_CTL def_bool y @@ -314,7 +308,7 @@ config CPU_SUP_INTEL config CPU_SUP_CYRIX_32 default y bool "Support Cyrix processors" if PROCESSOR_SELECT - depends on M586 || M586TSC || M586MMX || (EXPERT && !64BIT) + depends on X86_MINIMUM_CPU_FAMILY=3D5 help This enables detection, tunings and quirks for Cyrix processors =20 diff --git a/arch/x86/Kconfig.cpufeatures b/arch/x86/Kconfig.cpufeatures index e0f2ff65377d..a0a1e838014d 100644 --- a/arch/x86/Kconfig.cpufeatures +++ b/arch/x86/Kconfig.cpufeatures @@ -44,13 +44,7 @@ config X86_REQUIRED_FEATURE_NOPL # generates cmov. config X86_REQUIRED_FEATURE_CMOV def_bool y - depends on X86_CMOV - -# this should be set for all -march=3D options where the compiler -# generates movbe. -config X86_REQUIRED_FEATURE_MOVBE - def_bool y - depends on MATOM + depends on X86_MINIMUM_CPU_FAMILY >=3D 6 =20 config X86_REQUIRED_FEATURE_SYSFAST32 def_bool y diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h index c2ce213f2b9b..f65872f67820 100644 --- a/arch/x86/include/asm/bitops.h +++ b/arch/x86/include/asm/bitops.h @@ -312,7 +312,7 @@ static __always_inline __attribute_const__ int variable= _ffs(int x) asm("bsfl %1,%0" : "=3Dr" (r) : ASM_INPUT_RM (x), "0" (-1)); -#elif defined(CONFIG_X86_CMOV) +#elif CONFIG_X86_MINIMUM_CPU_FAMILY >=3D 6 asm("bsfl %1,%0\n\t" "cmovzl %2,%0" : "=3D&r" (r) : "rm" (x), "r" (-1)); @@ -369,7 +369,7 @@ static __always_inline __attribute_const__ int fls(unsi= gned int x) asm("bsrl %1,%0" : "=3Dr" (r) : ASM_INPUT_RM (x), "0" (-1)); -#elif defined(CONFIG_X86_CMOV) +#elif CONFIG_X86_MINIMUM_CPU_FAMILY >=3D 6 asm("bsrl %1,%0\n\t" "cmovzl %2,%0" : "=3D&r" (r) : "rm" (x), "rm" (-1)); diff --git a/arch/x86/include/asm/debugreg.h b/arch/x86/include/asm/debugre= g.h index a2c1f2d24b64..3799b2bb27bc 100644 --- a/arch/x86/include/asm/debugreg.h +++ b/arch/x86/include/asm/debugreg.h @@ -176,10 +176,9 @@ static inline unsigned long get_debugctlmsr(void) { unsigned long debugctlmsr =3D 0; =20 -#ifndef CONFIG_X86_DEBUGCTLMSR - if (boot_cpu_data.x86 < 6) + if (CONFIG_X86_MINIMUM_CPU_FAMILY < 6 || boot_cpu_data.x86 < 6) return 0; -#endif + rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctlmsr); =20 return debugctlmsr; @@ -187,10 +186,9 @@ static inline unsigned long get_debugctlmsr(void) =20 static inline void update_debugctlmsr(unsigned long debugctlmsr) { -#ifndef CONFIG_X86_DEBUGCTLMSR - if (boot_cpu_data.x86 < 6) + if (CONFIG_X86_MINIMUM_CPU_FAMILY < 6 || boot_cpu_data.x86 < 6) return; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="c2hi851n" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 54BF81F000E9; Fri, 22 May 2026 14:20:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779459661; bh=K7h54c4DvkhfQNfN7QdQhjOg4I0k8YRbNq4McvzRuIk=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=c2hi851njjoEsluyWfNsWOAgo4ryWXesbnIRp+aOMQ8h3tag+EGvBplPkdia+Scsx tGOsnfS0X/NXOAw0MyXzUkkVCC3UKJHHub1jxgMx/VfTPqXGoih9MtOUZ6xPTd0pqI h+gagBO0J1JkFpVYYOZuxOIx95jG04pbMRthSBRMxEB9aiPbajHKCIncKAG32jSpwF /v4VaQrspIjdw1crwbws2XIz69rh3qWX+RuSwHxbE3iukB0LbobEvNm5/exz3cvJ9E GTtLEYdzt+mUebwAES1W4ycjiiJIjA00X79HEFgILyofZpxM5racxSJMySAKgxlZrG 4o0gL2LVDRwVg== From: Arnd Bergmann To: Ingo Molnar Cc: Arnd Bergmann , Richard Weinberger , Anton Ivanov , Johannes Berg , Thomas Gleixner , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Peter Zijlstra , Will Deacon , Boqun Feng , Gary Guo , Yury Norov , Rasmus Villemoes , Boris Ostrovsky , Alexander Usyskin , Tony Nguyen , Przemek Kitszel , x86@kernel.org, linux-kernel@vger.kernel.org, linux-um@lists.infradead.org Subject: [PATCH 8/8] x86: simplify 32-bit instruction set selection Date: Fri, 22 May 2026 16:19:59 +0200 Message-Id: <20260522141959.1071595-9-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260522141959.1071595-1-arnd@kernel.org> References: <20260522141959.1071595-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann The -march=3D compiler flags select both instruction set and tuning for a particular CPU, which works well when building a kernel that can only run on this one type, but has some counterintuitive effects because it is not always clear which models are compatible. E.g. building for Geode LX results in a kernel that can work on all on all 686-class CPUs but crashes on CPUs without the CMOV instructions. Building a kernel for 686 could work on Geode LX and Crusoe but fails because of the CPU generation check that detects these as 585-class. Similarly, building for Intel Atom produces a 32-bit kernel that uses the MOVBE instructions and does not work on any other 32-bit CPU or even 64-bit CPUs before Haswell/Excavator. Change the CPU selection to build everything with either -march=3Di586 or -march=3Di686 and make the specific options only change the -mtune=3D parameter where this was previously handled by -march=3D. Note that the only -mtune=3D options that gcc or clang understand for x86-32 are i486, pentium, pentiumpro, pentium4, atom, geode, k6 and athlon, the other ten are just aliases for one of them. Selecting any 586-class configuration option now produces a kernel that works on every supported CPU, while selecting a 686-class configuration works on all 686-class CPUs but no 586-class ones. Consequently, the vermagic.h logic can be simplified to just these two cases. Signed-off-by: Arnd Bergmann --- arch/x86/Kconfig.cpu | 13 +++++------- arch/x86/Makefile_32.cpu | 16 +++++++-------- arch/x86/include/asm/vermagic.h | 36 ++------------------------------- 3 files changed, 15 insertions(+), 50 deletions(-) diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 979db473a41d..ebbf44e3cfc6 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -6,9 +6,9 @@ choice default M686 help This is the processor type of your CPU. This information is - used for optimizing purposes. In order to compile a kernel - that can run on all supported x86 CPU types (albeit not - optimally fast), you can specify "586" here. + used to pick between i586-class and i686-class processors, + as well as to optimize for a particular microarchitecture + within the two classes. =20 Note that the 386 and 486 is no longer supported, this includes AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI 486DLC/DLC2, @@ -164,16 +164,13 @@ config MCYRIXIII treat this chip as a generic 586. Whilst the CPU is 686 class, it lacks the cmov extension which gcc assumes is present when generating 686 code. - Note that Nehemiah (Model 9) and above will not boot with this - kernel due to them lacking the 3DNow! instructions used in earlier - incarnations of the CPU. =20 config MVIAC3_2 bool "VIA C3-2 (Nehemiah)" depends on X86_32 help - Select this for a VIA C3 "Nehemiah". Selecting this enables usage - of SSE and tells gcc to treat the CPU as a 686. + Select this for a VIA C3 "Nehemiah". Selecting tells gcc to treat + the CPU as a 686. Note, this kernel will not boot on older (pre model 9) C3s. =20 config MVIAC7 diff --git a/arch/x86/Makefile_32.cpu b/arch/x86/Makefile_32.cpu index c5aa169b596d..1735a5f95d33 100644 --- a/arch/x86/Makefile_32.cpu +++ b/arch/x86/Makefile_32.cpu @@ -11,26 +11,26 @@ align :=3D -falign-functions=3D0 -falign-jumps=3D0 -fa= lign-loops=3D0 endif =20 cflags-$(CONFIG_M586TSC) +=3D -march=3Di586 -cflags-$(CONFIG_M586MMX) +=3D -march=3Dpentium-mmx +cflags-$(CONFIG_M586MMX) +=3D -march=3Di586 cflags-$(CONFIG_M686) +=3D -march=3Di686 cflags-$(CONFIG_MPENTIUMII) +=3D -march=3Di686 $(call tune,pentium2) cflags-$(CONFIG_MPENTIUMIII) +=3D -march=3Di686 $(call tune,pentium3) cflags-$(CONFIG_MPENTIUMM) +=3D -march=3Di686 $(call tune,pentium3) cflags-$(CONFIG_MPENTIUM4) +=3D -march=3Di686 $(call tune,pentium4) -cflags-$(CONFIG_MK6) +=3D -march=3Dk6 +cflags-$(CONFIG_MK6) +=3D -march=3Di586 $(call tune,k6) # Please note, that patches that add -march=3Dathlon-xp and friends are po= intless. # They make zero difference whatsosever to performance at this time. -cflags-$(CONFIG_MK7) +=3D -march=3Dathlon +cflags-$(CONFIG_MK7) +=3D -march=3Di686 $(call tune,athlon) cflags-$(CONFIG_MCRUSOE) +=3D -march=3Di686 $(align) cflags-$(CONFIG_MEFFICEON) +=3D -march=3Di686 $(call tune,pentium3) $(alig= n) -cflags-$(CONFIG_MCYRIXIII) +=3D $(call cc-option,-march=3Dc3,-march=3Di486= ) $(align) -cflags-$(CONFIG_MVIAC3_2) +=3D $(call cc-option,-march=3Dc3-2,-march=3Di68= 6) +cflags-$(CONFIG_MCYRIXIII) +=3D -march=3Di586 $(call tune,i486) $(align) +cflags-$(CONFIG_MVIAC3_2) +=3D -march=3Di686 cflags-$(CONFIG_MVIAC7) +=3D -march=3Di686 -cflags-$(CONFIG_MATOM) +=3D -march=3Datom +cflags-$(CONFIG_MATOM) +=3D -march=3Di686 $(call tune,atom) =20 # Geode GX1 support -cflags-$(CONFIG_MGEODEGX1) +=3D -march=3Dpentium-mmx -cflags-$(CONFIG_MGEODE_LX) +=3D $(call cc-option,-march=3Dgeode,-march=3Dp= entium-mmx) +cflags-$(CONFIG_MGEODEGX1) +=3D -march=3Di586 $(call tune,geode) +cflags-$(CONFIG_MGEODE_LX) +=3D -march=3Di586 $(call tune,geode) # add at the end to overwrite eventual tuning options from earlier # cpu entries cflags-$(CONFIG_X86_GENERIC) +=3D $(call tune,generic,$(call tune,i686)) diff --git a/arch/x86/include/asm/vermagic.h b/arch/x86/include/asm/vermagi= c.h index e26061df0c9b..5323ed585bc9 100644 --- a/arch/x86/include/asm/vermagic.h +++ b/arch/x86/include/asm/vermagic.h @@ -5,42 +5,10 @@ =20 #ifdef CONFIG_X86_64 /* X86_64 does not define MODULE_PROC_FAMILY */ -#elif defined CONFIG_M586TSC -#define MODULE_PROC_FAMILY "586TSC " -#elif defined CONFIG_M586MMX -#define MODULE_PROC_FAMILY "586MMX " -#elif defined CONFIG_MATOM -#define MODULE_PROC_FAMILY "ATOM " -#elif defined CONFIG_M686 +#elif CONFIG_X86_MINIMUM_CPU_FAMILY =3D=3D 6 #define MODULE_PROC_FAMILY "686 " -#elif defined CONFIG_MPENTIUMII -#define MODULE_PROC_FAMILY "PENTIUMII " -#elif defined CONFIG_MPENTIUMIII -#define MODULE_PROC_FAMILY "PENTIUMIII " -#elif defined CONFIG_MPENTIUMM -#define MODULE_PROC_FAMILY "PENTIUMM " -#elif defined CONFIG_MPENTIUM4 -#define MODULE_PROC_FAMILY "PENTIUM4 " -#elif defined CONFIG_MK6 -#define MODULE_PROC_FAMILY "K6 " -#elif defined CONFIG_MK7 -#define MODULE_PROC_FAMILY "K7 " -#elif defined CONFIG_MCRUSOE -#define MODULE_PROC_FAMILY "CRUSOE " -#elif defined CONFIG_MEFFICEON -#define MODULE_PROC_FAMILY "EFFICEON " -#elif defined CONFIG_MCYRIXIII -#define MODULE_PROC_FAMILY "CYRIXIII " -#elif defined CONFIG_MVIAC3_2 -#define MODULE_PROC_FAMILY "VIAC3-2 " -#elif defined CONFIG_MVIAC7 -#define MODULE_PROC_FAMILY "VIAC7 " -#elif defined CONFIG_MGEODEGX1 -#define MODULE_PROC_FAMILY "GEODEGX1 " -#elif defined CONFIG_MGEODE_LX -#define MODULE_PROC_FAMILY "GEODE " #else -#error unknown processor family +#define MODULE_PROC_FAMILY "586 " #endif =20 #ifdef CONFIG_X86_32 --=20 2.39.5