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[95.98.212.71]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-43b6351a772sm1915628fac.3.2026.05.22.07.11.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 May 2026 07:11:55 -0700 (PDT) From: Stanislav Zaikin To: andersson@kernel.org, linusw@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Stanislav Zaikin Subject: [PATCH] pinctrl: qcom: sm6115: Add egpio support Date: Fri, 22 May 2026 16:11:48 +0200 Message-ID: <20260522141149.1425711-1-zstaseg@gmail.com> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This mirrors the egpio support added to sc7280/sm8450/sm8250/etc. This chan= ge is necessary for GPIOs 98-112 (15 GPIOs) to be used as normal GPIOs. Signed-off-by: Stanislav Zaikin --- drivers/pinctrl/qcom/pinctrl-sm6115.c | 40 +++++++++++++++++---------- 1 file changed, 25 insertions(+), 15 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115.c b/drivers/pinctrl/qcom/p= inctrl-sm6115.c index 234451fbf47b..97930db91476 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6115.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6115.c @@ -47,6 +47,8 @@ enum { .mux_bit =3D 2, \ .pull_bit =3D 0, \ .drv_bit =3D 6, \ + .egpio_enable =3D 12, \ + .egpio_present =3D 11, \ .oe_bit =3D 9, \ .in_bit =3D 0, \ .out_bit =3D 1, \ @@ -374,6 +376,7 @@ enum sm6115_functions { msm_mux_ddr_pxi1, msm_mux_ddr_pxi2, msm_mux_ddr_pxi3, + msm_mux_egpio, msm_mux_gcc_gp1, msm_mux_gcc_gp2, msm_mux_gcc_gp3, @@ -451,6 +454,11 @@ static const char * const gpio_groups[] =3D { "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", }; +static const char * const egpio_groups[] =3D { + "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", + "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", + "gpio110", "gpio111", "gpio112", +}; static const char * const ddr_bist_groups[] =3D { "gpio0", "gpio1", "gpio2", "gpio3", }; @@ -681,6 +689,7 @@ static const struct pinfunction sm6115_functions[] =3D { MSM_PIN_FUNCTION(ddr_pxi1), MSM_PIN_FUNCTION(ddr_pxi2), MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(egpio), MSM_PIN_FUNCTION(gcc_gp1), MSM_PIN_FUNCTION(gcc_gp2), MSM_PIN_FUNCTION(gcc_gp3), @@ -839,21 +848,21 @@ static const struct msm_pingroup sm6115_groups[] =3D { [95] =3D PINGROUP(95, WEST, nav_gpio, gp_pdm0, qdss_gpio, wlan1_adc1, _, = _, _, _, _), [96] =3D PINGROUP(96, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm1, sd_write,= jitter_bist, qdss_cti, qdss_cti, _), [97] =3D PINGROUP(97, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm2, jitter_bi= st, qdss_cti, qdss_cti, _, _), - [98] =3D PINGROUP(98, SOUTH, _, _, _, _, _, _, _, _, _), - [99] =3D PINGROUP(99, SOUTH, _, _, _, _, _, _, _, _, _), - [100] =3D PINGROUP(100, SOUTH, atest, _, _, _, _, _, _, _, _), - [101] =3D PINGROUP(101, SOUTH, atest, _, _, _, _, _, _, _, _), - [102] =3D PINGROUP(102, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, = _, _, _), - [103] =3D PINGROUP(103, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, = _, _, _), - [104] =3D PINGROUP(104, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_p= xi3, _, _, _, _), - [105] =3D PINGROUP(105, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_p= xi3, _, _, _, _), - [106] =3D PINGROUP(106, SOUTH, nav_gpio, gcc_gp3, qdss_gpio, _, _, _, _, = _, _), - [107] =3D PINGROUP(107, SOUTH, nav_gpio, gcc_gp2, qdss_gpio, _, _, _, _, = _, _), - [108] =3D PINGROUP(108, SOUTH, nav_gpio, _, _, _, _, _, _, _, _), - [109] =3D PINGROUP(109, SOUTH, _, qdss_gpio, _, _, _, _, _, _, _), - [110] =3D PINGROUP(110, SOUTH, _, qdss_gpio, _, _, _, _, _, _, _), - [111] =3D PINGROUP(111, SOUTH, _, _, _, _, _, _, _, _, _), - [112] =3D PINGROUP(112, SOUTH, _, _, _, _, _, _, _, _, _), + [98] =3D PINGROUP(98, SOUTH, _, _, _, _, _, _, _, _, egpio), + [99] =3D PINGROUP(99, SOUTH, _, _, _, _, _, _, _, _, egpio), + [100] =3D PINGROUP(100, SOUTH, atest, _, _, _, _, _, _, _, egpio), + [101] =3D PINGROUP(101, SOUTH, atest, _, _, _, _, _, _, _, egpio), + [102] =3D PINGROUP(102, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, = _, _, egpio), + [103] =3D PINGROUP(103, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, = _, _, egpio), + [104] =3D PINGROUP(104, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_p= xi3, _, _, _, egpio), + [105] =3D PINGROUP(105, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_p= xi3, _, _, _, egpio), + [106] =3D PINGROUP(106, SOUTH, nav_gpio, gcc_gp3, qdss_gpio, _, _, _, _, = _, egpio), + [107] =3D PINGROUP(107, SOUTH, nav_gpio, gcc_gp2, qdss_gpio, _, _, _, _, = _, egpio), + [108] =3D PINGROUP(108, SOUTH, nav_gpio, _, _, _, _, _, _, _, egpio), + [109] =3D PINGROUP(109, SOUTH, _, qdss_gpio, _, _, _, _, _, _, egpio), + [110] =3D PINGROUP(110, SOUTH, _, qdss_gpio, _, _, _, _, _, _, egpio), + [111] =3D PINGROUP(111, SOUTH, _, _, _, _, _, _, _, _, egpio), + [112] =3D PINGROUP(112, SOUTH, _, _, _, _, _, _, _, _, egpio), [113] =3D UFS_RESET(ufs_reset, 0x78000), [114] =3D SDC_QDSD_PINGROUP(sdc1_rclk, WEST, 0x75000, 15, 0), [115] =3D SDC_QDSD_PINGROUP(sdc1_clk, WEST, 0x75000, 13, 6), @@ -886,6 +895,7 @@ static const struct msm_pinctrl_soc_data sm6115_tlmm = =3D { .ntiles =3D ARRAY_SIZE(sm6115_tiles), .wakeirq_map =3D sm6115_mpm_map, .nwakeirq_map =3D ARRAY_SIZE(sm6115_mpm_map), + .egpio_func =3D 9, }; =20 static int sm6115_tlmm_probe(struct platform_device *pdev) --=20 2.51.0