From nobody Sun May 24 19:33:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9BEFC3ED5DC; Fri, 22 May 2026 12:00:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779451219; cv=none; b=U/F6BD1mP82rbyNa/w7x0Ku9avqh7TIlNEYyGVzyp+LagLGM3dxoaa2iiBexRI9Fw0Vbpawz1X/+H4HnlWGLGkxzgjEZrmFp8Uibj/6N8Q2g2VCj5wleNlIpQ7zpC6r9PI4jOGB+05RECrmPxsImmvEJskImpD3ZAZy8bWUVAU0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779451219; c=relaxed/simple; bh=NINJHrxZj1TGFwUlDmNhfnSQqJUMY37ppvIY0J2E8TY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GHunpOrFvAVEGIB6KGaXGePW81/lydk9O9h4wqrD+bijsr8RDXNLbgXeJ4/N+qWEgcvkwIC60Ho5Q6VYWqmu2MdfQYr8erVV3vADjhEUFtyXXL1YNHMsMPdIf0guhRDlO+WUFWMusRj3SwAg1Mii49wJ4j5nWZxiQOofS9QfZkE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=i941u6qf; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="i941u6qf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 566F11F00A3E; Fri, 22 May 2026 12:00:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779451218; bh=weMzmC97VT4eQPxanRtNqU9HBpxL1rHmi3VZXI/I3bw=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=i941u6qfviRWyVXQAllvCmvnWIJDTwvaujpPY+Q6fo6Y4vtvxvTsUH77pUy18rdzk sM9A+7VLjWnIRm3Ai8hazDjjIpXa9FhbqPSy48+zsKTBFIh72x3SgZb86LUX6UpcyY LHvt7y7VfbQa4tULUdPQZeIFuOc2rX4GCiUC5i+/c/0ZKa4IjLPcdcVi6TtTv5p7eC Ic/N5LtBQqBcJFiApU5URcak+rhoGRxFIrLgJ13q4wxSBThwCdoILG1RB1xQ3N0cns sMd+wJXZaxKk2miQfns41VUxdEpKdPijDtx3uIwC4w2ARyQL9Pvuv9iVdqDPL/24zj Bz1I6FGXfVOsQ== From: Sumit Garg To: andersson@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg Subject: [PATCH v7 01/15] arm64: dts: qcom: kodiak: Add EL2 overlay Date: Fri, 22 May 2026 17:29:22 +0530 Message-ID: <20260522115936.201208-2-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260522115936.201208-1-sumit.garg@kernel.org> References: <20260522115936.201208-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mukesh Ojha All the existing variants Kodiak boards are using Gunyah hypervisor which means that, so far, Linux-based OS could only boot in EL1 on those devices. However, it is possible for us to boot Linux at EL2 on these devices [1]. When running under Gunyah, the remote processor firmware IOMMU streams are controlled by Gunyah. However, without Gunyah, the IOMMU is managed by the consumer of this DeviceTree. Therefore, describe the firmware streams for each remote processor. Add a EL2-specific DT overlay and apply it to Kodiak IOT variant devices to create -el2.dtb for each of them alongside "normal" dtb. Note that modem and media subsystems haven't been supported yet due to missing dependencies. For GPU to work, zap shader is disabled and in EL2 mode the kernel owns hardware watchdog which is enabled here. [1] https://docs.qualcomm.com/bundle/publicresource/topics/80-70020-4/boot-deve= loper-touchpoints.html#uefi Signed-off-by: Mukesh Ojha [SG: watchdog and modem fixup] Signed-off-by: Sumit Garg --- arch/arm64/boot/dts/qcom/Makefile | 2 ++ arch/arm64/boot/dts/qcom/kodiak-el2.dtso | 39 ++++++++++++++++++++++++ 2 files changed, 41 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/kodiak-el2.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 795cee4757ab..d10490590e4c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -176,6 +176,8 @@ qcs615-ride-el2-dtbs :=3D qcs615-ride.dtb talos-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D qcs615-ride-el2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs6490-radxa-dragon-q6a.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs6490-rb3gen2.dtb +qcs6490-rb3gen2-el2-dtbs :=3D qcs6490-rb3gen2.dtb kodiak-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) +=3D qcs6490-rb3gen2-el2.dtb =20 qcs6490-rb3gen2-vision-mezzanine-dtbs :=3D qcs6490-rb3gen2.dtb qcs6490-rb3= gen2-vision-mezzanine.dtbo qcs6490-rb3gen2-industrial-mezzanine-dtbs :=3D qcs6490-rb3gen2.dtb qcs6490= -rb3gen2-industrial-mezzanine.dtbo diff --git a/arch/arm64/boot/dts/qcom/kodiak-el2.dtso b/arch/arm64/boot/dts= /qcom/kodiak-el2.dtso new file mode 100644 index 000000000000..520ed582370d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/kodiak-el2.dtso @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * Kodiak specific modifications required to boot in EL2. + */ + + +/dts-v1/; +/plugin/; + +&gpu_zap_shader { + status =3D "disabled"; +}; + +&remoteproc_adsp { + iommus =3D <&apps_smmu 0x1800 0x0>; +}; + +&remoteproc_cdsp { + iommus =3D <&apps_smmu 0x11a0 0x0400>; +}; + +&remoteproc_mpss { + status =3D "disabled"; +}; + +&remoteproc_wpss { + iommus =3D <&apps_smmu 0x1c03 0x1>, + <&apps_smmu 0x1c83 0x1>; +}; + +&venus { + status =3D "disabled"; +}; + +&watchdog { + status =3D "okay"; +}; --=20 2.51.0 From nobody Sun May 24 19:33:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACEB7313273; Fri, 22 May 2026 12:00:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779451237; cv=none; b=oO+vKf3+l4WmHH/+Olw9DvATuKVgptyS2kzqCm0L3vjBXVP7GWYytDFvhzGy28+Hog3VB/45aNPu9lcLT24S1h6uDamA/qVyE5Vck77Wf6lZU1Emuqu1EVAOBgY0eG2N4beEqPf4914LGZY5dWtHcPf8n4CvI+FnnXjCyJUMOTY= ARC-Message-Signature: i=1; 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b=RQzZQw9XFWi1K5rFpw1GkPMAqx5EPh3/XIMJ6/t84tTuOzepfMr7Ai1DCGJ/p/ETH b08/0W5KlRfkhDegTkabcfEJ7p3Kb6Mw4ftdVBY0aoLuZlGM9n3IrZz1scjJxZlPE3 m0jvENdV8tcZQI0g/oF70cr8nDidGRJ7fKbMrcV32bj2WdKXfNG2thUE5eoPYCAxix D6dvjmaHfPKAt4Pql7qxfef7KPJJKEcWL6Aw46KxSCWFvzLqkiNTDXOXDSMycRfPEt 8q11sUHzLHjNwcKtTci4HYOaB7Ehx4PwOfuInrQ8Fhcij+4814neWimwgNPijnPfGl dT1UGm3X1+DEA== From: Sumit Garg To: andersson@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg , Harshal Dev Subject: [PATCH v7 02/15] firmware: qcom: Add a generic PAS service Date: Fri, 22 May 2026 17:29:23 +0530 Message-ID: <20260522115936.201208-3-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260522115936.201208-1-sumit.garg@kernel.org> References: <20260522115936.201208-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg Qcom platforms has the legacy of using non-standard SCM calls splintered over the various kernel drivers. These SCM calls aren't compliant with the standard SMC calling conventions which is a prerequisite to enable migration to the FF-A specifications from Arm. OP-TEE as an alternative trusted OS to Qualcomm TEE (QTEE) can't support these non-standard SCM calls. And even for newer architectures using S-EL2 with Hafnium support, QTEE won't be able to support SCM calls either with FF-A requirements coming in. And with both OP-TEE and QTEE drivers well integrated in the TEE subsystem, it makes further sense to reuse the TEE bus client drivers infrastructure. The added benefit of TEE bus infrastructure is that there is support for discoverable/enumerable services. With that client drivers don't have to manually invoke a special SCM call to know the service status. So enable the generic Peripheral Authentication Service (PAS) provided by the firmware. It acts as the common layer with different TZ backends plugged in whether it's an SCM implementation or a proper TEE bus based PAS service implementation. Reviewed-by: Mukesh Ojha Tested-by: Mukesh Ojha # Lemans Reviewed-by: Harshal Dev Tested-by: Vignesh Viswanathan # IPQ= 9650 Signed-off-by: Sumit Garg --- drivers/firmware/qcom/Kconfig | 8 + drivers/firmware/qcom/Makefile | 1 + drivers/firmware/qcom/qcom_pas.c | 291 +++++++++++++++++++++++++ drivers/firmware/qcom/qcom_pas.h | 50 +++++ include/linux/firmware/qcom/qcom_pas.h | 43 ++++ 5 files changed, 393 insertions(+) create mode 100644 drivers/firmware/qcom/qcom_pas.c create mode 100644 drivers/firmware/qcom/qcom_pas.h create mode 100644 include/linux/firmware/qcom/qcom_pas.h diff --git a/drivers/firmware/qcom/Kconfig b/drivers/firmware/qcom/Kconfig index b477d54b495a..9f66cc774508 100644 --- a/drivers/firmware/qcom/Kconfig +++ b/drivers/firmware/qcom/Kconfig @@ -6,6 +6,14 @@ =20 menu "Qualcomm firmware drivers" =20 +config QCOM_PAS + tristate "Qualcomm generic PAS interface driver" + help + Enable the generic Peripheral Authentication Service (PAS) provided + by the firmware. It acts as the common layer with different TZ + backends plugged in whether it's an SCM implementation or a proper + TEE bus based PAS service implementation. + config QCOM_SCM select QCOM_TZMEM tristate diff --git a/drivers/firmware/qcom/Makefile b/drivers/firmware/qcom/Makefile index 0be40a1abc13..dc5ab45f906a 100644 --- a/drivers/firmware/qcom/Makefile +++ b/drivers/firmware/qcom/Makefile @@ -8,3 +8,4 @@ qcom-scm-objs +=3D qcom_scm.o qcom_scm-smc.o qcom_scm-legac= y.o obj-$(CONFIG_QCOM_TZMEM) +=3D qcom_tzmem.o obj-$(CONFIG_QCOM_QSEECOM) +=3D qcom_qseecom.o obj-$(CONFIG_QCOM_QSEECOM_UEFISECAPP) +=3D qcom_qseecom_uefisecapp.o +obj-$(CONFIG_QCOM_PAS) +=3D qcom_pas.o diff --git a/drivers/firmware/qcom/qcom_pas.c b/drivers/firmware/qcom/qcom_= pas.c new file mode 100644 index 000000000000..bc6c42f2b3c6 --- /dev/null +++ b/drivers/firmware/qcom/qcom_pas.c @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2010,2015,2019 The Linux Foundation. All rights reserved. + * Copyright (C) 2015 Linaro Ltd. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +#include "qcom_pas.h" + +static struct qcom_pas_ops *ops_ptr; + +/** + * devm_qcom_pas_context_alloc() - Allocate peripheral authentication serv= ice + * context for a given peripheral + * + * PAS context is device-resource managed, so the caller does not need + * to worry about freeing the context memory. + * + * @dev: PAS firmware device + * @pas_id: peripheral authentication service id + * @mem_phys: Subsystem reserve memory start address + * @mem_size: Subsystem reserve memory size + * + * Return: The new PAS context, or ERR_PTR() on failure. + */ +struct qcom_pas_context *devm_qcom_pas_context_alloc(struct device *dev, + u32 pas_id, + phys_addr_t mem_phys, + size_t mem_size) +{ + struct qcom_pas_context *ctx; + + ctx =3D devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return ERR_PTR(-ENOMEM); + + ctx->dev =3D dev; + ctx->pas_id =3D pas_id; + ctx->mem_phys =3D mem_phys; + ctx->mem_size =3D mem_size; + + return ctx; +} +EXPORT_SYMBOL_GPL(devm_qcom_pas_context_alloc); + +/** + * qcom_pas_init_image() - Initialize peripheral authentication service st= ate + * machine for a given peripheral, using the metadata + * @pas_id: peripheral authentication service id + * @metadata: pointer to memory containing ELF header, program header table + * and optional blob of data used for authenticating the metadata + * and the rest of the firmware + * @size: size of the metadata + * @ctx: optional pas context + * + * Return: 0 on success. + * + * Upon successful return, the PAS metadata context (@ctx) will be used to + * track the metadata allocation, this needs to be released by invoking + * qcom_pas_metadata_release() by the caller. + */ +int qcom_pas_init_image(u32 pas_id, const void *metadata, size_t size, + struct qcom_pas_context *ctx) +{ + if (!ops_ptr) + return -ENODEV; + + return ops_ptr->init_image(ops_ptr->dev, pas_id, metadata, size, ctx); +} +EXPORT_SYMBOL_GPL(qcom_pas_init_image); + +/** + * qcom_pas_metadata_release() - release metadata context + * @ctx: pas context + */ +void qcom_pas_metadata_release(struct qcom_pas_context *ctx) +{ + if (!ops_ptr || !ctx || !ctx->ptr) + return; + + ops_ptr->metadata_release(ops_ptr->dev, ctx); +} +EXPORT_SYMBOL_GPL(qcom_pas_metadata_release); + +/** + * qcom_pas_mem_setup() - Prepare the memory related to a given peripheral + * for firmware loading + * @pas_id: peripheral authentication service id + * @addr: start address of memory area to prepare + * @size: size of the memory area to prepare + * + * Return: 0 on success. + */ +int qcom_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size) +{ + if (!ops_ptr) + return -ENODEV; + + return ops_ptr->mem_setup(ops_ptr->dev, pas_id, addr, size); +} +EXPORT_SYMBOL_GPL(qcom_pas_mem_setup); + +/** + * qcom_pas_get_rsc_table() - Retrieve the resource table in passed output= buffer + * for a given peripheral. + * + * Qualcomm remote processor may rely on both static and dynamic resources= for + * its functionality. Static resources typically refer to memory-mapped + * addresses required by the subsystem and are often embedded within the + * firmware binary and dynamic resources, such as shared memory in DDR etc= ., + * are determined at runtime during the boot process. + * + * On Qualcomm Technologies devices, it's possible that static resources a= re + * not embedded in the firmware binary and instead are provided by TrustZo= ne. + * However, dynamic resources are always expected to come from TrustZone. = This + * indicates that for Qualcomm devices, all resources (static and dynamic)= will + * be provided by TrustZone PAS service. + * + * If the remote processor firmware binary does contain static resources, = they + * should be passed in input_rt. These will be forwarded to TrustZone for + * authentication. TrustZone will then append the dynamic resources and re= turn + * the complete resource table in output_rt_tzm. + * + * If the remote processor firmware binary does not include a resource tab= le, + * the caller of this function should set input_rt as NULL and input_rt_si= ze + * as zero respectively. + * + * More about documentation on resource table data structures can be found= in + * include/linux/remoteproc.h + * + * @ctx: PAS context + * @pas_id: peripheral authentication service id + * @input_rt: resource table buffer which is present in firmware bin= ary + * @input_rt_size: size of the resource table present in firmware binary + * @output_rt_size: TrustZone expects caller should pass worst case size f= or + * the output_rt_tzm. + * + * Return: + * On success, returns a pointer to the allocated buffer containing the f= inal + * resource table and output_rt_size will have actual resource table size= from + * TrustZone. The caller is responsible for freeing the buffer. On failur= e, + * returns ERR_PTR(-errno). + */ +struct resource_table *qcom_pas_get_rsc_table(struct qcom_pas_context *ctx, + void *input_rt, + size_t input_rt_size, + size_t *output_rt_size) +{ + if (!ops_ptr) + return ERR_PTR(-ENODEV); + if (!ctx) + return ERR_PTR(-EINVAL); + + return ops_ptr->get_rsc_table(ops_ptr->dev, ctx, input_rt, + input_rt_size, output_rt_size); +} +EXPORT_SYMBOL_GPL(qcom_pas_get_rsc_table); + +/** + * qcom_pas_auth_and_reset() - Authenticate the given peripheral firmware + * and reset the remote processor + * @pas_id: peripheral authentication service id + * + * Return: 0 on success. + */ +int qcom_pas_auth_and_reset(u32 pas_id) +{ + if (!ops_ptr) + return -ENODEV; + + return ops_ptr->auth_and_reset(ops_ptr->dev, pas_id); +} +EXPORT_SYMBOL_GPL(qcom_pas_auth_and_reset); + +/** + * qcom_pas_prepare_and_auth_reset() - Prepare, authenticate, and reset the + * remote processor + * + * @ctx: Context saved during call to devm_qcom_pas_context_alloc() + * + * This function performs the necessary steps to prepare a PAS subsystem, + * authenticate it using the provided metadata, and initiate a reset seque= nce. + * + * It should be used when Linux is in control setting up the IOMMU hardware + * for remote subsystem during secure firmware loading processes. The + * preparation step sets up a shmbridge over the firmware memory before + * TrustZone accesses the firmware memory region for authentication. The + * authentication step verifies the integrity and authenticity of the firm= ware + * or configuration using secure metadata. Finally, the reset step ensures= the + * subsystem starts in a clean and sane state. + * + * Return: 0 on success, negative errno on failure. + */ +int qcom_pas_prepare_and_auth_reset(struct qcom_pas_context *ctx) +{ + if (!ops_ptr) + return -ENODEV; + if (!ctx) + return -EINVAL; + + return ops_ptr->prepare_and_auth_reset(ops_ptr->dev, ctx); +} +EXPORT_SYMBOL_GPL(qcom_pas_prepare_and_auth_reset); + +/** + * qcom_pas_set_remote_state() - Set the remote processor state + * @state: peripheral state + * @pas_id: peripheral authentication service id + * + * Return: 0 on success. + */ +int qcom_pas_set_remote_state(u32 state, u32 pas_id) +{ + if (!ops_ptr) + return -ENODEV; + + return ops_ptr->set_remote_state(ops_ptr->dev, state, pas_id); +} +EXPORT_SYMBOL_GPL(qcom_pas_set_remote_state); + +/** + * qcom_pas_shutdown() - Shut down the remote processor + * @pas_id: peripheral authentication service id + * + * Return: 0 on success. + */ +int qcom_pas_shutdown(u32 pas_id) +{ + if (!ops_ptr) + return -ENODEV; + + return ops_ptr->shutdown(ops_ptr->dev, pas_id); +} +EXPORT_SYMBOL_GPL(qcom_pas_shutdown); + +/** + * qcom_pas_supported() - Check if the peripheral authentication service is + * available for the given peripheral + * @pas_id: peripheral authentication service id + * + * Return: true if PAS is supported for this peripheral, otherwise false. + */ +bool qcom_pas_supported(u32 pas_id) +{ + if (!ops_ptr) + return false; + + return ops_ptr->supported(ops_ptr->dev, pas_id); +} +EXPORT_SYMBOL_GPL(qcom_pas_supported); + +bool qcom_pas_is_available(void) +{ + /* + * The barrier for ops_ptr is intended to synchronize the data stores + * for the ops data structure when client drivers are in parallel + * checking for PAS service availability. + * + * Once the PAS backend becomes available, it is allowed for multiple + * threads to enter TZ for parallel bringup of co-processors during + * boot. + */ + return !!smp_load_acquire(&ops_ptr); +} +EXPORT_SYMBOL_GPL(qcom_pas_is_available); + +void qcom_pas_ops_register(struct qcom_pas_ops *ops) +{ + if (!qcom_pas_is_available()) + /* Paired with smp_load_acquire() in qcom_pas_is_available() */ + smp_store_release(&ops_ptr, ops); + else + pr_err("qcom_pas: ops already registered by %s\n", + ops_ptr->drv_name); +} +EXPORT_SYMBOL_GPL(qcom_pas_ops_register); + +void qcom_pas_ops_unregister(void) +{ + /* Paired with smp_load_acquire() in qcom_pas_is_available() */ + smp_store_release(&ops_ptr, NULL); +} +EXPORT_SYMBOL_GPL(qcom_pas_ops_unregister); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Qualcomm generic TZ PAS driver"); diff --git a/drivers/firmware/qcom/qcom_pas.h b/drivers/firmware/qcom/qcom_= pas.h new file mode 100644 index 000000000000..8643e2760602 --- /dev/null +++ b/drivers/firmware/qcom/qcom_pas.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __QCOM_PAS_INT_H +#define __QCOM_PAS_INT_H + +struct device; + +/** + * struct qcom_pas_ops - Qcom Peripheral Authentication Service (PAS) ops + * @drv_name: PAS driver name. + * @dev: PAS device pointer. + * @supported: Peripheral supported callback. + * @init_image: Peripheral image initialization callback. + * @mem_setup: Peripheral memory setup callback. + * @get_rsc_table: Peripheral get resource table callback. + * @prepare_and_auth_reset: Peripheral prepare firmware authentication and + * reset callback. + * @auth_and_reset: Peripheral firmware authentication and reset + * callback. + * @set_remote_state: Peripheral set remote state callback. + * @shutdown: Peripheral shutdown callback. + * @metadata_release: Image metadata release callback. + */ +struct qcom_pas_ops { + const char *drv_name; + struct device *dev; + bool (*supported)(struct device *dev, u32 pas_id); + int (*init_image)(struct device *dev, u32 pas_id, const void *metadata, + size_t size, struct qcom_pas_context *ctx); + int (*mem_setup)(struct device *dev, u32 pas_id, phys_addr_t addr, + phys_addr_t size); + void *(*get_rsc_table)(struct device *dev, struct qcom_pas_context *ctx, + void *input_rt, size_t input_rt_size, + size_t *output_rt_size); + int (*prepare_and_auth_reset)(struct device *dev, + struct qcom_pas_context *ctx); + int (*auth_and_reset)(struct device *dev, u32 pas_id); + int (*set_remote_state)(struct device *dev, u32 state, u32 pas_id); + int (*shutdown)(struct device *dev, u32 pas_id); + void (*metadata_release)(struct device *dev, + struct qcom_pas_context *ctx); +}; + +void qcom_pas_ops_register(struct qcom_pas_ops *ops); +void qcom_pas_ops_unregister(void); + +#endif /* __QCOM_PAS_INT_H */ diff --git a/include/linux/firmware/qcom/qcom_pas.h b/include/linux/firmwar= e/qcom/qcom_pas.h new file mode 100644 index 000000000000..65b1c9564458 --- /dev/null +++ b/include/linux/firmware/qcom/qcom_pas.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights res= erved. + * Copyright (C) 2015 Linaro Ltd. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __QCOM_PAS_H +#define __QCOM_PAS_H + +#include +#include + +struct qcom_pas_context { + struct device *dev; + u32 pas_id; + phys_addr_t mem_phys; + size_t mem_size; + void *ptr; + dma_addr_t phys; + ssize_t size; + bool use_tzmem; +}; + +bool qcom_pas_is_available(void); +struct qcom_pas_context *devm_qcom_pas_context_alloc(struct device *dev, + u32 pas_id, + phys_addr_t mem_phys, + size_t mem_size); +int qcom_pas_init_image(u32 pas_id, const void *metadata, size_t size, + struct qcom_pas_context *ctx); +struct resource_table *qcom_pas_get_rsc_table(struct qcom_pas_context *ctx, + void *input_rt, size_t input_rt_size, + size_t *output_rt_size); +int qcom_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size); +int qcom_pas_auth_and_reset(u32 pas_id); +int qcom_pas_prepare_and_auth_reset(struct qcom_pas_context *ctx); +int qcom_pas_set_remote_state(u32 state, u32 pas_id); +int qcom_pas_shutdown(u32 pas_id); +bool qcom_pas_supported(u32 pas_id); +void qcom_pas_metadata_release(struct qcom_pas_context *ctx); + +#endif /* __QCOM_PAS_H */ --=20 2.51.0 From nobody Sun May 24 19:33:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58F70371876; Fri, 22 May 2026 12:00:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779451254; cv=none; b=FbI067LnP7wVKIDdDyjL/ItEPGJ+zrwtGgpE7whyqPVXTPhebS1376HmIqyXzDH84d3OjG46G8PJOtsZbe/skxs7dbcNOrVqASjW9l1qtGVEfo9oPxB133Zk1H2olTA1eB8hDNapzv7H6b152FFoT4r1McMDww3nquWLLwWYU9c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779451254; c=relaxed/simple; bh=7bxinOIcX02WrbjMoHBnAazLoG4z2SXHsLaE3NHbFjs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sNUDfDzsJOLSNwXGKSgo1RfnD2em8ruebTsFzgpGcbkx4HSoVheepuwibgC77qGJ68qZhtznWhBylHr0M0JbVamQm5mJdMY+pJnlTJu6dKiLk+R9YB/dblYKEGgbBGz5183zFw8NjwBsYqjkbqGbMyAua4LgLjGQSRjvzPwwLQU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gFQdIZyP; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gFQdIZyP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 90A301F00A3D; Fri, 22 May 2026 12:00:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779451252; bh=YSocI/bhL9pCKFAii3Y3d9xTukYPGEeat4hxTy2tE3k=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=gFQdIZyPv+3qmTMbwNSdA0hzRTsOXGCYVVs4jlj/wx8+Ng4mBpMYJcJdJtnSW2ths JD+NTCSNRWHoHSuQdtohA1H3XxfZOSSta0wAGUztDG+MqBHvy9zGwiyS58wXbvrKb9 Xo7NQyA2TnHpMENpzd3yT8eYsas0O6B0VXpf3J3vG48PMqiIc/jIAW6A/Pf0r3kq1x ZfF40NIXqg1WEZe8NJiAs4v6c2CrcqSGd2Y9opVAO6sHPZ8OVadT9d5PZENLC38oJe NXBsKu0sKJ6KB3E/8FfNzhK1Et774/i9DfMuCtsZ6ikciiT3P6XAQIEjF+ZWoJJGCO 8LDx94QpQBRaA== From: Sumit Garg To: andersson@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg , Harshal Dev Subject: [PATCH v7 03/15] firmware: qcom_scm: Migrate to generic PAS service Date: Fri, 22 May 2026 17:29:24 +0530 Message-ID: <20260522115936.201208-4-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260522115936.201208-1-sumit.garg@kernel.org> References: <20260522115936.201208-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg With the availability of generic PAS service, let's add SCM calls as a backend to keep supporting legacy QTEE interfaces. The exported qcom_scm* wrappers will get dropped once all the client drivers get migrated as part of future patches. Tested-by: Mukesh Ojha # Lemans Reviewed-by: Harshal Dev Tested-by: Vignesh Viswanathan # IPQ= 9650 Signed-off-by: Sumit Garg --- drivers/firmware/qcom/Kconfig | 3 +- drivers/firmware/qcom/qcom_scm.c | 335 ++++++++++++++----------------- 2 files changed, 156 insertions(+), 182 deletions(-) diff --git a/drivers/firmware/qcom/Kconfig b/drivers/firmware/qcom/Kconfig index 9f66cc774508..732a0bff7d9f 100644 --- a/drivers/firmware/qcom/Kconfig +++ b/drivers/firmware/qcom/Kconfig @@ -15,8 +15,9 @@ config QCOM_PAS TEE bus based PAS service implementation. =20 config QCOM_SCM + tristate "Qualcomm PAS SCM interface driver" + select QCOM_PAS select QCOM_TZMEM - tristate =20 config QCOM_TZMEM tristate diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index 6b601a4b89db..7933e55803dc 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -33,6 +34,7 @@ =20 #include =20 +#include "qcom_pas.h" #include "qcom_scm.h" #include "qcom_tzmem.h" =20 @@ -479,25 +481,6 @@ void qcom_scm_cpu_power_down(u32 flags) } EXPORT_SYMBOL_GPL(qcom_scm_cpu_power_down); =20 -int qcom_scm_set_remote_state(u32 state, u32 id) -{ - struct qcom_scm_desc desc =3D { - .svc =3D QCOM_SCM_SVC_BOOT, - .cmd =3D QCOM_SCM_BOOT_SET_REMOTE_STATE, - .arginfo =3D QCOM_SCM_ARGS(2), - .args[0] =3D state, - .args[1] =3D id, - .owner =3D ARM_SMCCC_OWNER_SIP, - }; - struct qcom_scm_res res; - int ret; - - ret =3D qcom_scm_call(__scm->dev, &desc, &res); - - return ret ? : res.result[0]; -} -EXPORT_SYMBOL_GPL(qcom_scm_set_remote_state); - static int qcom_scm_disable_sdi(void) { int ret; @@ -570,26 +553,12 @@ static void qcom_scm_set_download_mode(u32 dload_mode) dev_err(__scm->dev, "failed to set download mode: %d\n", ret); } =20 -/** - * devm_qcom_scm_pas_context_alloc() - Allocate peripheral authentication = service - * context for a given peripheral - * - * PAS context is device-resource managed, so the caller does not need - * to worry about freeing the context memory. - * - * @dev: PAS firmware device - * @pas_id: peripheral authentication service id - * @mem_phys: Subsystem reserve memory start address - * @mem_size: Subsystem reserve memory size - * - * Returns: The new PAS context, or ERR_PTR() on failure. - */ struct qcom_scm_pas_context *devm_qcom_scm_pas_context_alloc(struct device= *dev, u32 pas_id, phys_addr_t mem_phys, size_t mem_size) { - struct qcom_scm_pas_context *ctx; + struct qcom_pas_context *ctx; =20 ctx =3D devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); if (!ctx) @@ -600,11 +569,12 @@ struct qcom_scm_pas_context *devm_qcom_scm_pas_contex= t_alloc(struct device *dev, ctx->mem_phys =3D mem_phys; ctx->mem_size =3D mem_size; =20 - return ctx; + return (struct qcom_scm_pas_context *)ctx; } EXPORT_SYMBOL_GPL(devm_qcom_scm_pas_context_alloc); =20 -static int __qcom_scm_pas_init_image(u32 pas_id, dma_addr_t mdata_phys, +static int __qcom_scm_pas_init_image(struct device *dev, u32 pas_id, + dma_addr_t mdata_phys, struct qcom_scm_res *res) { struct qcom_scm_desc desc =3D { @@ -626,7 +596,7 @@ static int __qcom_scm_pas_init_image(u32 pas_id, dma_ad= dr_t mdata_phys, =20 desc.args[1] =3D mdata_phys; =20 - ret =3D qcom_scm_call(__scm->dev, &desc, res); + ret =3D qcom_scm_call(dev, &desc, res); qcom_scm_bw_disable(); =20 disable_clk: @@ -635,7 +605,8 @@ static int __qcom_scm_pas_init_image(u32 pas_id, dma_ad= dr_t mdata_phys, return ret; } =20 -static int qcom_scm_pas_prep_and_init_image(struct qcom_scm_pas_context *c= tx, +static int qcom_scm_pas_prep_and_init_image(struct device *dev, + struct qcom_pas_context *ctx, const void *metadata, size_t size) { struct qcom_scm_res res; @@ -650,7 +621,7 @@ static int qcom_scm_pas_prep_and_init_image(struct qcom= _scm_pas_context *ctx, memcpy(mdata_buf, metadata, size); mdata_phys =3D qcom_tzmem_to_phys(mdata_buf); =20 - ret =3D __qcom_scm_pas_init_image(ctx->pas_id, mdata_phys, &res); + ret =3D __qcom_scm_pas_init_image(dev, ctx->pas_id, mdata_phys, &res); if (ret < 0) qcom_tzmem_free(mdata_buf); else @@ -659,25 +630,9 @@ static int qcom_scm_pas_prep_and_init_image(struct qco= m_scm_pas_context *ctx, return ret ? : res.result[0]; } =20 -/** - * qcom_scm_pas_init_image() - Initialize peripheral authentication service - * state machine for a given peripheral, using the - * metadata - * @pas_id: peripheral authentication service id - * @metadata: pointer to memory containing ELF header, program header table - * and optional blob of data used for authenticating the metadata - * and the rest of the firmware - * @size: size of the metadata - * @ctx: optional pas context - * - * Return: 0 on success. - * - * Upon successful return, the PAS metadata context (@ctx) will be used to - * track the metadata allocation, this needs to be released by invoking - * qcom_scm_pas_metadata_release() by the caller. - */ -int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size, - struct qcom_scm_pas_context *ctx) +static int __qcom_scm_pas_init_image2(struct device *dev, u32 pas_id, + const void *metadata, size_t size, + struct qcom_pas_context *ctx) { struct qcom_scm_res res; dma_addr_t mdata_phys; @@ -685,7 +640,7 @@ int qcom_scm_pas_init_image(u32 pas_id, const void *met= adata, size_t size, int ret; =20 if (ctx && ctx->use_tzmem) - return qcom_scm_pas_prep_and_init_image(ctx, metadata, size); + return qcom_scm_pas_prep_and_init_image(dev, ctx, metadata, size); =20 /* * During the scm call memory protection will be enabled for the meta @@ -699,16 +654,15 @@ int qcom_scm_pas_init_image(u32 pas_id, const void *m= etadata, size_t size, * If we pass a buffer that is already part of an SHM Bridge to this * call, it will fail. */ - mdata_buf =3D dma_alloc_coherent(__scm->dev, size, &mdata_phys, - GFP_KERNEL); + mdata_buf =3D dma_alloc_coherent(dev, size, &mdata_phys, GFP_KERNEL); if (!mdata_buf) return -ENOMEM; =20 memcpy(mdata_buf, metadata, size); =20 - ret =3D __qcom_scm_pas_init_image(pas_id, mdata_phys, &res); + ret =3D __qcom_scm_pas_init_image(dev, pas_id, mdata_phys, &res); if (ret < 0 || !ctx) { - dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys); + dma_free_coherent(dev, size, mdata_buf, mdata_phys); } else if (ctx) { ctx->ptr =3D mdata_buf; ctx->phys =3D mdata_phys; @@ -717,36 +671,35 @@ int qcom_scm_pas_init_image(u32 pas_id, const void *m= etadata, size_t size, =20 return ret ? : res.result[0]; } -EXPORT_SYMBOL_GPL(qcom_scm_pas_init_image); =20 -/** - * qcom_scm_pas_metadata_release() - release metadata context - * @ctx: pas context - */ -void qcom_scm_pas_metadata_release(struct qcom_scm_pas_context *ctx) +int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size, + struct qcom_scm_pas_context *ctx) { - if (!ctx->ptr) - return; + return __qcom_scm_pas_init_image2(__scm->dev, pas_id, metadata, size, + (struct qcom_pas_context *)ctx); +} +EXPORT_SYMBOL_GPL(qcom_scm_pas_init_image); =20 +static void __qcom_scm_pas_metadata_release(struct device *dev, + struct qcom_pas_context *ctx) +{ if (ctx->use_tzmem) qcom_tzmem_free(ctx->ptr); else - dma_free_coherent(__scm->dev, ctx->size, ctx->ptr, ctx->phys); + dma_free_coherent(dev, ctx->size, ctx->ptr, ctx->phys); =20 ctx->ptr =3D NULL; } + +void qcom_scm_pas_metadata_release(struct qcom_scm_pas_context *ctx) +{ + __qcom_scm_pas_metadata_release(__scm->dev, + (struct qcom_pas_context *)ctx); +} EXPORT_SYMBOL_GPL(qcom_scm_pas_metadata_release); =20 -/** - * qcom_scm_pas_mem_setup() - Prepare the memory related to a given periph= eral - * for firmware loading - * @pas_id: peripheral authentication service id - * @addr: start address of memory area to prepare - * @size: size of the memory area to prepare - * - * Returns 0 on success. - */ -int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size) +static int __qcom_scm_pas_mem_setup(struct device *dev, u32 pas_id, + phys_addr_t addr, phys_addr_t size) { int ret; struct qcom_scm_desc desc =3D { @@ -768,7 +721,7 @@ int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr= , phys_addr_t size) if (ret) goto disable_clk; =20 - ret =3D qcom_scm_call(__scm->dev, &desc, &res); + ret =3D qcom_scm_call(dev, &desc, &res); qcom_scm_bw_disable(); =20 disable_clk: @@ -776,9 +729,15 @@ int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t add= r, phys_addr_t size) =20 return ret ? : res.result[0]; } + +int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size) +{ + return __qcom_scm_pas_mem_setup(__scm->dev, pas_id, addr, size); +} EXPORT_SYMBOL_GPL(qcom_scm_pas_mem_setup); =20 -static void *__qcom_scm_pas_get_rsc_table(u32 pas_id, void *input_rt_tzm, +static void *__qcom_scm_pas_get_rsc_table(struct device *dev, u32 pas_id, + void *input_rt_tzm, size_t input_rt_size, size_t *output_rt_size) { @@ -813,7 +772,7 @@ static void *__qcom_scm_pas_get_rsc_table(u32 pas_id, v= oid *input_rt_tzm, * with output_rt_tzm buffer with res.result[2] size however, It should n= ot * be of unresonable size. */ - ret =3D qcom_scm_call(__scm->dev, &desc, &res); + ret =3D qcom_scm_call(dev, &desc, &res); if (!ret && res.result[2] > SZ_1G) { ret =3D -E2BIG; goto free_output_rt; @@ -830,51 +789,11 @@ static void *__qcom_scm_pas_get_rsc_table(u32 pas_id,= void *input_rt_tzm, return ret ? ERR_PTR(ret) : output_rt_tzm; } =20 -/** - * qcom_scm_pas_get_rsc_table() - Retrieve the resource table in passed ou= tput buffer - * for a given peripheral. - * - * Qualcomm remote processor may rely on both static and dynamic resources= for - * its functionality. Static resources typically refer to memory-mapped ad= dresses - * required by the subsystem and are often embedded within the firmware bi= nary - * and dynamic resources, such as shared memory in DDR etc., are determine= d at - * runtime during the boot process. - * - * On Qualcomm Technologies devices, it's possible that static resources a= re not - * embedded in the firmware binary and instead are provided by TrustZone H= owever, - * dynamic resources are always expected to come from TrustZone. This indi= cates - * that for Qualcomm devices, all resources (static and dynamic) will be p= rovided - * by TrustZone via the SMC call. - * - * If the remote processor firmware binary does contain static resources, = they - * should be passed in input_rt. These will be forwarded to TrustZone for - * authentication. TrustZone will then append the dynamic resources and re= turn - * the complete resource table in output_rt_tzm. - * - * If the remote processor firmware binary does not include a resource tab= le, - * the caller of this function should set input_rt as NULL and input_rt_si= ze - * as zero respectively. - * - * More about documentation on resource table data structures can be found= in - * include/linux/remoteproc.h - * - * @ctx: PAS context - * @pas_id: peripheral authentication service id - * @input_rt: resource table buffer which is present in firmware bin= ary - * @input_rt_size: size of the resource table present in firmware binary - * @output_rt_size: TrustZone expects caller should pass worst case size f= or - * the output_rt_tzm. - * - * Return: - * On success, returns a pointer to the allocated buffer containing the f= inal - * resource table and output_rt_size will have actual resource table size= from - * TrustZone. The caller is responsible for freeing the buffer. On failur= e, - * returns ERR_PTR(-errno). - */ -struct resource_table *qcom_scm_pas_get_rsc_table(struct qcom_scm_pas_cont= ext *ctx, - void *input_rt, - size_t input_rt_size, - size_t *output_rt_size) +static void *__qcom_scm_pas_get_rsc_table2(struct device *dev, + struct qcom_pas_context *ctx, + void *input_rt, + size_t input_rt_size, + size_t *output_rt_size) { struct resource_table empty_rsc =3D {}; size_t size =3D SZ_16K; @@ -909,11 +828,12 @@ struct resource_table *qcom_scm_pas_get_rsc_table(str= uct qcom_scm_pas_context *c =20 memcpy(input_rt_tzm, input_rt, input_rt_size); =20 - output_rt_tzm =3D __qcom_scm_pas_get_rsc_table(ctx->pas_id, input_rt_tzm, + output_rt_tzm =3D __qcom_scm_pas_get_rsc_table(dev, ctx->pas_id, + input_rt_tzm, input_rt_size, &size); if (PTR_ERR(output_rt_tzm) =3D=3D -EOVERFLOW) /* Try again with the size requested by the TZ */ - output_rt_tzm =3D __qcom_scm_pas_get_rsc_table(ctx->pas_id, + output_rt_tzm =3D __qcom_scm_pas_get_rsc_table(dev, ctx->pas_id, input_rt_tzm, input_rt_size, &size); @@ -943,16 +863,20 @@ struct resource_table *qcom_scm_pas_get_rsc_table(str= uct qcom_scm_pas_context *c =20 return ret ? ERR_PTR(ret) : tbl_ptr; } + +struct resource_table *qcom_scm_pas_get_rsc_table(struct qcom_scm_pas_cont= ext *ctx, + void *input_rt, + size_t input_rt_size, + size_t *output_rt_size) +{ + return __qcom_scm_pas_get_rsc_table2(__scm->dev, + (struct qcom_pas_context *)ctx, + input_rt, input_rt_size, + output_rt_size); +} EXPORT_SYMBOL_GPL(qcom_scm_pas_get_rsc_table); =20 -/** - * qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmw= are - * and reset the remote processor - * @pas_id: peripheral authentication service id - * - * Return 0 on success. - */ -int qcom_scm_pas_auth_and_reset(u32 pas_id) +static int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 pas_id) { int ret; struct qcom_scm_desc desc =3D { @@ -972,7 +896,7 @@ int qcom_scm_pas_auth_and_reset(u32 pas_id) if (ret) goto disable_clk; =20 - ret =3D qcom_scm_call(__scm->dev, &desc, &res); + ret =3D qcom_scm_call(dev, &desc, &res); qcom_scm_bw_disable(); =20 disable_clk: @@ -980,28 +904,15 @@ int qcom_scm_pas_auth_and_reset(u32 pas_id) =20 return ret ? : res.result[0]; } + +int qcom_scm_pas_auth_and_reset(u32 pas_id) +{ + return __qcom_scm_pas_auth_and_reset(__scm->dev, pas_id); +} EXPORT_SYMBOL_GPL(qcom_scm_pas_auth_and_reset); =20 -/** - * qcom_scm_pas_prepare_and_auth_reset() - Prepare, authenticate, and rese= t the - * remote processor - * - * @ctx: Context saved during call to qcom_scm_pas_context_init() - * - * This function performs the necessary steps to prepare a PAS subsystem, - * authenticate it using the provided metadata, and initiate a reset seque= nce. - * - * It should be used when Linux is in control setting up the IOMMU hardware - * for remote subsystem during secure firmware loading processes. The prep= aration - * step sets up a shmbridge over the firmware memory before TrustZone acce= sses the - * firmware memory region for authentication. The authentication step veri= fies - * the integrity and authenticity of the firmware or configuration using s= ecure - * metadata. Finally, the reset step ensures the subsystem starts in a cle= an and - * sane state. - * - * Return: 0 on success, negative errno on failure. - */ -int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_context *ctx) +static int __qcom_scm_pas_prepare_and_auth_reset(struct device *dev, + struct qcom_pas_context *ctx) { u64 handle; int ret; @@ -1012,7 +923,7 @@ int qcom_scm_pas_prepare_and_auth_reset(struct qcom_sc= m_pas_context *ctx) * memory region and then invokes a call to TrustZone to authenticate. */ if (!ctx->use_tzmem) - return qcom_scm_pas_auth_and_reset(ctx->pas_id); + return __qcom_scm_pas_auth_and_reset(dev, ctx->pas_id); =20 /* * When Linux runs @ EL2 Linux must create the shmbridge itself and then @@ -1022,20 +933,45 @@ int qcom_scm_pas_prepare_and_auth_reset(struct qcom_= scm_pas_context *ctx) if (ret) return ret; =20 - ret =3D qcom_scm_pas_auth_and_reset(ctx->pas_id); + ret =3D __qcom_scm_pas_auth_and_reset(dev, ctx->pas_id); qcom_tzmem_shm_bridge_delete(handle); =20 return ret; } + +int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_context *ctx) +{ + return __qcom_scm_pas_prepare_and_auth_reset(__scm->dev, + (struct qcom_pas_context *)ctx); +} EXPORT_SYMBOL_GPL(qcom_scm_pas_prepare_and_auth_reset); =20 -/** - * qcom_scm_pas_shutdown() - Shut down the remote processor - * @pas_id: peripheral authentication service id - * - * Returns 0 on success. - */ -int qcom_scm_pas_shutdown(u32 pas_id) +static int __qcom_scm_pas_set_remote_state(struct device *dev, u32 state, + u32 pas_id) +{ + struct qcom_scm_desc desc =3D { + .svc =3D QCOM_SCM_SVC_BOOT, + .cmd =3D QCOM_SCM_BOOT_SET_REMOTE_STATE, + .arginfo =3D QCOM_SCM_ARGS(2), + .args[0] =3D state, + .args[1] =3D pas_id, + .owner =3D ARM_SMCCC_OWNER_SIP, + }; + struct qcom_scm_res res; + int ret; + + ret =3D qcom_scm_call(dev, &desc, &res); + + return ret ? : res.result[0]; +} + +int qcom_scm_set_remote_state(u32 state, u32 id) +{ + return __qcom_scm_pas_set_remote_state(__scm->dev, state, id); +} +EXPORT_SYMBOL_GPL(qcom_scm_set_remote_state); + +static int __qcom_scm_pas_shutdown(struct device *dev, u32 pas_id) { int ret; struct qcom_scm_desc desc =3D { @@ -1055,7 +991,7 @@ int qcom_scm_pas_shutdown(u32 pas_id) if (ret) goto disable_clk; =20 - ret =3D qcom_scm_call(__scm->dev, &desc, &res); + ret =3D qcom_scm_call(dev, &desc, &res); qcom_scm_bw_disable(); =20 disable_clk: @@ -1063,16 +999,14 @@ int qcom_scm_pas_shutdown(u32 pas_id) =20 return ret ? : res.result[0]; } + +int qcom_scm_pas_shutdown(u32 pas_id) +{ + return __qcom_scm_pas_shutdown(__scm->dev, pas_id); +} EXPORT_SYMBOL_GPL(qcom_scm_pas_shutdown); =20 -/** - * qcom_scm_pas_supported() - Check if the peripheral authentication servi= ce is - * available for the given peripherial - * @pas_id: peripheral authentication service id - * - * Returns true if PAS is supported for this peripheral, otherwise false. - */ -bool qcom_scm_pas_supported(u32 pas_id) +static bool __qcom_scm_pas_supported(struct device *dev, u32 pas_id) { int ret; struct qcom_scm_desc desc =3D { @@ -1084,16 +1018,49 @@ bool qcom_scm_pas_supported(u32 pas_id) }; struct qcom_scm_res res; =20 - if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL, + if (!__qcom_scm_is_call_available(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_IS_SUPPORTED)) return false; =20 - ret =3D qcom_scm_call(__scm->dev, &desc, &res); + ret =3D qcom_scm_call(dev, &desc, &res); =20 return ret ? false : !!res.result[0]; } + +bool qcom_scm_pas_supported(u32 pas_id) +{ + return __qcom_scm_pas_supported(__scm->dev, pas_id); +} EXPORT_SYMBOL_GPL(qcom_scm_pas_supported); =20 +static struct qcom_pas_ops qcom_pas_ops_scm =3D { + .drv_name =3D "qcom_scm", + .supported =3D __qcom_scm_pas_supported, + .init_image =3D __qcom_scm_pas_init_image2, + .mem_setup =3D __qcom_scm_pas_mem_setup, + .get_rsc_table =3D __qcom_scm_pas_get_rsc_table2, + .auth_and_reset =3D __qcom_scm_pas_auth_and_reset, + .prepare_and_auth_reset =3D __qcom_scm_pas_prepare_and_auth_reset, + .set_remote_state =3D __qcom_scm_pas_set_remote_state, + .shutdown =3D __qcom_scm_pas_shutdown, + .metadata_release =3D __qcom_scm_pas_metadata_release, +}; + +/** + * qcom_scm_is_pas_available() - Check if the peripheral authentication se= rvice + * is available via SCM or not + * + * Returns true if PAS is available, otherwise false. + */ +static bool qcom_scm_is_pas_available(void) +{ + if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL, + QCOM_SCM_PIL_PAS_AUTH_AND_RESET)) + return false; + + return true; +} + static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) { struct qcom_scm_desc desc =3D { @@ -2837,6 +2804,11 @@ static int qcom_scm_probe(struct platform_device *pd= ev) =20 __get_convention(); =20 + if (qcom_scm_is_pas_available()) { + qcom_pas_ops_scm.dev =3D scm->dev; + qcom_pas_ops_register(&qcom_pas_ops_scm); + } + /* * If "download mode" is requested, from this point on warmboot * will cause the boot stages to enter download mode, unless @@ -2876,6 +2848,7 @@ static void qcom_scm_shutdown(struct platform_device = *pdev) { /* Clean shutdown, disable download mode to allow normal restart */ qcom_scm_set_download_mode(QCOM_DLOAD_NODUMP); + qcom_pas_ops_unregister(); } =20 static const struct of_device_id qcom_scm_dt_match[] =3D { --=20 2.51.0 From nobody Sun May 24 19:33:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B0B22F531B; Fri, 22 May 2026 12:01:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779451270; cv=none; b=aWGjLAmjzI7eOgeYjNtMau8/3NvyhNb/dXuMH4B1o68rf8XWpkWNPuvVh3c2it9fMfm917J6wC4HEHsd4qTvSKFvcsI4qV0P98H5CRiozkfF822R1QJax5pTMlqEGYxlILDwVnhimLJ20tHoXs2NQxIBBS07kOJVt5qgnw9FfMs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779451270; c=relaxed/simple; bh=1FxKC93QB3RuVIm0oAsHMRhvwKzwBmluakjgPEPaajo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kE/L+ntm3vCOj4iK51NMtR8j4cQWxSnTVoffhayvK7a6BMidoFX8BWeMzotAk+IwbMEPDpSfh+GQExTcBZ3DVDkat1H3OIoXbzEa/oh7+a14HGdYXllV3oguAxCQsT9HQ6d106wTScDcQyEHuKjHDkr7q8Wq9f9CQmkaiJl1lU0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nqXcCLW3; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nqXcCLW3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A02301F000E9; Fri, 22 May 2026 12:00:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779451268; bh=lEiCUBuFEqeKwPq/1mehizfr45j5ZmTvihe/s1VPklQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=nqXcCLW3+UxbGHFaS/praVM8oqCTbz3neN/xlwrfXPAPU/SFivqyqe2BbWfgTj5ig I60M/QUVABo1NC8EzP4x19szQKZfYoTYMZdhNTDPlTSunjh+5WiX5bcWGnoSwC9CXo EPC3+/g/olU4eEauywe6c/1Ug5AW8PRiN4NI4ZPOzAJcc2c6jiwqabptLyn8JLfRsI uQXAfPCbPgLA/hlfnDSOl4SPuz/fCoiIeZlAciG0c4KrI8zEgy8yMpob0QYx7uRyko 4pFp9z/tWzPyLc6U8pLC6bKq/qJx7rpkL5npb5PyCaRoDQ3XrSlbxJjtG30IMcPp4x Tsvb3APbCp+5A== From: Sumit Garg To: andersson@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg , Harshal Dev Subject: [PATCH v7 04/15] firmware: qcom: Add a PAS TEE service Date: Fri, 22 May 2026 17:29:25 +0530 Message-ID: <20260522115936.201208-5-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260522115936.201208-1-sumit.garg@kernel.org> References: <20260522115936.201208-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg Add support for Peripheral Authentication Service (PAS) driver based on TEE bus with OP-TEE providing the backend PAS service implementation. The TEE PAS service ABI is designed to be extensible with additional API as PTA_QCOM_PAS_CAPABILITIES. This allows to accommodate any future extensions of the PAS service needed while still maintaining backwards compatibility. Reviewed-by: Mukesh Ojha Tested-by: Mukesh Ojha # Lemans Reviewed-by: Harshal Dev Tested-by: Vignesh Viswanathan # IPQ= 9650 Signed-off-by: Sumit Garg --- drivers/firmware/qcom/Kconfig | 10 + drivers/firmware/qcom/Makefile | 1 + drivers/firmware/qcom/qcom_pas_tee.c | 477 +++++++++++++++++++++++++++ 3 files changed, 488 insertions(+) create mode 100644 drivers/firmware/qcom/qcom_pas_tee.c diff --git a/drivers/firmware/qcom/Kconfig b/drivers/firmware/qcom/Kconfig index 732a0bff7d9f..b851bcc592be 100644 --- a/drivers/firmware/qcom/Kconfig +++ b/drivers/firmware/qcom/Kconfig @@ -14,6 +14,16 @@ config QCOM_PAS backends plugged in whether it's an SCM implementation or a proper TEE bus based PAS service implementation. =20 +config QCOM_PAS_TEE + tristate "Qualcomm PAS TEE interface driver" + select QCOM_PAS + depends on TEE + depends on !CPU_BIG_ENDIAN + default m if ARCH_QCOM + help + Enable the generic Peripheral Authentication Service (PAS) provided + by the firmware TEE implementation as the backend. + config QCOM_SCM tristate "Qualcomm PAS SCM interface driver" select QCOM_PAS diff --git a/drivers/firmware/qcom/Makefile b/drivers/firmware/qcom/Makefile index dc5ab45f906a..48801d18f37b 100644 --- a/drivers/firmware/qcom/Makefile +++ b/drivers/firmware/qcom/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_QCOM_TZMEM) +=3D qcom_tzmem.o obj-$(CONFIG_QCOM_QSEECOM) +=3D qcom_qseecom.o obj-$(CONFIG_QCOM_QSEECOM_UEFISECAPP) +=3D qcom_qseecom_uefisecapp.o obj-$(CONFIG_QCOM_PAS) +=3D qcom_pas.o +obj-$(CONFIG_QCOM_PAS_TEE) +=3D qcom_pas_tee.o diff --git a/drivers/firmware/qcom/qcom_pas_tee.c b/drivers/firmware/qcom/q= com_pas_tee.c new file mode 100644 index 000000000000..a2ba3af05a50 --- /dev/null +++ b/drivers/firmware/qcom/qcom_pas_tee.c @@ -0,0 +1,477 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "qcom_pas.h" + +/* + * Peripheral Authentication Service (PAS) supported. + * + * [in] params[0].value.a: Unique 32bit remote processor identifier + */ +#define TA_QCOM_PAS_IS_SUPPORTED 1 + +/* + * PAS capabilities. + * + * [in] params[0].value.a: Unique 32bit remote processor identifier + * [out] params[1].value.a: PAS capability flags + */ +#define TA_QCOM_PAS_CAPABILITIES 2 + +/* + * PAS image initialization. + * + * [in] params[0].value.a: Unique 32bit remote processor identifier + * [in] params[1].memref: Loadable firmware metadata + */ +#define TA_QCOM_PAS_INIT_IMAGE 3 + +/* + * PAS memory setup. + * + * [in] params[0].value.a: Unique 32bit remote processor identifier + * [in] params[0].value.b: Relocatable firmware size + * [in] params[1].value.a: 32bit LSB relocatable firmware memory address + * [in] params[1].value.b: 32bit MSB relocatable firmware memory address + */ +#define TA_QCOM_PAS_MEM_SETUP 4 + +/* + * PAS get resource table. + * + * [in] params[0].value.a: Unique 32bit remote processor identifier + * [inout] params[1].memref: Resource table config + */ +#define TA_QCOM_PAS_GET_RESOURCE_TABLE 5 + +/* + * PAS image authentication and co-processor reset. + * + * [in] params[0].value.a: Unique 32bit remote processor identifier + * [in] params[0].value.b: Firmware size + * [in] params[1].value.a: 32bit LSB firmware memory address + * [in] params[1].value.b: 32bit MSB firmware memory address + * [in] params[2].memref: Optional fw memory space shared/lent + */ +#define TA_QCOM_PAS_AUTH_AND_RESET 6 + +/* + * PAS co-processor set suspend/resume state. + * + * [in] params[0].value.a: Unique 32bit remote processor identifier + * [in] params[0].value.b: Co-processor state identifier + */ +#define TA_QCOM_PAS_SET_REMOTE_STATE 7 + +/* + * PAS co-processor shutdown. + * + * [in] params[0].value.a: Unique 32bit remote processor identifier + */ +#define TA_QCOM_PAS_SHUTDOWN 8 + +#define TEE_NUM_PARAMS 4 + +/** + * struct qcom_pas_tee_private - PAS service private data + * @dev: PAS service device. + * @ctx: TEE context handler. + * @session_id: PAS TA session identifier. + */ +struct qcom_pas_tee_private { + struct device *dev; + struct tee_context *ctx; + u32 session_id; +}; + +static bool qcom_pas_tee_supported(struct device *dev, u32 pas_id) +{ + struct qcom_pas_tee_private *data =3D dev_get_drvdata(dev); + struct tee_ioctl_invoke_arg inv_arg =3D { + .func =3D TA_QCOM_PAS_IS_SUPPORTED, + .session =3D data->session_id, + .num_params =3D TEE_NUM_PARAMS + }; + struct tee_param param[4] =3D { + [0] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT, + .u.value.a =3D pas_id + } + }; + int ret; + + ret =3D tee_client_invoke_func(data->ctx, &inv_arg, param); + if (ret < 0 || inv_arg.ret !=3D 0) { + dev_err(dev, "PAS not supported, pas_id: %d, ret: %d, err: 0x%x\n", + pas_id, ret, inv_arg.ret); + return false; + } + + return true; +} + +static int qcom_pas_tee_init_image(struct device *dev, u32 pas_id, + const void *metadata, size_t size, + struct qcom_pas_context *ctx) +{ + struct qcom_pas_tee_private *data =3D dev_get_drvdata(dev); + struct tee_ioctl_invoke_arg inv_arg =3D { + .func =3D TA_QCOM_PAS_INIT_IMAGE, + .session =3D data->session_id, + .num_params =3D TEE_NUM_PARAMS + }; + struct tee_param param[4] =3D { + [0] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT, + .u.value.a =3D pas_id + }, + [1] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INPUT, + } + }; + struct tee_shm *mdata_shm; + u8 *mdata_buf =3D NULL; + int ret; + + mdata_shm =3D tee_shm_alloc_kernel_buf(data->ctx, size); + if (IS_ERR(mdata_shm)) { + dev_err(dev, "mdata_shm allocation failed\n"); + return PTR_ERR(mdata_shm); + } + + mdata_buf =3D tee_shm_get_va(mdata_shm, 0); + if (IS_ERR(mdata_buf)) { + dev_err(dev, "mdata_buf get VA failed\n"); + tee_shm_free(mdata_shm); + return PTR_ERR(mdata_buf); + } + memcpy(mdata_buf, metadata, size); + + param[1].u.memref.shm =3D mdata_shm; + param[1].u.memref.size =3D size; + + ret =3D tee_client_invoke_func(data->ctx, &inv_arg, param); + if (ret < 0 || inv_arg.ret !=3D 0) { + dev_err(dev, "PAS init image failed, pas_id: %d, ret: %d, err: 0x%x\n", + pas_id, ret, inv_arg.ret); + tee_shm_free(mdata_shm); + return ret ?: -EINVAL; + } + + if (ctx) + ctx->ptr =3D (void *)mdata_shm; + else + tee_shm_free(mdata_shm); + + return ret; +} + +static int qcom_pas_tee_mem_setup(struct device *dev, u32 pas_id, + phys_addr_t addr, phys_addr_t size) +{ + struct qcom_pas_tee_private *data =3D dev_get_drvdata(dev); + struct tee_ioctl_invoke_arg inv_arg =3D { + .func =3D TA_QCOM_PAS_MEM_SETUP, + .session =3D data->session_id, + .num_params =3D TEE_NUM_PARAMS + }; + struct tee_param param[4] =3D { + [0] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT, + .u.value.a =3D pas_id, + .u.value.b =3D size, + }, + [1] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT, + .u.value.a =3D lower_32_bits(addr), + .u.value.b =3D upper_32_bits(addr), + } + }; + int ret; + + ret =3D tee_client_invoke_func(data->ctx, &inv_arg, param); + if (ret < 0 || inv_arg.ret !=3D 0) { + dev_err(dev, "PAS mem setup failed, pas_id: %d, ret: %d, err: 0x%x\n", + pas_id, ret, inv_arg.ret); + return ret ?: -EINVAL; + } + + return ret; +} + +DEFINE_FREE(shm_free, struct tee_shm *, tee_shm_free(_T)) + +static void *qcom_pas_tee_get_rsc_table(struct device *dev, + struct qcom_pas_context *ctx, + void *input_rt, size_t input_rt_size, + size_t *output_rt_size) +{ + struct qcom_pas_tee_private *data =3D dev_get_drvdata(dev); + struct tee_ioctl_invoke_arg inv_arg =3D { + .func =3D TA_QCOM_PAS_GET_RESOURCE_TABLE, + .session =3D data->session_id, + .num_params =3D TEE_NUM_PARAMS + }; + struct tee_param param[4] =3D { + [0] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT, + .u.value.a =3D ctx->pas_id, + }, + [1] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INOUT, + .u.memref.size =3D input_rt_size, + } + }; + void *rt_buf =3D NULL; + int ret; + + ret =3D tee_client_invoke_func(data->ctx, &inv_arg, param); + if (ret < 0 || inv_arg.ret !=3D 0) { + dev_err(dev, "PAS get RT failed, pas_id: %d, ret: %d, err: 0x%x\n", + ctx->pas_id, ret, inv_arg.ret); + return ret ? ERR_PTR(ret) : ERR_PTR(-EINVAL); + } + + if (param[1].u.memref.size) { + struct tee_shm *rt_shm __free(shm_free) =3D + tee_shm_alloc_kernel_buf(data->ctx, + param[1].u.memref.size); + void *rt_shm_va; + + if (IS_ERR_OR_NULL(rt_shm)) { + dev_err(dev, "rt_shm allocation failed\n"); + rt_shm =3D NULL; + return ERR_PTR(-ENOMEM); + } + + rt_shm_va =3D tee_shm_get_va(rt_shm, 0); + if (IS_ERR(rt_shm_va)) { + dev_err(dev, "rt_shm get VA failed\n"); + return ERR_CAST(rt_shm_va); + } + memcpy(rt_shm_va, input_rt, input_rt_size); + + param[1].u.memref.shm =3D rt_shm; + ret =3D tee_client_invoke_func(data->ctx, &inv_arg, param); + if (ret < 0 || inv_arg.ret !=3D 0) { + dev_err(dev, "PAS get RT failed, pas_id: %d, ret: %d, err: 0x%x\n", + ctx->pas_id, ret, inv_arg.ret); + return ret ? ERR_PTR(ret) : ERR_PTR(-EINVAL); + } + + if (param[1].u.memref.size) { + *output_rt_size =3D param[1].u.memref.size; + rt_buf =3D kmemdup(rt_shm_va, *output_rt_size, GFP_KERNEL); + if (!rt_buf) + return ERR_PTR(-ENOMEM); + } + } + + return rt_buf; +} + +static int __qcom_pas_tee_auth_and_reset(struct device *dev, u32 pas_id, + phys_addr_t mem_phys, size_t mem_size) +{ + struct qcom_pas_tee_private *data =3D dev_get_drvdata(dev); + struct tee_ioctl_invoke_arg inv_arg =3D { + .func =3D TA_QCOM_PAS_AUTH_AND_RESET, + .session =3D data->session_id, + .num_params =3D TEE_NUM_PARAMS + }; + struct tee_param param[4] =3D { + [0] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT, + .u.value.a =3D pas_id, + .u.value.b =3D mem_size, + }, + [1] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT, + .u.value.a =3D lower_32_bits(mem_phys), + .u.value.b =3D upper_32_bits(mem_phys), + }, + /* Reserved for fw memory space to be shared or lent */ + [2] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INPUT, + } + }; + int ret; + + ret =3D tee_client_invoke_func(data->ctx, &inv_arg, param); + if (ret < 0 || inv_arg.ret !=3D 0) { + dev_err(dev, "PAS auth reset failed, pas_id: %d, ret: %d, err: 0x%x\n", + pas_id, ret, inv_arg.ret); + return ret ?: -EINVAL; + } + + return ret; +} + +static int qcom_pas_tee_auth_and_reset(struct device *dev, u32 pas_id) +{ + return __qcom_pas_tee_auth_and_reset(dev, pas_id, 0, 0); +} + +static int qcom_pas_tee_prepare_and_auth_reset(struct device *dev, + struct qcom_pas_context *ctx) +{ + return __qcom_pas_tee_auth_and_reset(dev, ctx->pas_id, ctx->mem_phys, + ctx->mem_size); +} + +static int qcom_pas_tee_set_remote_state(struct device *dev, u32 state, + u32 pas_id) +{ + struct qcom_pas_tee_private *data =3D dev_get_drvdata(dev); + struct tee_ioctl_invoke_arg inv_arg =3D { + .func =3D TA_QCOM_PAS_SET_REMOTE_STATE, + .session =3D data->session_id, + .num_params =3D TEE_NUM_PARAMS + }; + struct tee_param param[4] =3D { + [0] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT, + .u.value.a =3D pas_id, + .u.value.b =3D state, + } + }; + int ret; + + ret =3D tee_client_invoke_func(data->ctx, &inv_arg, param); + if (ret < 0 || inv_arg.ret !=3D 0) { + dev_err(dev, "PAS set remote state failed, pas_id: %d, ret: %d, err: 0x%= x\n", + pas_id, ret, inv_arg.ret); + return ret ?: -EINVAL; + } + + return ret; +} + +static int qcom_pas_tee_shutdown(struct device *dev, u32 pas_id) +{ + struct qcom_pas_tee_private *data =3D dev_get_drvdata(dev); + struct tee_ioctl_invoke_arg inv_arg =3D { + .func =3D TA_QCOM_PAS_SHUTDOWN, + .session =3D data->session_id, + .num_params =3D TEE_NUM_PARAMS + }; + struct tee_param param[4] =3D { + [0] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT, + .u.value.a =3D pas_id + } + }; + int ret; + + ret =3D tee_client_invoke_func(data->ctx, &inv_arg, param); + if (ret < 0 || inv_arg.ret !=3D 0) { + dev_err(dev, "PAS shutdown failed, pas_id: %d, ret: %d, err: 0x%x\n", + pas_id, ret, inv_arg.ret); + return ret ?: -EINVAL; + } + + return ret; +} + +static void qcom_pas_tee_metadata_release(struct device *dev, + struct qcom_pas_context *ctx) +{ + struct tee_shm *mdata_shm =3D ctx->ptr; + + tee_shm_free(mdata_shm); + ctx->ptr =3D NULL; +} + +static struct qcom_pas_ops qcom_pas_ops_tee =3D { + .drv_name =3D "qcom-pas-tee", + .supported =3D qcom_pas_tee_supported, + .init_image =3D qcom_pas_tee_init_image, + .mem_setup =3D qcom_pas_tee_mem_setup, + .get_rsc_table =3D qcom_pas_tee_get_rsc_table, + .auth_and_reset =3D qcom_pas_tee_auth_and_reset, + .prepare_and_auth_reset =3D qcom_pas_tee_prepare_and_auth_reset, + .set_remote_state =3D qcom_pas_tee_set_remote_state, + .shutdown =3D qcom_pas_tee_shutdown, + .metadata_release =3D qcom_pas_tee_metadata_release, +}; + +static int optee_ctx_match(struct tee_ioctl_version_data *ver, const void = *data) +{ + return ver->impl_id =3D=3D TEE_IMPL_ID_OPTEE; +} + +static int qcom_pas_tee_probe(struct tee_client_device *pas_dev) +{ + struct device *dev =3D &pas_dev->dev; + struct qcom_pas_tee_private *data; + struct tee_ioctl_open_session_arg sess_arg =3D { + .clnt_login =3D TEE_IOCTL_LOGIN_REE_KERNEL + }; + int ret; + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->ctx =3D tee_client_open_context(NULL, optee_ctx_match, NULL, NULL); + if (IS_ERR(data->ctx)) + return -ENODEV; + + export_uuid(sess_arg.uuid, &pas_dev->id.uuid); + ret =3D tee_client_open_session(data->ctx, &sess_arg, NULL); + if (ret < 0 || sess_arg.ret !=3D 0) { + dev_err(dev, "tee_client_open_session failed, ret: %d, err: 0x%x\n", + ret, sess_arg.ret); + tee_client_close_context(data->ctx); + return ret ?: -EINVAL; + } + + data->session_id =3D sess_arg.session; + dev_set_drvdata(dev, data); + qcom_pas_ops_tee.dev =3D dev; + qcom_pas_ops_register(&qcom_pas_ops_tee); + + return ret; +} + +static void qcom_pas_tee_remove(struct tee_client_device *pas_dev) +{ + struct device *dev =3D &pas_dev->dev; + struct qcom_pas_tee_private *data =3D dev_get_drvdata(dev); + + qcom_pas_ops_unregister(); + tee_client_close_session(data->ctx, data->session_id); + tee_client_close_context(data->ctx); +} + +static const struct tee_client_device_id qcom_pas_tee_id_table[] =3D { + {UUID_INIT(0xcff7d191, 0x7ca0, 0x4784, + 0xaf, 0x13, 0x48, 0x22, 0x3b, 0x9a, 0x4f, 0xbe)}, + {} +}; +MODULE_DEVICE_TABLE(tee, qcom_pas_tee_id_table); + +static struct tee_client_driver optee_pas_tee_driver =3D { + .probe =3D qcom_pas_tee_probe, + .remove =3D qcom_pas_tee_remove, + .id_table =3D qcom_pas_tee_id_table, + .driver =3D { + .name =3D "qcom-pas-tee", + }, +}; + +module_tee_client_driver(optee_pas_tee_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Qualcomm PAS TEE driver"); --=20 2.51.0 From nobody Sun May 24 19:33:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A573F36AB54; Fri, 22 May 2026 12:01:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779451286; cv=none; b=D/8uXmKQk3X14DJgNS/+kDOYevAWwKNMeqR7GOyv7HCVD8OUOW5jJHr0E87OpgQbJsQzPX5SeQF7IQXFih2OnREqpku6WulKVIXPQcLddXdbcgnJuV3vGcK9y4uoENBPxHC5dwTsJP+u6vTp+UIi9AoT7aY0Omz/rxdcLBY0Db0= ARC-Message-Signature: i=1; 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b=RZ7Xijj8L5LyNQUz0tIqPFlA2eSfHAuiUbulCW5wxwq0DDS0vi0Mroatwr7PqwKbN XTn7Um5O8zAbP6owkQhqDgyYo4MU3Yej/1N0DMUf0/b+4VdHASYkkUmZhT0bytuZEU BveIB0hfrWZjR6LDKJrl8nszVER7fw0j8b6zuVkY5pgIuQJ/WJa5fRZZbamW/ocTLN F4v/Vvo776E/f7iW+6/w4qIPmpOlUipR5f/dPhKzI5kNLaYL1NStBTUlhPU6/9sL+U t0Rtap1zlWBb9LxjB9mKfzxwuzo4Y25Pc2MM3DZLheEg+I+KpNcFDYc6jrIClK7zPi xO9XEIPUMY0Ow== From: Sumit Garg To: andersson@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg Subject: [PATCH v7 05/15] remoteproc: qcom_q6v5_pas: Switch over to generic PAS TZ APIs Date: Fri, 22 May 2026 17:29:26 +0530 Message-ID: <20260522115936.201208-6-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260522115936.201208-1-sumit.garg@kernel.org> References: <20260522115936.201208-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg Switch qcom_q6v5_pas client driver over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Since qcom_q6v5_pas depends on MDT loader for PAS firmware loading, it has to be switched over to generic PAS APIs in this commit to avoid any build issues. Reviewed-by: Mukesh Ojha Tested-by: Mukesh Ojha # Lemans Tested-by: Vignesh Viswanathan # IPQ= 9650 Signed-off-by: Sumit Garg --- drivers/remoteproc/qcom_q6v5_pas.c | 51 +++++++++++++++-------------- drivers/soc/qcom/mdt_loader.c | 12 +++---- include/linux/soc/qcom/mdt_loader.h | 6 ++-- 3 files changed, 35 insertions(+), 34 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q= 6v5_pas.c index da27d1d3c9da..847249c28c1b 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -118,8 +119,8 @@ struct qcom_pas { struct qcom_rproc_ssr ssr_subdev; struct qcom_sysmon *sysmon; =20 - struct qcom_scm_pas_context *pas_ctx; - struct qcom_scm_pas_context *dtb_pas_ctx; + struct qcom_pas_context *pas_ctx; + struct qcom_pas_context *dtb_pas_ctx; }; =20 static void qcom_pas_segment_dump(struct rproc *rproc, @@ -196,7 +197,7 @@ static int qcom_pas_shutdown_poll_decrypt(struct qcom_p= as *pas) =20 do { msleep(QCOM_PAS_DECRYPT_SHUTDOWN_DELAY_MS); - ret =3D qcom_scm_pas_shutdown(pas->pas_id); + ret =3D qcom_pas_shutdown(pas->pas_id); } while (ret =3D=3D -EINVAL && --retry_num); =20 return ret; @@ -212,9 +213,9 @@ static int qcom_pas_unprepare(struct rproc *rproc) * auth_and_reset() was successful, but in other cases clean it up * here. */ - qcom_scm_pas_metadata_release(pas->pas_ctx); + qcom_pas_metadata_release(pas->pas_ctx); if (pas->dtb_pas_id) - qcom_scm_pas_metadata_release(pas->dtb_pas_ctx); + qcom_pas_metadata_release(pas->dtb_pas_ctx); =20 return 0; } @@ -228,9 +229,9 @@ static int qcom_pas_load(struct rproc *rproc, const str= uct firmware *fw) pas->firmware =3D fw; =20 if (pas->lite_pas_id) - qcom_scm_pas_shutdown(pas->lite_pas_id); + qcom_pas_shutdown(pas->lite_pas_id); if (pas->lite_dtb_pas_id) - qcom_scm_pas_shutdown(pas->lite_dtb_pas_id); + qcom_pas_shutdown(pas->lite_dtb_pas_id); =20 if (pas->dtb_pas_id) { ret =3D request_firmware(&pas->dtb_firmware, pas->dtb_firmware_name, pas= ->dev); @@ -250,7 +251,7 @@ static int qcom_pas_load(struct rproc *rproc, const str= uct firmware *fw) return 0; =20 release_dtb_metadata: - qcom_scm_pas_metadata_release(pas->dtb_pas_ctx); + qcom_pas_metadata_release(pas->dtb_pas_ctx); release_firmware(pas->dtb_firmware); =20 return ret; @@ -310,7 +311,7 @@ static int qcom_pas_start(struct rproc *rproc) if (ret) goto disable_px_supply; =20 - ret =3D qcom_scm_pas_prepare_and_auth_reset(pas->dtb_pas_ctx); + ret =3D qcom_pas_prepare_and_auth_reset(pas->dtb_pas_ctx); if (ret) { dev_err(pas->dev, "failed to authenticate dtb image and release reset\n"); @@ -329,7 +330,7 @@ static int qcom_pas_start(struct rproc *rproc) if (ret) goto release_pas_metadata; =20 - ret =3D qcom_scm_pas_prepare_and_auth_reset(pas->pas_ctx); + ret =3D qcom_pas_prepare_and_auth_reset(pas->pas_ctx); if (ret) { dev_err(pas->dev, "failed to authenticate image and release reset\n"); @@ -339,13 +340,13 @@ static int qcom_pas_start(struct rproc *rproc) ret =3D qcom_q6v5_wait_for_start(&pas->q6v5, msecs_to_jiffies(5000)); if (ret =3D=3D -ETIMEDOUT) { dev_err(pas->dev, "start timed out\n"); - qcom_scm_pas_shutdown(pas->pas_id); + qcom_pas_shutdown(pas->pas_id); goto unmap_carveout; } =20 - qcom_scm_pas_metadata_release(pas->pas_ctx); + qcom_pas_metadata_release(pas->pas_ctx); if (pas->dtb_pas_id) - qcom_scm_pas_metadata_release(pas->dtb_pas_ctx); + qcom_pas_metadata_release(pas->dtb_pas_ctx); =20 /* firmware is used to pass reference from qcom_pas_start(), drop it now = */ pas->firmware =3D NULL; @@ -355,9 +356,9 @@ static int qcom_pas_start(struct rproc *rproc) unmap_carveout: qcom_pas_unmap_carveout(rproc, pas->mem_phys, pas->mem_size); release_pas_metadata: - qcom_scm_pas_metadata_release(pas->pas_ctx); + qcom_pas_metadata_release(pas->pas_ctx); if (pas->dtb_pas_id) - qcom_scm_pas_metadata_release(pas->dtb_pas_ctx); + qcom_pas_metadata_release(pas->dtb_pas_ctx); =20 unmap_dtb_carveout: if (pas->dtb_pas_id) @@ -406,7 +407,7 @@ static int qcom_pas_stop(struct rproc *rproc) if (ret =3D=3D -ETIMEDOUT) dev_err(pas->dev, "timed out on wait\n"); =20 - ret =3D qcom_scm_pas_shutdown(pas->pas_id); + ret =3D qcom_pas_shutdown(pas->pas_id); if (ret && pas->decrypt_shutdown) ret =3D qcom_pas_shutdown_poll_decrypt(pas); =20 @@ -414,7 +415,7 @@ static int qcom_pas_stop(struct rproc *rproc) dev_err(pas->dev, "failed to shutdown: %d\n", ret); =20 if (pas->dtb_pas_id) { - ret =3D qcom_scm_pas_shutdown(pas->dtb_pas_id); + ret =3D qcom_pas_shutdown(pas->dtb_pas_id); if (ret) dev_err(pas->dev, "failed to shutdown dtb: %d\n", ret); =20 @@ -484,11 +485,11 @@ static int qcom_pas_parse_firmware(struct rproc *rpro= c, const struct firmware *f * * Here, we call rproc_elf_load_rsc_table() to check firmware binary has = resources * or not and if it is not having then we pass NULL and zero as input res= ource - * table pointer and size respectively to the argument of qcom_scm_pas_ge= t_rsc_table() + * table pointer and size respectively to the argument of qcom_pas_get_rs= c_table() * and this is even true for Qualcomm remote processor who does follow re= moteproc * framework. */ - output_rt =3D qcom_scm_pas_get_rsc_table(pas->pas_ctx, table, table_sz, &= output_rt_size); + output_rt =3D qcom_pas_get_rsc_table(pas->pas_ctx, table, table_sz, &outp= ut_rt_size); ret =3D IS_ERR(output_rt) ? PTR_ERR(output_rt) : 0; if (ret) { dev_err(pas->dev, "Error in getting resource table: %d\n", ret); @@ -746,7 +747,7 @@ static int qcom_pas_probe(struct platform_device *pdev) if (!desc) return -EINVAL; =20 - if (!qcom_scm_is_available()) + if (!qcom_pas_is_available()) return -EPROBE_DEFER; =20 fw_name =3D desc->firmware_name; @@ -838,16 +839,16 @@ static int qcom_pas_probe(struct platform_device *pde= v) =20 qcom_add_ssr_subdev(rproc, &pas->ssr_subdev, desc->ssr_name); =20 - pas->pas_ctx =3D devm_qcom_scm_pas_context_alloc(pas->dev, pas->pas_id, - pas->mem_phys, pas->mem_size); + pas->pas_ctx =3D devm_qcom_pas_context_alloc(pas->dev, pas->pas_id, + pas->mem_phys, pas->mem_size); if (IS_ERR(pas->pas_ctx)) { ret =3D PTR_ERR(pas->pas_ctx); goto remove_ssr_sysmon; } =20 - pas->dtb_pas_ctx =3D devm_qcom_scm_pas_context_alloc(pas->dev, pas->dtb_p= as_id, - pas->dtb_mem_phys, - pas->dtb_mem_size); + pas->dtb_pas_ctx =3D devm_qcom_pas_context_alloc(pas->dev, pas->dtb_pas_i= d, + pas->dtb_mem_phys, + pas->dtb_mem_size); if (IS_ERR(pas->dtb_pas_ctx)) { ret =3D PTR_ERR(pas->dtb_pas_ctx); goto remove_ssr_sysmon; diff --git a/drivers/soc/qcom/mdt_loader.c b/drivers/soc/qcom/mdt_loader.c index c004d444d698..137992456b71 100644 --- a/drivers/soc/qcom/mdt_loader.c +++ b/drivers/soc/qcom/mdt_loader.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include @@ -229,7 +229,7 @@ EXPORT_SYMBOL_GPL(qcom_mdt_read_metadata); =20 static int __qcom_mdt_pas_init(struct device *dev, const struct firmware *= fw, const char *fw_name, int pas_id, phys_addr_t mem_phys, - struct qcom_scm_pas_context *ctx) + struct qcom_pas_context *ctx) { const struct elf32_phdr *phdrs; const struct elf32_phdr *phdr; @@ -271,7 +271,7 @@ static int __qcom_mdt_pas_init(struct device *dev, cons= t struct firmware *fw, goto out; } =20 - ret =3D qcom_scm_pas_init_image(pas_id, metadata, metadata_len, ctx); + ret =3D qcom_pas_init_image(pas_id, metadata, metadata_len, ctx); kfree(metadata); if (ret) { /* Invalid firmware metadata */ @@ -280,7 +280,7 @@ static int __qcom_mdt_pas_init(struct device *dev, cons= t struct firmware *fw, } =20 if (relocate) { - ret =3D qcom_scm_pas_mem_setup(pas_id, mem_phys, max_addr - min_addr); + ret =3D qcom_pas_mem_setup(pas_id, mem_phys, max_addr - min_addr); if (ret) { /* Unable to set up relocation */ dev_err(dev, "error %d setting up firmware %s\n", ret, fw_name); @@ -472,7 +472,7 @@ EXPORT_SYMBOL_GPL(qcom_mdt_load); * firmware segments (e.g., .bXX files). Authentication of the segments do= ne * by a separate call. * - * The PAS context must be initialized using qcom_scm_pas_context_init() + * The PAS context must be initialized using devm_qcom_pas_context_alloc() * prior to invoking this function. * * @ctx: Pointer to the PAS (Peripheral Authentication Service) con= text @@ -483,7 +483,7 @@ EXPORT_SYMBOL_GPL(qcom_mdt_load); * * Return: 0 on success or a negative error code on failure. */ -int qcom_mdt_pas_load(struct qcom_scm_pas_context *ctx, const struct firmw= are *fw, +int qcom_mdt_pas_load(struct qcom_pas_context *ctx, const struct firmware = *fw, const char *firmware, void *mem_region, phys_addr_t *reloc_base) { int ret; diff --git a/include/linux/soc/qcom/mdt_loader.h b/include/linux/soc/qcom/m= dt_loader.h index 82372e0db0a1..142409555425 100644 --- a/include/linux/soc/qcom/mdt_loader.h +++ b/include/linux/soc/qcom/mdt_loader.h @@ -10,7 +10,7 @@ =20 struct device; struct firmware; -struct qcom_scm_pas_context; +struct qcom_pas_context; =20 #if IS_ENABLED(CONFIG_QCOM_MDT_LOADER) =20 @@ -20,7 +20,7 @@ int qcom_mdt_load(struct device *dev, const struct firmwa= re *fw, phys_addr_t mem_phys, size_t mem_size, phys_addr_t *reloc_base); =20 -int qcom_mdt_pas_load(struct qcom_scm_pas_context *ctx, const struct firmw= are *fw, +int qcom_mdt_pas_load(struct qcom_pas_context *ctx, const struct firmware = *fw, const char *firmware, void *mem_region, phys_addr_t *reloc_base); =20 int qcom_mdt_load_no_init(struct device *dev, const struct firmware *fw, @@ -45,7 +45,7 @@ static inline int qcom_mdt_load(struct device *dev, const= struct firmware *fw, return -ENODEV; } =20 -static inline int qcom_mdt_pas_load(struct qcom_scm_pas_context *ctx, +static inline int qcom_mdt_pas_load(struct qcom_pas_context *ctx, const struct firmware *fw, const char *firmware, void *mem_region, phys_addr_t *reloc_base) { --=20 2.51.0 From nobody Sun May 24 19:33:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BA0133ADB3; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HYfezcDA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E8D6C1F000E9; Fri, 22 May 2026 12:01:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779451300; bh=Gis5FlnsjXweQNyiZ8MplDGZbBjtOxZAnvE3+VBYhs0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=HYfezcDAXQqKZTL9OY7M7WX60dliyZ9J9e4yVCAlbfrrGl79CT4GnxXBVWuPbeFfb vBZ1kw4X7xkRN5KfrGCd4jRn4UzlhKib1x4S7M1Bu51U+GbtIzxlWVRQdn22ijeWvS PETXaR8VoUz5Pk0g8KhQXKzkHqIXbrEn/fnVXIcGN6TA/fr/BVGjmVvVO+A7F31NNh awxpvhHiIU5frXKwPoZRaAze4vgPigqAIz/tYIYhQd+3CVzL2abxqUHkiCggNBZUHd Hz+eHdCB+qb5g6NxZnwdRkTzwKRiWbKsF9B8q+WGufgA0n7+gPO36Ck9oqaQ9/H63Z 0E968TrbhLagQ== From: Sumit Garg To: andersson@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg Subject: [PATCH v7 06/15] remoteproc: qcom_q6v5_mss: Switch to generic PAS TZ APIs Date: Fri, 22 May 2026 17:29:27 +0530 Message-ID: <20260522115936.201208-7-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260522115936.201208-1-sumit.garg@kernel.org> References: <20260522115936.201208-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg Switch qcom_q6v5_mss client driver over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Reviewed-by: Mukesh Ojha Tested-by: Mukesh Ojha # Lemans Signed-off-by: Sumit Garg --- drivers/remoteproc/qcom_q6v5_mss.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q= 6v5_mss.c index ae78f5c7c1b6..96888007faa8 100644 --- a/drivers/remoteproc/qcom_q6v5_mss.c +++ b/drivers/remoteproc/qcom_q6v5_mss.c @@ -34,6 +34,7 @@ #include "qcom_pil_info.h" #include "qcom_q6v5.h" =20 +#include #include =20 #define MPSS_CRASH_REASON_SMEM 421 @@ -1480,7 +1481,7 @@ static int q6v5_mpss_load(struct q6v5 *qproc) } =20 if (qproc->need_pas_mem_setup) { - ret =3D qcom_scm_pas_mem_setup(MPSS_PAS_ID, qproc->mpss_phys, qproc->mps= s_size); + ret =3D qcom_pas_mem_setup(MPSS_PAS_ID, qproc->mpss_phys, qproc->mpss_si= ze); if (ret) { dev_err(qproc->dev, "setting up mpss memory failed: %d\n", ret); @@ -2077,7 +2078,7 @@ static int q6v5_probe(struct platform_device *pdev) if (!desc) return -EINVAL; =20 - if (desc->need_mem_protection && !qcom_scm_is_available()) + if (desc->need_mem_protection && !qcom_pas_is_available()) return -EPROBE_DEFER; =20 mba_image =3D desc->hexagon_mba_image; --=20 2.51.0 From nobody Sun May 24 19:33:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59431349CC4; Fri, 22 May 2026 12:01:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779451317; cv=none; b=Cdw4PChrCJqMxULm8K+3QttrqgmXNj3IK0cdIJ5Jij9sVJ0zuy8cfeVrs+awYRoj3Z1ueb+8o4aiOrx+Zel4NY2olREO2m2f76zAc62keg8QFHeS5ZjhQExRaZax69eUBBLLH9Q6jkw3lLACM8kKrDIjSqt3eFRpSwv7WanLKbE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779451317; c=relaxed/simple; bh=2y1dLYSN9I5MyCre0kGkJeNgpsjPOlU7guTiFjyNhvA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=f9thv7wsKLxCYUvh2/nZtxAqi4HAl0zGqr3me7f6io9T1ftLv/FiyjHdlyjffr1BcQfZUh7RcEOe6Oe0CjtFHrZoJ2OhZ+xVoCWITnb5BsjeB3zPa4egyuKu5sOiIiP2MyVi7ce6RU9PW/rWu2EeChu9RZbkxcoHvWgIOPV4plc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=aTlfXNtj; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="aTlfXNtj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B829D1F00A3D; Fri, 22 May 2026 12:01:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779451316; bh=wKsgbpUVkZO9zW0In0sWJicjFDTgo4Mlcppw/kDfVs0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=aTlfXNtjIaj9o47TEuehFmkjsImumavGXNOVarCCDwfW1zckYzwFtay1Pr9xTRIaY r/mUIKCevJ2zP5F82g5QMArBC7/4raoHLtFBKXxnI9iULe8/KQH/bWv1ixFbGiPnP/ KtbDZzolQcg+JvqiH7coA7VGk4G+hOdlyIuRzujaVZmHy8yG02bv7VxhweBvPKzQsE 5yYqTzOLTt0PVrNva+KIxrcz87+KvVwvw/oPMqXBN+Nr7aYS9LblbJfAIrRDQ43iLU YMGeU/o6llXpPT36P3IUA5538wBBVv5l+ioAOa0Z46WTTc7CdUW4mQWFv++P6WoFM0 nfJlxrsE34Ufw== From: Sumit Garg To: andersson@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg Subject: [PATCH v7 07/15] remoteproc: qcom_wcnss: Switch to generic PAS TZ APIs Date: Fri, 22 May 2026 17:29:28 +0530 Message-ID: <20260522115936.201208-8-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260522115936.201208-1-sumit.garg@kernel.org> References: <20260522115936.201208-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg Switch qcom_wcnss client driver over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Reviewed-by: Mukesh Ojha Tested-by: Mukesh Ojha # Lemans Signed-off-by: Sumit Garg --- drivers/remoteproc/qcom_wcnss.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/remoteproc/qcom_wcnss.c b/drivers/remoteproc/qcom_wcns= s.c index 4add9037dbd5..0dbdd18ab3dd 100644 --- a/drivers/remoteproc/qcom_wcnss.c +++ b/drivers/remoteproc/qcom_wcnss.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include @@ -257,7 +257,7 @@ static int wcnss_start(struct rproc *rproc) wcnss_indicate_nv_download(wcnss); wcnss_configure_iris(wcnss); =20 - ret =3D qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID); + ret =3D qcom_pas_auth_and_reset(WCNSS_PAS_ID); if (ret) { dev_err(wcnss->dev, "failed to authenticate image and release reset\n"); @@ -269,7 +269,7 @@ static int wcnss_start(struct rproc *rproc) if (wcnss->ready_irq > 0 && ret =3D=3D 0) { /* We have a ready_irq, but it didn't fire in time. */ dev_err(wcnss->dev, "start timed out\n"); - qcom_scm_pas_shutdown(WCNSS_PAS_ID); + qcom_pas_shutdown(WCNSS_PAS_ID); ret =3D -ETIMEDOUT; goto disable_iris; } @@ -311,7 +311,7 @@ static int wcnss_stop(struct rproc *rproc) 0); } =20 - ret =3D qcom_scm_pas_shutdown(WCNSS_PAS_ID); + ret =3D qcom_pas_shutdown(WCNSS_PAS_ID); if (ret) dev_err(wcnss->dev, "failed to shutdown: %d\n", ret); =20 @@ -557,10 +557,10 @@ static int wcnss_probe(struct platform_device *pdev) =20 data =3D of_device_get_match_data(&pdev->dev); =20 - if (!qcom_scm_is_available()) + if (!qcom_pas_is_available()) return -EPROBE_DEFER; =20 - if (!qcom_scm_pas_supported(WCNSS_PAS_ID)) { + if (!qcom_pas_supported(WCNSS_PAS_ID)) { dev_err(&pdev->dev, "PAS is not available for WCNSS\n"); return -ENXIO; } --=20 2.51.0 From nobody Sun May 24 19:33:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35BD6369990; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PPVe/AJE" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E4D101F00A3E; Fri, 22 May 2026 12:01:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779451332; bh=Z6uy6Kioni3gaYTMtj9KN4Qx170IjsLwGLPu9IFKsDA=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=PPVe/AJEUwumHJ0Yd71Phu5zgHX8psmZpYH73sqmPVgHok1KmsUBfKJtzZh1Wpmf8 cqH6sSCp008OdQJ7KKqjss97TH2z6yE6I4sJRsAExipFiXlTPGFS1FUnw7xPK4yLMs SPJEmyWWOw/8IEMVoE/eZqpJ+GCrYtmlG9kDhRtoigOXhI0rHbTGO76CzCAV/5dW7k pdWEzaa7pQYD7rDYSPakyb5WeESkuYpPOYcZKzYJ4yN2cjfivWSv7X0UKqQK1dibb3 L2QLqe6PZoojO1cb8NBTm50QxOj403JEOq393OM/NPxMHyKeRFzk5M9v1deTNhrwi6 ilYCgspCiDYeA== From: Sumit Garg To: andersson@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg Subject: [PATCH v7 08/15] remoteproc: qcom: Select QCOM_PAS generic service Date: Fri, 22 May 2026 17:29:29 +0530 Message-ID: <20260522115936.201208-9-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260522115936.201208-1-sumit.garg@kernel.org> References: <20260522115936.201208-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg Select PAS generic service driver to enable support for multiple PAS backends like OP-TEE in addition to SCM. Tested-by: Mukesh Ojha # Lemans Tested-by: Vignesh Viswanathan # IPQ= 9650 Signed-off-by: Sumit Garg --- drivers/remoteproc/Kconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index ee54436fea5a..9a6ca30e1481 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -210,6 +210,7 @@ config QCOM_Q6V5_MSS select QCOM_Q6V5_COMMON select QCOM_RPROC_COMMON select QCOM_SCM + select QCOM_PAS help Say y here to support the Qualcomm self-authenticating modem subsystem based on Hexagon V5. The TrustZone based system is @@ -230,6 +231,7 @@ config QCOM_Q6V5_PAS select QCOM_Q6V5_COMMON select QCOM_RPROC_COMMON select QCOM_SCM + select QCOM_PAS help Say y here to support the TrustZone based Peripheral Image Loader for the Qualcomm remote processors. This is commonly used to control @@ -282,7 +284,7 @@ config QCOM_WCNSS_PIL select QCOM_MDT_LOADER select QCOM_PIL_INFO select QCOM_RPROC_COMMON - select QCOM_SCM + select QCOM_PAS help Say y here to support the Peripheral Image Loader for loading WCNSS firmware and boot the core on e.g. MSM8974, MSM8916. The firmware is --=20 2.51.0 From nobody Sun May 24 19:33:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CA9D371053; Fri, 22 May 2026 12:02:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779451350; cv=none; b=YWq3/X72/3GcnQaFc/49qMCS7yH2irP3fDa4AXH0uZeUAtcU+Ht2GyN1ylZ+ggV2gudvhaAG359oib7dpmObrFiFrrF5pRnzT4YvrkIc1Xcc6OgjKCOwJQpAXO3+5fiPRNvAVTfe/csRwqi56D3K5Le/WWFnsq5ynUUIzwUlZyI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779451350; c=relaxed/simple; bh=MQ04LvOdFtPiYRe2pIYqNHIMNscNznxQvxkIS8rauvE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bEmj/CPvHUVw0KBbu8Ye8BZIw5ZEFJfvyO0PCgS85w49X1w2t8+DmnzhVCLdGK34uUbptQr9PWLIXP8r8uuK1iAIu8kZJ9F39URZi7kilcMTbiW1vfZiiqIK7ic8SFEvo432qRkRLkAU75Qh8jB7kyCDMPilBbh6UFiWAcxc7iA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jlaA9RLg; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jlaA9RLg" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8CA2A1F000E9; Fri, 22 May 2026 12:02:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779451349; bh=zjXwJqwWyv3Rk5OaDq24BXThTX1dvi6g0LZf0i73ehs=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=jlaA9RLg2KXb1lnRiobJ881MP8Y2UNeRCWFUX0gwy4AnrNaD/nz2R6KKoz/cRa4b4 sfMDPMztQzWar2GvNGrzLSwudmXUIiqSPSeJRSbcinG3ApNpGbjPU9r7CpdKjg+Qbx Wx/NgbEEmmqS4MMF2QZ93tkYMxQ3LOu0uVzpAAl8R72SYg5Hq/mkWRiaYh8eXHWDzn qq4H2TuzUS/C0CGq0FMg7n5BZmBwD2us082jEeJbPHBcEcd22BXpfKUrhhw67Oi7R1 iLdfL0e+V+BeGWOQwwk4ufhTnk4rSULL/2whMOgt29ba8TpHQB54uDLNtCBQsc341s Nuc5k8pdUvIxw== From: Sumit Garg To: andersson@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg , Dmitry Baryshkov Subject: [PATCH v7 09/15] drm/msm: Switch to generic PAS TZ APIs Date: Fri, 22 May 2026 17:29:30 +0530 Message-ID: <20260522115936.201208-10-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260522115936.201208-1-sumit.garg@kernel.org> References: <20260522115936.201208-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg Switch drm/msm client drivers over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Acked-by: Dmitry Baryshkov Reviewed-by: Mukesh Ojha Tested-by: Mukesh Ojha # Lemans Signed-off-by: Sumit Garg --- drivers/gpu/drm/msm/Kconfig | 1 + drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++-- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 11 ++++++----- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index 250246f81ea9..09469d56513b 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -21,6 +21,7 @@ config DRM_MSM select SHMEM select TMPFS select QCOM_SCM + select QCOM_PAS select QCOM_UBWC_CONFIG select WANT_DEV_COREDUMP select SND_SOC_HDMI_CODEC if SND_SOC diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a5xx_gpu.c index 79acae11154a..b556da823897 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include #include @@ -653,7 +653,7 @@ static int a5xx_zap_shader_resume(struct msm_gpu *gpu) if (adreno_is_a506(adreno_gpu)) return 0; =20 - ret =3D qcom_scm_set_remote_state(SCM_GPU_ZAP_SHADER_RESUME, GPU_PAS_ID); + ret =3D qcom_pas_set_remote_state(SCM_GPU_ZAP_SHADER_RESUME, GPU_PAS_ID); if (ret) DRM_ERROR("%s: zap-shader resume failed: %d\n", gpu->name, ret); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/= adreno/adreno_gpu.c index 66f80f2d12f9..6d68edf0578c 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -8,6 +8,7 @@ =20 #include #include +#include #include #include #include @@ -146,10 +147,10 @@ static int zap_shader_load_mdt(struct msm_gpu *gpu, c= onst char *fwname, goto out; =20 /* Send the image to the secure world */ - ret =3D qcom_scm_pas_auth_and_reset(pasid); + ret =3D qcom_pas_auth_and_reset(pasid); =20 /* - * If the scm call returns -EOPNOTSUPP we assume that this target + * If the pas call returns -EOPNOTSUPP we assume that this target * doesn't need/support the zap shader so quietly fail */ if (ret =3D=3D -EOPNOTSUPP) @@ -175,9 +176,9 @@ int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pas= id) if (!zap_available) return -ENODEV; =20 - /* We need SCM to be able to load the firmware */ - if (!qcom_scm_is_available()) { - DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n"); + /* We need PAS to be able to load the firmware */ + if (!qcom_pas_is_available()) { + DRM_DEV_ERROR(&pdev->dev, "Qcom PAS is not available\n"); return -EPROBE_DEFER; } =20 --=20 2.51.0 From nobody Sun May 24 19:33:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E85C6335BBB; Fri, 22 May 2026 12:02:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779451366; cv=none; b=luqsyZXZ4vUhjyMuufbk8axwe8pDGIfJ50Rpcbqd3jIcjZxgbiP0FpiqAdgSXqd39X2o2YuG15XahvwzCgr1tRDrchagVLZ0fwFSCaRZ3R/JM35wF+/T+Ng0iXRhZBvlnzl/jTUIZzKQP/KT6x+d1ipTtdATvK8u0Hs/kzSITYs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779451366; c=relaxed/simple; bh=A/MOY2Fpnbj5Gd4jiyAsP5rZ2YFti7UrddGsHyaBWZk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LY3043uN29VP9h+NjmX14I7v5S96JmAKhki/ofjz24tdgwd9ISC/4PLNdA++5QgAFxhCEfwyDA9EoxA8+/4kPmZgmg09Nl5MNLz/As+N1Jao49lRlu5yImQ5ocn7aqeink4b5odBywa6qZ6QtoAdXuJTbt2fBr0NqMkOCPbo2B8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QTkQVODR; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QTkQVODR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D63D51F00A3D; Fri, 22 May 2026 12:02:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779451364; bh=MHDG7IjS9HKb3a8veRwfvhTuNDO7QoZE87yhiyX9F8E=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=QTkQVODR9TTpcg9O5q760cfPCZJ13+h8v9188rS08e7SHonObPNxOcX3UfuSc7Qlc lA5VsF/mnAq/ClLCIyX303HQXKWdSZi/94aTld5FeQuJqyCndgkawqbIzeoFpX2sjE TYguFFzwiohedLDGq6zuFrAAJfXkRUuzNdxL9urLFPJ0W8G6toEbysLzLdZXQr+CJa mDxsxuOs9LH8Mzu3Gt+LA4Tp0379hTJLvS22Mptd+92OEkGv7/6HgIndu3QR4LzQzo yOb0sP4D6gqR70r7oO6D5BhqfN5iVd2AXdXE8AgeMiPuG1qVwAG3A6Ibd9SnbHyz1L jRVI8vgAv8daw== From: Sumit Garg To: andersson@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg Subject: [PATCH v7 10/15] media: qcom: Switch to generic PAS TZ APIs Date: Fri, 22 May 2026 17:29:31 +0530 Message-ID: <20260522115936.201208-11-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260522115936.201208-1-sumit.garg@kernel.org> References: <20260522115936.201208-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg Switch qcom media client drivers over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Reviewed-by: Mukesh Ojha Tested-by: Mukesh Ojha # Lemans Signed-off-by: Sumit Garg --- drivers/media/platform/qcom/iris/Kconfig | 25 ++++++++++--------- .../media/platform/qcom/iris/iris_firmware.c | 9 ++++--- drivers/media/platform/qcom/venus/Kconfig | 1 + drivers/media/platform/qcom/venus/firmware.c | 11 ++++---- 4 files changed, 25 insertions(+), 21 deletions(-) diff --git a/drivers/media/platform/qcom/iris/Kconfig b/drivers/media/platf= orm/qcom/iris/Kconfig index 3c803a05305a..f54b759c18aa 100644 --- a/drivers/media/platform/qcom/iris/Kconfig +++ b/drivers/media/platform/qcom/iris/Kconfig @@ -1,13 +1,14 @@ config VIDEO_QCOM_IRIS - tristate "Qualcomm iris V4L2 decoder driver" - depends on VIDEO_DEV - depends on ARCH_QCOM || COMPILE_TEST - select V4L2_MEM2MEM_DEV - select QCOM_MDT_LOADER if ARCH_QCOM - select QCOM_SCM - select VIDEOBUF2_DMA_CONTIG - help - This is a V4L2 driver for Qualcomm iris video accelerator - hardware. It accelerates decoding operations on various - Qualcomm SoCs. - To compile this driver as a module choose m here. + tristate "Qualcomm iris V4L2 decoder driver" + depends on VIDEO_DEV + depends on ARCH_QCOM || COMPILE_TEST + select V4L2_MEM2MEM_DEV + select QCOM_MDT_LOADER if ARCH_QCOM + select QCOM_SCM + select QCOM_PAS + select VIDEOBUF2_DMA_CONTIG + help + This is a V4L2 driver for Qualcomm iris video accelerator + hardware. It accelerates decoding operations on various + Qualcomm SoCs. + To compile this driver as a module choose m here. diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/med= ia/platform/qcom/iris/iris_firmware.c index 5f408024e967..b3c5281aea91 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -4,6 +4,7 @@ */ =20 #include +#include #include #include #include @@ -79,7 +80,7 @@ int iris_fw_load(struct iris_core *core) return -ENOMEM; } =20 - ret =3D qcom_scm_pas_auth_and_reset(core->iris_platform_data->pas_id); + ret =3D qcom_pas_auth_and_reset(core->iris_platform_data->pas_id); if (ret) { dev_err(core->dev, "auth and reset failed: %d\n", ret); return ret; @@ -93,7 +94,7 @@ int iris_fw_load(struct iris_core *core) cp_config->cp_nonpixel_size); if (ret) { dev_err(core->dev, "qcom_scm_mem_protect_video_var failed: %d\n", ret); - qcom_scm_pas_shutdown(core->iris_platform_data->pas_id); + qcom_pas_shutdown(core->iris_platform_data->pas_id); return ret; } } @@ -103,10 +104,10 @@ int iris_fw_load(struct iris_core *core) =20 int iris_fw_unload(struct iris_core *core) { - return qcom_scm_pas_shutdown(core->iris_platform_data->pas_id); + return qcom_pas_shutdown(core->iris_platform_data->pas_id); } =20 int iris_set_hw_state(struct iris_core *core, bool resume) { - return qcom_scm_set_remote_state(resume, 0); + return qcom_pas_set_remote_state(resume, 0); } diff --git a/drivers/media/platform/qcom/venus/Kconfig b/drivers/media/plat= form/qcom/venus/Kconfig index ffb731ecd48c..574172724e8f 100644 --- a/drivers/media/platform/qcom/venus/Kconfig +++ b/drivers/media/platform/qcom/venus/Kconfig @@ -6,6 +6,7 @@ config VIDEO_QCOM_VENUS select OF_DYNAMIC if ARCH_QCOM select QCOM_MDT_LOADER if ARCH_QCOM select QCOM_SCM + select QCOM_PAS select VIDEOBUF2_DMA_CONTIG select V4L2_MEM2MEM_DEV help diff --git a/drivers/media/platform/qcom/venus/firmware.c b/drivers/media/p= latform/qcom/venus/firmware.c index 1de7436713ed..3a38ff985822 100644 --- a/drivers/media/platform/qcom/venus/firmware.c +++ b/drivers/media/platform/qcom/venus/firmware.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -58,7 +59,7 @@ int venus_set_hw_state(struct venus_core *core, bool resu= me) int ret; =20 if (core->use_tz) { - ret =3D qcom_scm_set_remote_state(resume, 0); + ret =3D qcom_pas_set_remote_state(resume, 0); if (resume && ret =3D=3D -EINVAL) ret =3D 0; return ret; @@ -218,7 +219,7 @@ int venus_boot(struct venus_core *core) int ret; =20 if (!IS_ENABLED(CONFIG_QCOM_MDT_LOADER) || - (core->use_tz && !qcom_scm_is_available())) + (core->use_tz && !qcom_pas_is_available())) return -EPROBE_DEFER; =20 ret =3D of_property_read_string_index(dev->of_node, "firmware-name", 0, @@ -236,7 +237,7 @@ int venus_boot(struct venus_core *core) core->fw.mem_phys =3D mem_phys; =20 if (core->use_tz) - ret =3D qcom_scm_pas_auth_and_reset(VENUS_PAS_ID); + ret =3D qcom_pas_auth_and_reset(VENUS_PAS_ID); else ret =3D venus_boot_no_tz(core, mem_phys, mem_size); =20 @@ -259,7 +260,7 @@ int venus_boot(struct venus_core *core) res->cp_nonpixel_start, res->cp_nonpixel_size); if (ret) { - qcom_scm_pas_shutdown(VENUS_PAS_ID); + qcom_pas_shutdown(VENUS_PAS_ID); dev_err(dev, "set virtual address ranges fail (%d)\n", ret); return ret; @@ -274,7 +275,7 @@ int venus_shutdown(struct venus_core *core) int ret; =20 if (core->use_tz) - ret =3D qcom_scm_pas_shutdown(VENUS_PAS_ID); + ret =3D qcom_pas_shutdown(VENUS_PAS_ID); else ret =3D venus_shutdown_no_tz(core); =20 --=20 2.51.0 From nobody Sun May 24 19:33:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F209364047; Fri, 22 May 2026 12:03:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779451381; cv=none; b=NtI1aP/aLialnmiil65rrjmzjz3MXXfr5jN2h+R1Yh3iFC8jNr0g2CFcOZoD2fUzYi0uwnI9/G7ydcJqvw7mbzFcT7Fj49JGjpcSEOpsMGV0uZL5pBxm3QOoEc7H41TMpXJCSOJQhnKEOJcixt/M4yoxuxrdscheip1kP3P2N8k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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charset="utf-8" From: Sumit Garg As per testing the SCM backend just ignores it while OP-TEE makes use of it to for proper book keeping purpose. Reviewed-by: Mukesh Ojha Tested-by: Mukesh Ojha # Lemans Reviewed-by: Vikash Garodia Signed-off-by: Sumit Garg --- drivers/media/platform/qcom/iris/iris_firmware.c | 2 +- drivers/media/platform/qcom/venus/firmware.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/med= ia/platform/qcom/iris/iris_firmware.c index b3c5281aea91..856fa6a79064 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -109,5 +109,5 @@ int iris_fw_unload(struct iris_core *core) =20 int iris_set_hw_state(struct iris_core *core, bool resume) { - return qcom_pas_set_remote_state(resume, 0); + return qcom_pas_set_remote_state(resume, core->iris_platform_data->pas_id= ); } diff --git a/drivers/media/platform/qcom/venus/firmware.c b/drivers/media/p= latform/qcom/venus/firmware.c index 3a38ff985822..3c0727ea137d 100644 --- a/drivers/media/platform/qcom/venus/firmware.c +++ b/drivers/media/platform/qcom/venus/firmware.c @@ -59,7 +59,7 @@ int venus_set_hw_state(struct venus_core *core, bool resu= me) int ret; =20 if (core->use_tz) { - ret =3D qcom_pas_set_remote_state(resume, 0); + ret =3D qcom_pas_set_remote_state(resume, VENUS_PAS_ID); if (resume && ret =3D=3D -EINVAL) ret =3D 0; return ret; --=20 2.51.0 From nobody Sun May 24 19:33:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E1EF376A00; Fri, 22 May 2026 12:03:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779451399; cv=none; b=VGAAJxCdJgZQD8l6wuy5ngqsjT6wKk+se7EbUx9Vgtc9RWvVE0b6UuP4UAFTEQmEXSEFB13tzXosRen7EaV/KjtzaRSXBK7CGPNiLNJI76VeS4BQW17sy+d1p8m1sSUIjsUdPOqJUPYt/qE78QSYbT9CvztkWbzDP1/fjOJ1Y/g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779451399; c=relaxed/simple; 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charset="utf-8" From: Sumit Garg Switch ipa client driver over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Reviewed-by: Alex Elder Signed-off-by: Sumit Garg --- drivers/net/ipa/Kconfig | 2 +- drivers/net/ipa/ipa_main.c | 13 ++++++++----- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/net/ipa/Kconfig b/drivers/net/ipa/Kconfig index 01d219d3760c..a9aff1b7977d 100644 --- a/drivers/net/ipa/Kconfig +++ b/drivers/net/ipa/Kconfig @@ -6,7 +6,7 @@ config QCOM_IPA depends on QCOM_RPROC_COMMON || (QCOM_RPROC_COMMON=3Dn && COMPILE_TEST) depends on QCOM_AOSS_QMP || QCOM_AOSS_QMP=3Dn select QCOM_MDT_LOADER - select QCOM_SCM + select QCOM_PAS select QCOM_QMI_HELPERS help Choose Y or M here to include support for the Qualcomm diff --git a/drivers/net/ipa/ipa_main.c b/drivers/net/ipa/ipa_main.c index 788dd99af2a4..3cd9e44680e9 100644 --- a/drivers/net/ipa/ipa_main.c +++ b/drivers/net/ipa/ipa_main.c @@ -14,7 +14,7 @@ #include #include =20 -#include +#include #include =20 #include "ipa.h" @@ -624,10 +624,13 @@ static int ipa_firmware_load(struct device *dev) } =20 ret =3D qcom_mdt_load(dev, fw, path, IPA_PAS_ID, virt, phys, size, NULL); - if (ret) + if (ret) { dev_err(dev, "error %d loading \"%s\"\n", ret, path); - else if ((ret =3D qcom_scm_pas_auth_and_reset(IPA_PAS_ID))) - dev_err(dev, "error %d authenticating \"%s\"\n", ret, path); + } else { + ret =3D qcom_pas_auth_and_reset(IPA_PAS_ID); + if (ret) + dev_err(dev, "error %d authenticating \"%s\"\n", ret, path); + } =20 memunmap(virt); out_release_firmware: @@ -758,7 +761,7 @@ static enum ipa_firmware_loader ipa_firmware_loader(str= uct device *dev) return IPA_LOADER_INVALID; out_self: /* We need Trust Zone to load firmware; make sure it's available */ - if (qcom_scm_is_available()) + if (qcom_pas_is_available()) return IPA_LOADER_SELF; =20 return IPA_LOADER_DEFER; --=20 2.51.0 From nobody Sun May 24 19:33:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81801369D41; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PBirVbw1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1C4251F000E9; Fri, 22 May 2026 12:03:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779451412; bh=SzmZGhPkbcXgHDehZfZsWRdKMa/+53zBtK7vFqcwR/M=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=PBirVbw1N+cx+pVxLpHObQwJsDkKu+O9qoh2B5vj05THa8d2RUztSMjEfNo4zsiW0 oWFjjcHSUWVhZ0LJ6ivvNmTtNqfyuDLODXIX6diLTjiqC48xwGC1aKBxfWj9uSil/5 saRdxS08H/XjG2v7r36+n+gM52xqpiJXTP++BbnR8wRYyri7Kh6pNSnQsY30nzIPUl J5HNlBXK1Wx2bShG4fXyGSatK6CcY4hoO0OJs+WEJ+u+8DBN/5hsc9BbvgciXk4YC9 VOGBvhUi2VLCisGn84DtB2fa7YAkbxmFBNRPNgg0g2iN6ZPnY4RJIWnOYdn5LRL3B9 qG8hw1GFQ+TiA== From: Sumit Garg To: andersson@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg Subject: [PATCH v7 13/15] wifi: ath12k: Switch to generic PAS TZ APIs Date: Fri, 22 May 2026 17:29:34 +0530 Message-ID: <20260522115936.201208-14-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260522115936.201208-1-sumit.garg@kernel.org> References: <20260522115936.201208-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg Switch ath12k client driver over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Acked-by: Jeff Johnson Signed-off-by: Sumit Garg --- drivers/net/wireless/ath/ath12k/Kconfig | 2 +- drivers/net/wireless/ath/ath12k/ahb.c | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/wireless/ath/ath12k/Kconfig b/drivers/net/wireless= /ath/ath12k/Kconfig index d39c075758bd..2b8b87931330 100644 --- a/drivers/net/wireless/ath/ath12k/Kconfig +++ b/drivers/net/wireless/ath/ath12k/Kconfig @@ -18,7 +18,7 @@ config ATH12K_AHB bool "QTI ath12k AHB support" depends on ATH12K && REMOTEPROC select QCOM_MDT_LOADER - select QCOM_SCM + select QCOM_PAS help Enable support for Ath12k AHB bus chipsets, example IPQ5332. =20 diff --git a/drivers/net/wireless/ath/ath12k/ahb.c b/drivers/net/wireless/a= th/ath12k/ahb.c index 2dcf0a52e4c1..dff7fa7027c5 100644 --- a/drivers/net/wireless/ath/ath12k/ahb.c +++ b/drivers/net/wireless/ath/ath12k/ahb.c @@ -5,7 +5,7 @@ */ =20 #include -#include +#include #include #include #include @@ -420,7 +420,7 @@ static int ath12k_ahb_power_up(struct ath12k_base *ab) =20 if (ab_ahb->scm_auth_enabled) { /* Authenticate FW image using peripheral ID */ - ret =3D qcom_scm_pas_auth_and_reset(pasid); + ret =3D qcom_pas_auth_and_reset(pasid); if (ret) { ath12k_err(ab, "failed to boot the remote processor %d\n", ret); goto err_fw2; @@ -485,10 +485,10 @@ static void ath12k_ahb_power_down(struct ath12k_base = *ab, bool is_suspend) pasid =3D (u32_encode_bits(ab_ahb->userpd_id, ATH12K_USERPD_ID_MASK)) | ATH12K_AHB_UPD_SWID; /* Release the firmware */ - ret =3D qcom_scm_pas_shutdown(pasid); + ret =3D qcom_pas_shutdown(pasid); if (ret) - ath12k_err(ab, "scm pas shutdown failed for userPD%d\n", - ab_ahb->userpd_id); + ath12k_err(ab, "pas shutdown failed for userPD%d: %d\n", + ab_ahb->userpd_id, ret); } } =20 --=20 2.51.0 From nobody Sun May 24 19:33:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54266369D41; Fri, 22 May 2026 12:03:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 22 May 2026 12:03:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779451427; bh=sYX11vTIXcXa/o/s33s/aXKJIJgNQokJvJOCwfyk2Bo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Vlrqi/xtwPj5UifFNuJPtFxYpaPhkisxKELrqZ5QH0AHR+L+c/IGuXeaCBcWS8TFA dEj4dNwknkiME165Z6ZCaH0htJducnAWquvGeeEsjCh+yIo/OwMdoDuMCKDUleQ4ze Jmo5VuTXv52M5cZHGD0ecqQiV02zfO+7OTu9Ua8WTjVyZ0OJhiZP1/mGFvZiaAGX1b cIq30SildH48x/nQR90hsgkjEbWyOqKdgl2h41aL6EtKjb2j+QWrlPCoUY7NZ28d5b zfjDFO2mCLAa6kGyLIgyI9jswXW9PpePKrjB9+l9qfo4quvT+eJMCgRMZ0pdAPvMbR iUDjyahnEfumA== From: Sumit Garg To: andersson@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg Subject: [PATCH v7 14/15] firmware: qcom_scm: Remove SCM PAS wrappers Date: Fri, 22 May 2026 17:29:35 +0530 Message-ID: <20260522115936.201208-15-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260522115936.201208-1-sumit.garg@kernel.org> References: <20260522115936.201208-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg Now since all the Qcom SCM client drivers have been migrated over to generic PAS TZ service, let's drop the exported SCM PAS wrappers. Reviewed-by: Mukesh Ojha Tested-by: Mukesh Ojha # Lemans Tested-by: Vignesh Viswanathan # IPQ= 9650 Signed-off-by: Sumit Garg --- drivers/firmware/qcom/qcom_scm.c | 143 +++++-------------------- include/linux/firmware/qcom/qcom_scm.h | 29 ----- 2 files changed, 29 insertions(+), 143 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index 7933e55803dc..1deee6aea387 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -553,26 +553,6 @@ static void qcom_scm_set_download_mode(u32 dload_mode) dev_err(__scm->dev, "failed to set download mode: %d\n", ret); } =20 -struct qcom_scm_pas_context *devm_qcom_scm_pas_context_alloc(struct device= *dev, - u32 pas_id, - phys_addr_t mem_phys, - size_t mem_size) -{ - struct qcom_pas_context *ctx; - - ctx =3D devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); - if (!ctx) - return ERR_PTR(-ENOMEM); - - ctx->dev =3D dev; - ctx->pas_id =3D pas_id; - ctx->mem_phys =3D mem_phys; - ctx->mem_size =3D mem_size; - - return (struct qcom_scm_pas_context *)ctx; -} -EXPORT_SYMBOL_GPL(devm_qcom_scm_pas_context_alloc); - static int __qcom_scm_pas_init_image(struct device *dev, u32 pas_id, dma_addr_t mdata_phys, struct qcom_scm_res *res) @@ -630,9 +610,9 @@ static int qcom_scm_pas_prep_and_init_image(struct devi= ce *dev, return ret ? : res.result[0]; } =20 -static int __qcom_scm_pas_init_image2(struct device *dev, u32 pas_id, - const void *metadata, size_t size, - struct qcom_pas_context *ctx) +static int qcom_scm_pas_init_image(struct device *dev, u32 pas_id, + const void *metadata, size_t size, + struct qcom_pas_context *ctx) { struct qcom_scm_res res; dma_addr_t mdata_phys; @@ -672,16 +652,8 @@ static int __qcom_scm_pas_init_image2(struct device *d= ev, u32 pas_id, return ret ? : res.result[0]; } =20 -int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size, - struct qcom_scm_pas_context *ctx) -{ - return __qcom_scm_pas_init_image2(__scm->dev, pas_id, metadata, size, - (struct qcom_pas_context *)ctx); -} -EXPORT_SYMBOL_GPL(qcom_scm_pas_init_image); - -static void __qcom_scm_pas_metadata_release(struct device *dev, - struct qcom_pas_context *ctx) +static void qcom_scm_pas_metadata_release(struct device *dev, + struct qcom_pas_context *ctx) { if (ctx->use_tzmem) qcom_tzmem_free(ctx->ptr); @@ -691,15 +663,8 @@ static void __qcom_scm_pas_metadata_release(struct dev= ice *dev, ctx->ptr =3D NULL; } =20 -void qcom_scm_pas_metadata_release(struct qcom_scm_pas_context *ctx) -{ - __qcom_scm_pas_metadata_release(__scm->dev, - (struct qcom_pas_context *)ctx); -} -EXPORT_SYMBOL_GPL(qcom_scm_pas_metadata_release); - -static int __qcom_scm_pas_mem_setup(struct device *dev, u32 pas_id, - phys_addr_t addr, phys_addr_t size) +static int qcom_scm_pas_mem_setup(struct device *dev, u32 pas_id, + phys_addr_t addr, phys_addr_t size) { int ret; struct qcom_scm_desc desc =3D { @@ -730,12 +695,6 @@ static int __qcom_scm_pas_mem_setup(struct device *dev= , u32 pas_id, return ret ? : res.result[0]; } =20 -int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size) -{ - return __qcom_scm_pas_mem_setup(__scm->dev, pas_id, addr, size); -} -EXPORT_SYMBOL_GPL(qcom_scm_pas_mem_setup); - static void *__qcom_scm_pas_get_rsc_table(struct device *dev, u32 pas_id, void *input_rt_tzm, size_t input_rt_size, @@ -789,11 +748,10 @@ static void *__qcom_scm_pas_get_rsc_table(struct devi= ce *dev, u32 pas_id, return ret ? ERR_PTR(ret) : output_rt_tzm; } =20 -static void *__qcom_scm_pas_get_rsc_table2(struct device *dev, - struct qcom_pas_context *ctx, - void *input_rt, - size_t input_rt_size, - size_t *output_rt_size) +static void *qcom_scm_pas_get_rsc_table(struct device *dev, + struct qcom_pas_context *ctx, + void *input_rt, size_t input_rt_size, + size_t *output_rt_size) { struct resource_table empty_rsc =3D {}; size_t size =3D SZ_16K; @@ -864,19 +822,7 @@ static void *__qcom_scm_pas_get_rsc_table2(struct devi= ce *dev, return ret ? ERR_PTR(ret) : tbl_ptr; } =20 -struct resource_table *qcom_scm_pas_get_rsc_table(struct qcom_scm_pas_cont= ext *ctx, - void *input_rt, - size_t input_rt_size, - size_t *output_rt_size) -{ - return __qcom_scm_pas_get_rsc_table2(__scm->dev, - (struct qcom_pas_context *)ctx, - input_rt, input_rt_size, - output_rt_size); -} -EXPORT_SYMBOL_GPL(qcom_scm_pas_get_rsc_table); - -static int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 pas_id) +static int qcom_scm_pas_auth_and_reset(struct device *dev, u32 pas_id) { int ret; struct qcom_scm_desc desc =3D { @@ -905,14 +851,8 @@ static int __qcom_scm_pas_auth_and_reset(struct device= *dev, u32 pas_id) return ret ? : res.result[0]; } =20 -int qcom_scm_pas_auth_and_reset(u32 pas_id) -{ - return __qcom_scm_pas_auth_and_reset(__scm->dev, pas_id); -} -EXPORT_SYMBOL_GPL(qcom_scm_pas_auth_and_reset); - -static int __qcom_scm_pas_prepare_and_auth_reset(struct device *dev, - struct qcom_pas_context *ctx) +static int qcom_scm_pas_prepare_and_auth_reset(struct device *dev, + struct qcom_pas_context *ctx) { u64 handle; int ret; @@ -923,7 +863,7 @@ static int __qcom_scm_pas_prepare_and_auth_reset(struct= device *dev, * memory region and then invokes a call to TrustZone to authenticate. */ if (!ctx->use_tzmem) - return __qcom_scm_pas_auth_and_reset(dev, ctx->pas_id); + return qcom_scm_pas_auth_and_reset(dev, ctx->pas_id); =20 /* * When Linux runs @ EL2 Linux must create the shmbridge itself and then @@ -933,21 +873,14 @@ static int __qcom_scm_pas_prepare_and_auth_reset(stru= ct device *dev, if (ret) return ret; =20 - ret =3D __qcom_scm_pas_auth_and_reset(dev, ctx->pas_id); + ret =3D qcom_scm_pas_auth_and_reset(dev, ctx->pas_id); qcom_tzmem_shm_bridge_delete(handle); =20 return ret; } =20 -int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_context *ctx) -{ - return __qcom_scm_pas_prepare_and_auth_reset(__scm->dev, - (struct qcom_pas_context *)ctx); -} -EXPORT_SYMBOL_GPL(qcom_scm_pas_prepare_and_auth_reset); - -static int __qcom_scm_pas_set_remote_state(struct device *dev, u32 state, - u32 pas_id) +static int qcom_scm_pas_set_remote_state(struct device *dev, u32 state, + u32 pas_id) { struct qcom_scm_desc desc =3D { .svc =3D QCOM_SCM_SVC_BOOT, @@ -965,13 +898,7 @@ static int __qcom_scm_pas_set_remote_state(struct devi= ce *dev, u32 state, return ret ? : res.result[0]; } =20 -int qcom_scm_set_remote_state(u32 state, u32 id) -{ - return __qcom_scm_pas_set_remote_state(__scm->dev, state, id); -} -EXPORT_SYMBOL_GPL(qcom_scm_set_remote_state); - -static int __qcom_scm_pas_shutdown(struct device *dev, u32 pas_id) +static int qcom_scm_pas_shutdown(struct device *dev, u32 pas_id) { int ret; struct qcom_scm_desc desc =3D { @@ -1000,13 +927,7 @@ static int __qcom_scm_pas_shutdown(struct device *dev= , u32 pas_id) return ret ? : res.result[0]; } =20 -int qcom_scm_pas_shutdown(u32 pas_id) -{ - return __qcom_scm_pas_shutdown(__scm->dev, pas_id); -} -EXPORT_SYMBOL_GPL(qcom_scm_pas_shutdown); - -static bool __qcom_scm_pas_supported(struct device *dev, u32 pas_id) +static bool qcom_scm_pas_supported(struct device *dev, u32 pas_id) { int ret; struct qcom_scm_desc desc =3D { @@ -1027,23 +948,17 @@ static bool __qcom_scm_pas_supported(struct device *= dev, u32 pas_id) return ret ? false : !!res.result[0]; } =20 -bool qcom_scm_pas_supported(u32 pas_id) -{ - return __qcom_scm_pas_supported(__scm->dev, pas_id); -} -EXPORT_SYMBOL_GPL(qcom_scm_pas_supported); - static struct qcom_pas_ops qcom_pas_ops_scm =3D { .drv_name =3D "qcom_scm", - .supported =3D __qcom_scm_pas_supported, - .init_image =3D __qcom_scm_pas_init_image2, - .mem_setup =3D __qcom_scm_pas_mem_setup, - .get_rsc_table =3D __qcom_scm_pas_get_rsc_table2, - .auth_and_reset =3D __qcom_scm_pas_auth_and_reset, - .prepare_and_auth_reset =3D __qcom_scm_pas_prepare_and_auth_reset, - .set_remote_state =3D __qcom_scm_pas_set_remote_state, - .shutdown =3D __qcom_scm_pas_shutdown, - .metadata_release =3D __qcom_scm_pas_metadata_release, + .supported =3D qcom_scm_pas_supported, + .init_image =3D qcom_scm_pas_init_image, + .mem_setup =3D qcom_scm_pas_mem_setup, + .get_rsc_table =3D qcom_scm_pas_get_rsc_table, + .auth_and_reset =3D qcom_scm_pas_auth_and_reset, + .prepare_and_auth_reset =3D qcom_scm_pas_prepare_and_auth_reset, + .set_remote_state =3D qcom_scm_pas_set_remote_state, + .shutdown =3D qcom_scm_pas_shutdown, + .metadata_release =3D qcom_scm_pas_metadata_release, }; =20 /** diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmwar= e/qcom/qcom_scm.h index 5747bd191bf1..a0a6bc0229c4 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -64,35 +64,6 @@ bool qcom_scm_is_available(void); int qcom_scm_set_cold_boot_addr(void *entry); int qcom_scm_set_warm_boot_addr(void *entry); void qcom_scm_cpu_power_down(u32 flags); -int qcom_scm_set_remote_state(u32 state, u32 id); - -struct qcom_scm_pas_context { - struct device *dev; - u32 pas_id; - phys_addr_t mem_phys; - size_t mem_size; - void *ptr; - dma_addr_t phys; - ssize_t size; - bool use_tzmem; -}; - -struct qcom_scm_pas_context *devm_qcom_scm_pas_context_alloc(struct device= *dev, - u32 pas_id, - phys_addr_t mem_phys, - size_t mem_size); -int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size, - struct qcom_scm_pas_context *ctx); -void qcom_scm_pas_metadata_release(struct qcom_scm_pas_context *ctx); -int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size); -int qcom_scm_pas_auth_and_reset(u32 pas_id); -int qcom_scm_pas_shutdown(u32 pas_id); -bool qcom_scm_pas_supported(u32 pas_id); -struct resource_table *qcom_scm_pas_get_rsc_table(struct qcom_scm_pas_cont= ext *ctx, - void *input_rt, size_t input_rt_size, - size_t *output_rt_size); - -int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_context *ctx); =20 int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); --=20 2.51.0 From nobody Sun May 24 19:33:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7993A37BE64; Fri, 22 May 2026 12:04:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779451445; 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a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779451443; bh=WvxxqGuP8bQ7/a21X6z/2vTzkxYwHNKvCYoV2WNH1nw=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Y7m5ymt70pu9vNboppFTfjqhMoHN/WGtjS+ISoh9vdAT37fjHByARwrZv6tg7nuTH YT+bX6BjM5q+p3euvoF5q3tkEYihgyHLQShHogbrqtAhy7JYceiY7Ivsn4CYbS+TJB H0rKTz0nhNge21mLBla/q2MGXGMJMM/zKzCpyUYm1q8dS8UvHbl2VFZXmmgrZkWbV1 uknWfu6bqMoLkY/jFWuTzLGpkWl7DZ86TuLDK2RzaRuX7K1sVDLYe3qKUGipvqNODj WlAeCRrBL+EOHW0cUi2CWIjWG+KmMsakmBktWzVj7vTVZ5uJMiZCV1BEl+7v09Zh39 mmjkFX8wVNfFA== From: Sumit Garg To: andersson@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg Subject: [PATCH v7 15/15] MAINTAINERS: Add maintainer entry for Qualcomm PAS TZ service Date: Fri, 22 May 2026 17:29:36 +0530 Message-ID: <20260522115936.201208-16-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260522115936.201208-1-sumit.garg@kernel.org> References: <20260522115936.201208-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg Add Sumit Garg as the maintainer for the Qualcomm generic Peripheral Authentication Service (PAS) as well as the PAS TEE backend driver. Signed-off-by: Sumit Garg --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2fb1c75afd16..6d3fc5145f0a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22007,6 +22007,15 @@ F: Documentation/devicetree/bindings/media/*qcom* F: drivers/media/platform/qcom F: include/dt-bindings/media/*qcom* =20 +QUALCOMM PAS TZ SERVICE +M: Sumit Garg +L: linux-arm-msm@vger.kernel.org +S: Maintained +F: drivers/firmware/qcom/qcom_pas.c +F: drivers/firmware/qcom/qcom_pas.h +F: drivers/firmware/qcom/qcom_pas_tee.c +F: include/linux/firmware/qcom/qcom_pas.h + QUALCOMM SMB CHARGER DRIVER M: Casey Connolly L: linux-arm-msm@vger.kernel.org --=20 2.51.0