From nobody Sun May 24 18:42:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2B043E0248; Fri, 22 May 2026 10:23:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779445395; cv=none; b=AqQz4nacZecONHzH3JRlI4gGBw6IsTP6V+m0vC1qX8GYsd5xuFZ+nt0vHk4JYBE5DbtH09Z+cz7wFYpQWLvK6rbexWk5/AP4Whl2/k6+efjDM2s/MEYGJcup1oZXUJq3W9ErqA2TtNWzgDWeJaVF1lVtJSh5sojjTgpJ+cB+IbQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779445395; c=relaxed/simple; bh=lJQPr3VxlmXH+zSXA+CLMKPYpgVJGQ116BpPTJu7RyU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=powmY1/kZEpk363HzNnm6Xg9HeqBV0KC8Z3dzzCCsoM54Z/YbwEIKRx8H8urMnnCakp9MTCAq/IiqEddzIgAvenpYkZB6+by1U1bqSg62R+xfpoC659L6D12YnCbRjrAiTC812NMWJyjLhxDvpPhL1F539pVPCOTB6Ldv+KWlxg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=K3R9AZVG; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="K3R9AZVG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 514DB1F00A3E; Fri, 22 May 2026 10:23:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779445385; bh=rrj5Fbj11F+1roWfV5QbQYCe85rfRXNVPie5x7X3ipA=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=K3R9AZVGqKDNaiiuraaDqtPNmYVxhnK5bmAGHVrfHr4Ctyoz0VOV22Bvkfkz1JtHZ CbdqDHxqFOJI67ZT5QtZarXSctZBfPbq2l8fCXdkxg+b/JHL3xupmljz+jqbJaO2xo O4Wbzg9IExE/707AbAzdWjrPHmBL1//MVvR1RoRolaaIkZJq5EVNNKKnkfFD/MdLUO ItIAUf0AE0YiTApBu82jGzcL2mUJfKPBecWwJwZ1jKL5af/KJstCGRb0IjK7DBR54r unA60uLRptaC2aqIedC1K/w0li8VeyjjcQpQr1XsgZLhsmi1j3qGeO3PDKHI0fCFGE 59q2EcSrZ81ag== From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, wsa+renesas@sang-engineering.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH 1/9] pinctrl: renesas: rzg2l: Generalize the power source code Date: Fri, 22 May 2026 13:22:43 +0300 Message-ID: <20260522102251.1723392-2-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522102251.1723392-1-claudiu.beznea@kernel.org> References: <20260522102251.1723392-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The current functions used to get/set the pin power source check the OTHER_POC register, which is specific to the RZ/G3L SoC only. To allow the code to be extended for other power source functionalities (e.g. I3C on RZ/G3S), generalize the functions used to get/set the pin power source. For this, introduce the struct rzg2l_register_masks data structure whose purpose is to store SoC specific register bit masks. The members of this structure are then used in rzg2l_caps_to_pwr_reg() to retrieve the bitmask corresponding to a SoC specific power source capability. The conversion between HW specific power source values and SW specific power source values is now handled through rzg2l_pwr_reg_val_to_ps() and rzg2l_ps_to_pwr_reg_val(). Finally, to keep the code generic, the register update in rzg2l_set_power_source() was changed to a read-modify-write approach to cover all cases. Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 177 +++++++++++++++--------- 1 file changed, 112 insertions(+), 65 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index ac42093fc579..a648d75a2bd2 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -186,6 +186,7 @@ #define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <=3D 1.8V */ #define PVDD_3300 0 /* I/O domain voltage >=3D 3.3V */ +#define PVDD_MASK 0x3 =20 #define PWPR_B0WI BIT(7) /* Bit Write Disable */ #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ @@ -268,6 +269,23 @@ struct rzg2l_register_offsets { u16 other_poc; }; =20 +/** + * struct rzg2l_register_masks - Masks for different RZ/G2L pinctrl functi= onalities + * @other_poc_pvdd1833_oth_awo_poc: PVDD1833_OTH_AWO_POC mask + * @other_poc_pvdd1833_oth_iso_poc: PVDD1833_OTH_ISO_POC mask + * @other_poc_wdtovf_n_poc: WDTOVF_N_POC mask + */ +struct rzg2l_register_masks { + union { + /* RZ/G3L masks */ + struct { + u8 other_poc_pvdd1833_oth_awo_poc; + u8 other_poc_pvdd1833_oth_iso_poc; + u8 other_poc_wdtovf_n_poc; + }; + }; +}; + /** * enum rzg2l_iolh_index - starting indices in IOLH specific arrays * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source @@ -288,6 +306,8 @@ enum rzg2l_iolh_index { /** * struct rzg2l_hwcfg - hardware configuration data structure * @regs: hardware specific register offsets + * @masks: hardware specific masks for various functionalities available in + * the registers described by regs * @iolh_groupa_ua: IOLH group A uA specific values * @iolh_groupb_ua: IOLH group B uA specific values * @iolh_groupc_ua: IOLH group C uA specific values @@ -301,6 +321,7 @@ enum rzg2l_iolh_index { */ struct rzg2l_hwcfg { const struct rzg2l_register_offsets regs; + const struct rzg2l_register_masks masks; u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX]; u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX]; u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX]; @@ -1047,27 +1068,73 @@ static void rzg2l_rmw_pin_config(struct rzg2l_pinct= rl *pctrl, u32 offset, } =20 static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, - u32 caps, u8 *mask) + const struct rzg2l_register_masks *masks, + u32 caps, u16 *offset, u8 *mask) { - if (caps & PIN_CFG_IO_VMC_SD0) - return SD_CH(regs->sd_ch, 0); - if (caps & PIN_CFG_IO_VMC_SD1) - return SD_CH(regs->sd_ch, 1); - if (caps & PIN_CFG_IO_VMC_ETH0) - return ETH_POC(regs->eth_poc, 0); - if (caps & PIN_CFG_IO_VMC_ETH1) - return ETH_POC(regs->eth_poc, 1); - if (caps & PIN_CFG_IO_VMC_QSPI) - return QSPI; + *mask =3D PVDD_MASK; + + if (caps & PIN_CFG_IO_VMC_SD0) { + *offset =3D SD_CH(regs->sd_ch, 0); + return 0; + } + if (caps & PIN_CFG_IO_VMC_SD1) { + *offset =3D SD_CH(regs->sd_ch, 1); + return 0; + } + if (caps & PIN_CFG_IO_VMC_ETH0) { + *offset =3D ETH_POC(regs->eth_poc, 0); + return 0; + } + if (caps & PIN_CFG_IO_VMC_ETH1) { + *offset =3D ETH_POC(regs->eth_poc, 1); + return 0; + } + if (caps & PIN_CFG_IO_VMC_QSPI) { + *offset =3D regs->qspi; + return 0; + } if (caps & PIN_CFG_OTHER_POC_MASK) { + *offset =3D regs->other_poc; if (caps & PIN_CFG_PVDD1833_OTH_AWO_POC) - *mask =3D BIT(0); + *mask =3D masks->other_poc_pvdd1833_oth_awo_poc; else if (caps & PIN_CFG_PVDD1833_OTH_ISO_POC) - *mask =3D BIT(1); + *mask =3D masks->other_poc_pvdd1833_oth_iso_poc; else - *mask =3D BIT(2); + *mask =3D masks->other_poc_wdtovf_n_poc; + return 0; + } =20 - return OTHER_POC; + return -EINVAL; +} + +static int rzg2l_pwr_reg_val_to_ps(u8 val, u32 caps) +{ + switch (val) { + case PVDD_1800: + return 1800; + case PVDD_2500: + return 2500; + case PVDD_3300: + return 3300; + } + + return -EINVAL; +} + +static int rzg2l_ps_to_pwr_reg_val(u8 *val, u32 ps, u32 caps) +{ + switch (ps) { + case 1800: + *val =3D PVDD_1800; + return 0; + case 2500: + if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) + return -EINVAL; + *val =3D PVDD_2500; + return 0; + case 3300: + *val =3D PVDD_3300; + return 0; } =20 return -EINVAL; @@ -1077,76 +1144,51 @@ static int rzg2l_get_power_source(struct rzg2l_pinc= trl *pctrl, u32 pin, u32 caps { const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs =3D &hwcfg->regs; - u8 val, mask; - int pwr_reg; + const struct rzg2l_register_masks *masks =3D &hwcfg->masks; + u8 mask, val; + u16 offset; + int ret; =20 if (caps & PIN_CFG_SOFT_PS) return pctrl->settings[pin].power_source; =20 - pwr_reg =3D rzg2l_caps_to_pwr_reg(regs, caps, &mask); - if (pwr_reg < 0) - return pwr_reg; + ret =3D rzg2l_caps_to_pwr_reg(regs, masks, caps, &offset, &mask); + if (ret) + return ret; =20 - val =3D readb(pctrl->base + pwr_reg); - if (pwr_reg =3D=3D OTHER_POC) - val =3D field_get(mask, val); + val =3D readb(pctrl->base + offset); =20 - switch (val) { - case PVDD_1800: - return 1800; - case PVDD_2500: - return 2500; - case PVDD_3300: - return 3300; - default: - /* Should not happen. */ - return -EINVAL; - } + return rzg2l_pwr_reg_val_to_ps(field_get(mask, val), caps); } =20 static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u3= 2 caps, u32 ps) { const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs =3D &hwcfg->regs; - u8 poc_val, val, mask; - int pwr_reg; + const struct rzg2l_register_masks *masks =3D &hwcfg->masks; + u8 mask, val; + u16 offset; + int ret; =20 if (caps & PIN_CFG_SOFT_PS) { pctrl->settings[pin].power_source =3D ps; return 0; } =20 - switch (ps) { - case 1800: - poc_val =3D PVDD_1800; - break; - case 2500: - if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) - return -EINVAL; - poc_val =3D PVDD_2500; - break; - case 3300: - poc_val =3D PVDD_3300; - break; - default: - return -EINVAL; - } + ret =3D rzg2l_ps_to_pwr_reg_val(&val, ps, caps); + if (ret) + return ret; + + ret =3D rzg2l_caps_to_pwr_reg(regs, masks, caps, &offset, &mask); + if (ret) + return ret; =20 - pwr_reg =3D rzg2l_caps_to_pwr_reg(regs, caps, &mask); - if (pwr_reg < 0) - return pwr_reg; + scoped_guard(raw_spinlock, &pctrl->lock) { + u8 tmp =3D readb(pctrl->base + offset); =20 - if (pwr_reg =3D=3D OTHER_POC) { - scoped_guard(raw_spinlock, &pctrl->lock) { - val =3D readb(pctrl->base + pwr_reg); - if (poc_val) - val |=3D mask; - else - val &=3D ~mask; - writeb(val, pctrl->base + pwr_reg); - } - } else { - writeb(poc_val, pctrl->base + pwr_reg); + tmp &=3D ~mask; + tmp |=3D field_prep(mask, val); + writeb(tmp, pctrl->base + offset); } =20 pctrl->settings[pin].power_source =3D ps; @@ -3795,6 +3837,11 @@ static const struct rzg2l_hwcfg rzg3l_hwcfg =3D { .oen =3D 0x3018, .other_poc =3D OTHER_POC, }, + .masks =3D { + .other_poc_pvdd1833_oth_awo_poc =3D BIT(0), + .other_poc_pvdd1833_oth_iso_poc =3D BIT(1), + .other_poc_wdtovf_n_poc =3D BIT(2), + }, .iolh_groupa_ua =3D { /* 1v8 power source */ [RZG2L_IOLH_IDX_1V8] =3D 2200, 4400, 9000, 10000, --=20 2.43.0 From nobody Sun May 24 18:42:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 398DD3B2FF8; Fri, 22 May 2026 10:23:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779445388; bh=pHdLavqRXkA3FHH3+USq+datVIb7v/EfPh2zTHQx5FI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=e6SDvqlWS20S990IcKWSwkDGeezIULKSZEiw8GgSkby7Q9zx1fK0OjxfZeZLPeUUo RGH0984aKof2gx0VvX9Xgqd+w5WQKICBnfCtTLvV7QJwbisL2WE8YTOTkuCNzVXryK Q11E1p0Pht1+LHAaerhqKMkhHUc6HaqmrtyM1hW4hnX9bZhwE0BqWMK1VhsGEr2i+n Le3u8qaZ7UKJX2332rQDtpXnXs4CY2tizFDYN02MldXRq9t0HES4wZn/bnQXnLs4Ah SHMg8MCMD1LH0WSuO9h+VmY02/sQ/cwP7Fc/JCG0ZGRqY79ilYZ/DLxIFmB5L+Jo43 +g1O9Ul9J3QbA== From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, wsa+renesas@sang-engineering.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH 2/9] pinctrl: renesas: rzg2l: Drop defines present in struct rzg2l_hwcfg Date: Fri, 22 May 2026 13:22:44 +0300 Message-ID: <20260522102251.1723392-3-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522102251.1723392-1-claudiu.beznea@kernel.org> References: <20260522102251.1723392-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Drop the QSPI and OTHER_POC register defines, which are SoC specific and accessible through struct rzg2l_hwcfg::{qspi, other_poc}. Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index a648d75a2bd2..77443cf1f431 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -180,8 +180,6 @@ #define SMT(off) (0x3400 + (off) * 8) #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) -#define QSPI (0x3008) /* known on RZ/{G2L,G2LC,G2UL,Five} only */ -#define OTHER_POC (0x3028) /* known on RZ/G3L only */ =20 #define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <=3D 1.8V */ @@ -3816,9 +3814,9 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg =3D { .regs =3D { .pwpr =3D 0x3014, .sd_ch =3D 0x3000, + .qspi =3D 0x3008, .eth_poc =3D 0x300c, .oen =3D 0x3018, - .qspi =3D QSPI, }, .iolh_groupa_ua =3D { /* 3v3 power source */ @@ -3835,7 +3833,7 @@ static const struct rzg2l_hwcfg rzg3l_hwcfg =3D { .sd_ch =3D 0x3004, .eth_poc =3D 0x3010, .oen =3D 0x3018, - .other_poc =3D OTHER_POC, + .other_poc =3D 0x3028, }, .masks =3D { .other_poc_pvdd1833_oth_awo_poc =3D BIT(0), --=20 2.43.0 From nobody Sun May 24 18:42:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7F603E5590; Fri, 22 May 2026 10:23:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779445395; cv=none; b=cMad57cfjWduhOGrsDY9kZp0ZGeEL9SDgQF99pMnLmWXv4B49B33rfC2Ixs1aJdrgu8Ac9l5PgD7yI5h2Ib+FThRqe+g0Zy5qFw++/rkmKmOF2Kga56YsWGkxwM33oogqDYtBXIYIrg4F5z83VA7u7zbhUEK/4pBHB2+iwMLyuw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779445395; c=relaxed/simple; bh=l2Uj4xt+63HmKdjgb7EezycxDf+kepwJpwznf4eHN6A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=g5zvrvarT8BXjUS/as1wUbDru9/bvQo3LdcdZTJ3XDm6sAtoOskJ4vVy+rLxUWkz3Xyk0KoaNtTa2vvTcEFK0H1e7Ru5pQo9rPNYAN5kV9mwa1U7kB5k3w33CgaGJAOzSGatbcwu0vA+u2XQFSy/RdhRMG2kNai/djBQGq2tppA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dOpJv9h/; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dOpJv9h/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4AD051F00A3F; Fri, 22 May 2026 10:23:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779445392; bh=P3cBV2PxnmWeSNwKUBnmjOtO2VySEPTJeALnjDSE/Lc=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=dOpJv9h/0C/d+W4Zn1BzuT4dL9kQl+SAZWxntCPHrl/3IkcloQ9a3iuQXIFYf5BV9 ooR8Qdf/nj+ElJ8tjYuTsWLwrtUoQGcQ2TT606KjjeTNZNnIweF4WtTvxketfhf/VM EnqpbeFEkgw3Bz6VOjcAsF9+NroXm9bHg37mfibtB6Y8WnlMmzazMNuphdGfKqLg35 EgZYbAZY6gR2K+UVRsT+0++wa+4Ebez65u6tKTJ0yUxYJpeJCz5NWeXjkAu3udlUnD LX4DB0JFJZxIDR4fdOcPjYuRnctX8uazzuhlyNAAHKQGdfHqXhf0eNbZDiumrULpdH CgTNLlaBTyocg== From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, wsa+renesas@sang-engineering.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH 3/9] pinctrl: renesas: rzg2l: Keep member documentation aligned Date: Fri, 22 May 2026 13:22:45 +0300 Message-ID: <20260522102251.1723392-4-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522102251.1723392-1-claudiu.beznea@kernel.org> References: <20260522102251.1723392-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Keep the documentation for struct rzg2l_pinctrl_reg_cache members aligned with the struct member order. Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 77443cf1f431..b1ffdc133987 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -380,16 +380,16 @@ struct rzg2l_pinctrl_pin_settings { * @pmc: PMC registers cache * @pfc: PFC registers cache * @iolh: IOLH registers cache - * @pupd: PUPD registers cache * @ien: IEN registers cache + * @pupd: PUPD registers cache * @smt: SMT registers cache * @sr: SR registers cache * @nod: NOD registers cache * @clone: Clone register cache * @sd_ch: SD_CH registers cache * @eth_poc: ET_POC registers cache - * @other_poc: OTHER_POC register cache * @oen: Output Enable register cache + * @other_poc: OTHER_POC register cache * @qspi: QSPI registers cache */ struct rzg2l_pinctrl_reg_cache { --=20 2.43.0 From nobody Sun May 24 18:42:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99B1E3E1714; Fri, 22 May 2026 10:23:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779445397; cv=none; b=o7ce0wGzZ/I9FK9Mc8NFZjHQxP9hZbKbSuowTTYF+EBKWKKnWyX2NJ2koDpDmUucSXJLRtAcVg3lJoirTDDaC5hfJLMi01tTXxIWygHa0V3gcur/ZzrebWU0OsegFILh5cl9xw1OpSw8JZzjNpUbKcv12ceBzd16ox8ew79SJeY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779445397; c=relaxed/simple; bh=r94YYOnneZl5g78y1Es6ziDHoQfYcRQPd4LSXbGifKE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fAfYPM4b/WQ8mZ63+Iq5kx/viBGX624VkRYv329jTYDZGXSwH3Aip0hr0K8O8wwFIpOo7siMNDL/6l1TLfPYNQf0mtDymLKu/RSVlV9xBeU+W4Vbz8ze32Kju57mAFjRd0gNuh8xucmrpqoOlqGMZseyUcvNUebJAQJNQhLHCgE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=D4AcwFSO; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="D4AcwFSO" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 301461F00ADF; Fri, 22 May 2026 10:23:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779445396; bh=gbq0415eDXwHx+EGm1lEW07SwsGVGhqSlRkLd2RKaRU=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=D4AcwFSOPwtCgn/zd8cI/X4smXYqc9Kx5X0OeC/WuJzX45TkGOFKppFX0Kdk2Xx+z iUCQz22SQjKKIDsu2jOspmlvDhi4JvwXVUpYQlN3pDoJclvi5XL8rtJazlX9tMC22M lA87RfPINmNG7ZjKYoS0xVLzdeM/cchbr02w6oS5W3I80a2Eu470T1M8J1UDHm04Dp fPM95kN0gByalsYpwuwkbclwpQayiBN/0K8/OqaBTOr+X5z1TAG6sVE5fL9UQH+GTv JDANR2+jGD7h6BW/W9yRsgcpcFrABXLS0zU3EyQe+GdPfin0s/g4rV4mZhCf9ZGH6L MEOQfIC31dFDQ== From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, wsa+renesas@sang-engineering.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH 4/9] pinctrl: renesas: rzg2l: Use tab instead of spaces Date: Fri, 22 May 2026 13:22:46 +0300 Message-ID: <20260522102251.1723392-5-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522102251.1723392-1-claudiu.beznea@kernel.org> References: <20260522102251.1723392-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Use tab instead of spaces to follow the same coding style. Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index b1ffdc133987..517001145bd0 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -407,7 +407,7 @@ struct rzg2l_pinctrl_reg_cache { u8 sd_ch[2]; u8 eth_poc[2]; u8 oen; - u8 other_poc; + u8 other_poc; u8 qspi; }; =20 --=20 2.43.0 From nobody Sun May 24 18:42:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E7D33E1714; Fri, 22 May 2026 10:23:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779445401; cv=none; b=dPLVjQEtUng5Sex7VI7nXICGRGBXmIDQus6C9zaIbGy+6kmtyvP4Kcpc+KsfLFIJ/U1CLzDXINgRCIZrif/TgjY6FE1Cbu0XkL5EuTfqyae3VKmuavmQlHaRWdkGShP0oO+nkzG+/YnW6qPVNee+Iaw9emh8aeNQmrxyP7cq9A8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779445401; c=relaxed/simple; bh=odzKeAx3xAtW/AGGgIaMEmqpdSmeNMxlzlLr6+ZZjTs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ao4AqfA5Op0RGRBLuKsN+b8Xv7Oin9keH1YY/TAIjLq0bH156X0Sr8DkNrwLmdMS6po2Bn4H/Lljg80tHdG3MMTXvDMkiRi6oUs9xslSq2Q+/Qv1euzp6mvi5rlqhgDlyHetQoNzEU7zuASWQTPggq0Y+S7qtoBFULd1vIpl3gc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=D3wo5wUW; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="D3wo5wUW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 15E8E1F000E9; Fri, 22 May 2026 10:23:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779445400; bh=6MW412GldaFzSu+r4HcOKYF7u9/tvdCqWjKmh7EonC4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=D3wo5wUWf25MYwJd6e80X5oB0zi2tDtM53YChUj4MOdqRAkuiqBLYyVpGefGbWJiG UhnxvMJ115dJlyMzqOIKkU8BzGsc6mmVvGrQhlmXEPCR+VJ8qbg4SNoMrTNe7VdONh 9Hr5El/guTZomYbVq1VN5c7CE2gW1IIbZfFXpJb5I7HQ9vUHRdFqfklitf9YAeO2o1 BLnUwiKE+5RteXwoTR1RVXFOQMJPO3Za56NT6rUIpfCuPqwMNa8xNy56P8GPIFUrTI 9SGaQ6mBDci/tjNTEg8opyJicZFtutKow5HquDjkv+ULj6F9mwBPI56eexKsCgGQHy s0UwfD3EKlQPg== From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, wsa+renesas@sang-engineering.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH 5/9] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document the missing I3C power source option Date: Fri, 22 May 2026 13:22:47 +0300 Message-ID: <20260522102251.1723392-6-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522102251.1723392-1-claudiu.beznea@kernel.org> References: <20260522102251.1723392-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The I3C pins on the Renesas RZ/G3S SoC can be powered at either 1.2V or 1.8V. Document the missing 1.2V power source option. Signed-off-by: Claudiu Beznea Acked-by: Conor Dooley --- .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.ya= ml index fb1fe1ea759f..32864c9add4a 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -129,7 +129,7 @@ additionalProperties: enum: [ 33, 50, 66, 100 ] power-source: description: I/O voltage in millivolt. - enum: [ 1800, 2500, 3300 ] + enum: [ 1200, 1800, 2500, 3300 ] slew-rate: true gpio-hog: true gpios: true --=20 2.43.0 From nobody Sun May 24 18:42:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C0673E16B5; Fri, 22 May 2026 10:23:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779445405; cv=none; b=TltFVQGm6Borzs4dy+UBcCvUdI68OKBvYythrBnhuUNXJF3Euft7uGT1FjOV3Uu+rSF7VRkNrTMezV3WMwIwb/FjmKFFczO1W9cf+7tS3drh/zKwPrCeKe4rD9XkMdyOsKZsfu+/xPmJNdN7XCKwAfV/wmSdZag7ikZnBq/K1mc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779445405; c=relaxed/simple; bh=k/x1H1lb5SDnYhbID3OaHDBaQfG1JKtPUzs4Ksb4Bu8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GbpRWM5eDpopdGWLXjp0/pMQn4chW5OIFenPH7oqvqCZVCV9fBIApa0qg27xOOC0A4mAb0PuA9X3zhnzk3I3Yf06uONxuTEd3dz1WhBmOhHgJzPPYV7e74YRRhQwzqyEAasXgQtoG4HH2+NJ1hoXFaGJy48Rad0tWSWV0ESFKfI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=D3ti6WNC; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="D3ti6WNC" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D60931F00A3E; Fri, 22 May 2026 10:23:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779445404; bh=a9hTL/kCvVkTVRTfV4ZAvZnfvLN46nq4BPNWu82pu7Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=D3ti6WNC2WhdLtKJ7EfXLaKcKCF3xT5d2hhjK1mHW+T4gkUFwTDanuCU8TZLriJfs lPMgpytwrBZCBUkeNQV53ltcRK/ZrBPgh0GlGbelhW0lczODZTrVfSB6ll9Wyo2ic6 LRJVkGOfmHQzMl9C92pN7HRN5B+fpt2HZkgWUCyxkyMSJNpcnW/Q8As3dMdm1oq9ft PXieg/9LZZ9o0mMxRn2BNPKmRzOqmgLSmFWrOqZB7reoeNm4ObRegvdSgMfXQeLp8o mUBeYZLutJBV3mTt4ECJMuenxBYgJAODY/P2sB+VN0Dz8963rjYyf0RhNx1NqX3M4X wSIwDydSHenkQ== From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, wsa+renesas@sang-engineering.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH 6/9] pinctrl: renesas: rzg2l: Add RZ/G3S support for selecting the I3C power source Date: Fri, 22 May 2026 13:22:48 +0300 Message-ID: <20260522102251.1723392-7-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522102251.1723392-1-claudiu.beznea@kernel.org> References: <20260522102251.1723392-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The Renesas RZ/G3S I3C pins can be powered at either 1.8V or 1.2V. The pin controller provides a register to select between these two options. Update the Renesas RZ/G2L pin controller driver to allow selecting the I3C power source on RZ/G3S SoC. Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 73 +++++++++++++++++++++++-- 1 file changed, 68 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 517001145bd0..68329b6c6649 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -69,6 +69,7 @@ #define PIN_CFG_PVDD1833_OTH_AWO_POC BIT(19) /* known on RZ/G3L only */ #define PIN_CFG_PVDD1833_OTH_ISO_POC BIT(20) /* known on RZ/G3L only */ #define PIN_CFG_WDTOVF_N_POC BIT(21) /* known on RZ/G3L only */ +#define PIN_CFG_IO_VMC_I3C BIT(22) =20 #define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ #define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */ @@ -186,6 +187,9 @@ #define PVDD_3300 0 /* I/O domain voltage >=3D 3.3V */ #define PVDD_MASK 0x3 =20 +#define PVDD_I3C_1200 1 /* I3C I/O domain voltage 1.2V */ +#define PVDD_I3C_1800 0 /* I3C I/O domain voltage 1.8V */ + #define PWPR_B0WI BIT(7) /* Bit Write Disable */ #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ #define PWPR_REGWE_A BIT(6) /* PFC and PMC Register Write Enable on RZ/V2= H(P) */ @@ -257,6 +261,7 @@ static const struct pin_config_item renesas_rzv2h_conf_= items[] =3D { * @oen: OEN register offset * @qspi: QSPI register offset * @other_poc: OTHER_POC register offset + * @i3c_set: I3C_SET register offset */ struct rzg2l_register_offsets { u16 pwpr; @@ -265,6 +270,7 @@ struct rzg2l_register_offsets { u16 oen; u16 qspi; u16 other_poc; + u16 i3c_set; }; =20 /** @@ -272,6 +278,7 @@ struct rzg2l_register_offsets { * @other_poc_pvdd1833_oth_awo_poc: PVDD1833_OTH_AWO_POC mask * @other_poc_pvdd1833_oth_iso_poc: PVDD1833_OTH_ISO_POC mask * @other_poc_wdtovf_n_poc: WDTOVF_N_POC mask + * @i3c_set_poc: I3C_SET_POC mask */ struct rzg2l_register_masks { union { @@ -281,6 +288,11 @@ struct rzg2l_register_masks { u8 other_poc_pvdd1833_oth_iso_poc; u8 other_poc_wdtovf_n_poc; }; + + /* RZ/G3S masks */ + struct { + u8 i3c_set_poc; + }; }; }; =20 @@ -391,6 +403,7 @@ struct rzg2l_pinctrl_pin_settings { * @oen: Output Enable register cache * @other_poc: OTHER_POC register cache * @qspi: QSPI registers cache + * @i3c_set: I3C_SET register cache */ struct rzg2l_pinctrl_reg_cache { u8 *p; @@ -409,6 +422,7 @@ struct rzg2l_pinctrl_reg_cache { u8 oen; u8 other_poc; u8 qspi; + u8 i3c_set; }; =20 struct rzg2l_pinctrl { @@ -441,6 +455,7 @@ struct rzg2l_pinctrl { }; =20 static const u16 available_ps[] =3D { 1800, 2500, 3300 }; +static const u16 available_i3c_ps[] =3D { 1200, 1800 }; =20 static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, u64 pincfg, @@ -1101,12 +1116,28 @@ static int rzg2l_caps_to_pwr_reg(const struct rzg2l= _register_offsets *regs, *mask =3D masks->other_poc_wdtovf_n_poc; return 0; } + if (caps & PIN_CFG_IO_VMC_I3C) { + *offset =3D regs->i3c_set; + *mask =3D masks->i3c_set_poc; + return 0; + } =20 return -EINVAL; } =20 static int rzg2l_pwr_reg_val_to_ps(u8 val, u32 caps) { + if (caps & PIN_CFG_IO_VMC_I3C) { + switch (val) { + case PVDD_I3C_1200: + return 1200; + case PVDD_I3C_1800: + return 1800; + } + + return -EINVAL; + } + switch (val) { case PVDD_1800: return 1800; @@ -1121,6 +1152,19 @@ static int rzg2l_pwr_reg_val_to_ps(u8 val, u32 caps) =20 static int rzg2l_ps_to_pwr_reg_val(u8 *val, u32 ps, u32 caps) { + if (caps & PIN_CFG_IO_VMC_I3C) { + switch (ps) { + case 1200: + *val =3D PVDD_I3C_1200; + return 0; + case 1800: + *val =3D PVDD_I3C_1800; + return 0; + } + + return -EINVAL; + } + switch (ps) { case 1800: *val =3D PVDD_1800; @@ -1194,12 +1238,21 @@ static int rzg2l_set_power_source(struct rzg2l_pinc= trl *pctrl, u32 pin, u32 caps return 0; } =20 -static bool rzg2l_ps_is_supported(u16 ps) +static bool rzg2l_ps_is_supported(u16 ps, u32 caps) { - unsigned int i; + unsigned int i, len; + const u16 *array; =20 - for (i =3D 0; i < ARRAY_SIZE(available_ps); i++) { - if (available_ps[i] =3D=3D ps) + if (caps & PIN_CFG_IO_VMC_I3C) { + array =3D available_i3c_ps; + len =3D ARRAY_SIZE(available_i3c_ps); + } else { + array =3D available_ps; + len =3D ARRAY_SIZE(available_ps); + } + + for (i =3D 0; i < len; i++) { + if (array[i] =3D=3D ps) return true; } =20 @@ -1800,7 +1853,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_d= ev *pctldev, =20 /* Apply power source. */ if (settings.power_source !=3D pctrl->settings[_pin].power_source) { - ret =3D rzg2l_ps_is_supported(settings.power_source); + ret =3D rzg2l_ps_is_supported(settings.power_source, cfg); if (!ret) return -EINVAL; =20 @@ -2498,6 +2551,8 @@ static const struct rzg2l_dedicated_configs rzg3s_ded= icated_pins[] =3D { { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x2, 0, PIN_CFG_IEN) }, { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x2, 1, PIN_CFG_IEN) }, { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_C= FG_SOFT_PS) }, + { "I3C_SDA", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IEN | PIN_CFG_IO_VMC_= I3C)) }, + { "I3C_SCL", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IEN | PIN_CFG_IO_VMC_= I3C)) }, { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_= VMC_SD0)) }, { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN= | PIN_CFG_IO_VMC_SD0)) }, @@ -3717,6 +3772,8 @@ static int rzg2l_pinctrl_suspend_noirq(struct device = *dev) cache->oen =3D readb(pctrl->base + pctrl->data->hwcfg->regs.oen); if (regs->other_poc) cache->other_poc =3D readb(pctrl->base + regs->other_poc); + if (regs->i3c_set) + cache->i3c_set =3D readb(pctrl->base + regs->i3c_set); =20 if (pctrl->syscon) { int ret; @@ -3759,6 +3816,8 @@ static int rzg2l_pinctrl_resume_noirq(struct device *= dev) writeb(cache->qspi, pctrl->base + regs->qspi); if (regs->other_poc) writeb(cache->other_poc, pctrl->base + regs->other_poc); + if (regs->i3c_set) + writeb(cache->i3c_set, pctrl->base + regs->i3c_set); =20 raw_spin_lock_irqsave(&pctrl->lock, flags); rzg2l_oen_write_with_pwpr(pctrl, cache->oen); @@ -3871,8 +3930,12 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg =3D { .pwpr =3D 0x3000, .sd_ch =3D 0x3004, .eth_poc =3D 0x3010, + .i3c_set =3D 0x301c, .oen =3D 0x3018, }, + .masks =3D { + .i3c_set_poc =3D BIT(2), + }, .iolh_groupa_ua =3D { /* 1v8 power source */ [RZG2L_IOLH_IDX_1V8] =3D 2200, 4400, 9000, 10000, --=20 2.43.0 From nobody Sun May 24 18:42:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D6433F1ADF; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HrH3gYeE" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A3EF41F00A3F; Fri, 22 May 2026 10:23:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779445407; bh=NvT2fppSlj/gIreeQ+5hb0r40tegKZeJ3kZ9EEuIgzI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=HrH3gYeE9HOXOC4cChypNKnfKcLlAu0xxTGtDreHz6cdokcJ+VWoB0HQpKxydQfWn WggJTzVsGdE0FPU0TNYA9b086ZOX20S9piZzaNDe/v7kdcSCB3rKkEKVhfXE0Fzem0 rbVHXOdMV65jzl2TrfJ0oUB6gKDixHs56nsD4KxhjyTlqjGwTBVNNnZZ0GNiOYtjnz gW3flHxbHHTZmEn3GoHZDjeJ0gqOBGpLcrOkJg7qqy0alMc4CazQDL6z+xM35AM98D qkix4R/AC8lH5HAmGglz3feiJZGoOQHdTyRBGW2LioiWAzKcMqGxL3+1RftoqaVKAU WJAiarFo1K3hA== From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, wsa+renesas@sang-engineering.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH 7/9] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document the I3C standby property Date: Fri, 22 May 2026 13:22:49 +0300 Message-ID: <20260522102251.1723392-8-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522102251.1723392-1-claudiu.beznea@kernel.org> References: <20260522102251.1723392-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The I3C pins on the Renesas RZ/G3S SoC can be configured in standby mode when operating in I2C mode. According to the RZ/G3S HW manual (Rev. 1.20), when standby mode is selected, the output is fixed at Hi-Z and no data is transferred internally, even if data is received from outside. Document the renesas,i3c-standby property. Signed-off-by: Claudiu Beznea --- .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.ya= ml index 32864c9add4a..94a51666b1a2 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -153,6 +153,13 @@ additionalProperties: register, which adjusts the drive strength value and is pin-de= pendent. $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2, 3] + renesas,i3c-standby: + description: + Controls the standby mode of the I3C interface when operating = in I2C mode. + When standby mode is selected, the output is fixed at Hi-Z and= no data is + transferred internally, even if data is received from outside. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] =20 - type: object additionalProperties: --=20 2.43.0 From nobody Sun May 24 18:42:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5FCB3E558E; Fri, 22 May 2026 10:23:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779445417; cv=none; b=AQwT0JmB6sIR/Su9GBn7D3AbG8Z/gShsC9v/5V8hFuLf59r5euaw+AbrR7iohX7XVvIVteR+FQvx/5xrd3V/4UM3/rLgaOcwmjWXkoZAD0X6VZaGRZpt2bD3fYsGGU9+lj3rwvYPr9ItwHkyBqlnVlle3J4r67exF8MdygCZlCo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779445417; c=relaxed/simple; bh=3ieREa1l0OIGxVr2h0+jei79Cqol5ZZWYWjHXdW0cTw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EIvQPcORdSJqG5x0kO+dBaaajWfu9u7j2PTyJ/2DGrOoPr9z/5YzduEDZ23/8kQ0tA+Ji8IqFnJpBq7gPXPrsCIT+CsPRxh4eLFfdLz+MWk1Fs6XIocDzR54Rx2rTGd+GFUY01yDry1udk8yk1mAWQ9kMyDfD/Tu7lIuyJjG8Ok= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FURRJO1e; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FURRJO1e" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 755A01F00A3D; Fri, 22 May 2026 10:23:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779445412; bh=SpzT0kfCrLKElIpEGkZ7lbyJuca/WmE2raj0yWcYax8=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=FURRJO1emf/MSMNnJECgBRN1aDo8vmJbo1iYOo/qD6ycdWNKV84Sz5PTzdgE7fFFW 9wj/i8EaYBjcA7PC/9tAY0xHKC7qMJ5ce+b2XBkjAcmB5mcrzbr6FfBwFobVQuRkhf 1+CX/GzSsi6Uq5OkuamuHSmk4hiJI6/4KbF4ngiXk86a7liGOhBuOrvy+Wpb1r7nP2 8WVE4xeCyotpAQedDLsRaoDx18gR2kHGX1EkiKjkZaXHAo/RJjsbc4lBZXKDBEKoJl 8U4wv/jFbD/YuJpa4h5xdbsFEzKC4Wa6+AKj+bD9S8b9mZ3tzbPhTCdL+HdjVf/2qA fR8TkxEISX0/g== From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, wsa+renesas@sang-engineering.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH 8/9] pinctrl: renesas: rzg2l: Add RZ/G3S support for selecting the I3C standby state Date: Fri, 22 May 2026 13:22:50 +0300 Message-ID: <20260522102251.1723392-9-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522102251.1723392-1-claudiu.beznea@kernel.org> References: <20260522102251.1723392-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The I3C pins on the Renesas RZ/G3S SoC can be switched to a standby mode when the controller operates in I2C mode. According to the RZ/G3S HW manual (Rev. 1.20), in standby mode "the output is fixed at Hi-Z and no data is transferred to the inside even if data is input from outside". Add support to configure the I3C standby mode. Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 49 ++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 68329b6c6649..b313de35e9df 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -70,6 +70,7 @@ #define PIN_CFG_PVDD1833_OTH_ISO_POC BIT(20) /* known on RZ/G3L only */ #define PIN_CFG_WDTOVF_N_POC BIT(21) /* known on RZ/G3L only */ #define PIN_CFG_IO_VMC_I3C BIT(22) +#define PIN_CFG_I3C_STANDBY_RZG3S BIT(23) =20 #define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ #define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */ @@ -215,15 +216,24 @@ =20 /* Custom pinconf parameters */ #define RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE (PIN_CONFIG_END + 1) +#define RENESAS_RZG3S_PIN_CONFIG_I3C_STANDBY (PIN_CONFIG_END + 2) =20 static const struct pinconf_generic_params renesas_rzv2h_custom_bindings[]= =3D { { "renesas,output-impedance", RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, = 1 }, }; =20 +static const struct pinconf_generic_params renesas_rzg3s_custom_bindings[]= =3D { + { "renesas,i3c-standby", RENESAS_RZG3S_PIN_CONFIG_I3C_STANDBY, 0 }, +}; + #ifdef CONFIG_DEBUG_FS static const struct pin_config_item renesas_rzv2h_conf_items[] =3D { PCONFDUMP(RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, "output-impedance", = "x", true), }; + +static const struct pin_config_item renesas_rzg3s_conf_items[] =3D { + PCONFDUMP(RENESAS_RZG3S_PIN_CONFIG_I3C_STANDBY, "standby", NULL, true), +}; #endif =20 /* Read/write 8 bits register */ @@ -279,6 +289,7 @@ struct rzg2l_register_offsets { * @other_poc_pvdd1833_oth_iso_poc: PVDD1833_OTH_ISO_POC mask * @other_poc_wdtovf_n_poc: WDTOVF_N_POC mask * @i3c_set_poc: I3C_SET_POC mask + * @i3c_set_stbn: I3C_SET_STBN mask */ struct rzg2l_register_masks { union { @@ -292,6 +303,7 @@ struct rzg2l_register_masks { /* RZ/G3S masks */ struct { u8 i3c_set_poc; + u8 i3c_set_stbn; }; }; }; @@ -1560,6 +1572,8 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_d= ev *pctldev, struct rzg2l_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctldev); const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; const struct pinctrl_pin_desc *pin =3D &pctrl->desc.pins[_pin]; + const struct rzg2l_register_offsets *regs =3D &hwcfg->regs; + const struct rzg2l_register_masks *masks =3D &hwcfg->masks; u32 param =3D pinconf_to_config_param(*config); u64 *pin_data =3D pin->drv_data; unsigned int arg =3D 0; @@ -1702,6 +1716,14 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_= dev *pctldev, arg =3D rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); break; =20 + case RENESAS_RZG3S_PIN_CONFIG_I3C_STANDBY: + if (!(cfg & PIN_CFG_I3C_STANDBY_RZG3S)) + return -EINVAL; + + arg =3D readb(pctrl->base + regs->i3c_set); + arg =3D !field_get(masks->i3c_set_stbn, arg); + break; + default: return -ENOTSUPP; } @@ -1720,6 +1742,8 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_d= ev *pctldev, const struct pinctrl_pin_desc *pin =3D &pctrl->desc.pins[_pin]; const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; struct rzg2l_pinctrl_pin_settings settings =3D pctrl->settings[_pin]; + const struct rzg2l_register_offsets *regs =3D &hwcfg->regs; + const struct rzg2l_register_masks *masks =3D &hwcfg->masks; u64 *pin_data =3D pin->drv_data; unsigned int i, arg, index; u32 off, param; @@ -1846,6 +1870,19 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_= dev *pctldev, rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, arg); break; =20 + case RENESAS_RZG3S_PIN_CONFIG_I3C_STANDBY: + if (!(cfg & PIN_CFG_I3C_STANDBY_RZG3S)) + return -EINVAL; + + scoped_guard(raw_spinlock, &pctrl->lock) { + u8 tmp =3D readb(pctrl->base + regs->i3c_set); + + tmp &=3D ~masks->i3c_set_stbn; + tmp |=3D field_prep(masks->i3c_set_stbn, !arg); + writeb(tmp, pctrl->base + regs->i3c_set); + } + break; + default: return -ENOTSUPP; } @@ -2551,8 +2588,10 @@ static const struct rzg2l_dedicated_configs rzg3s_de= dicated_pins[] =3D { { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x2, 0, PIN_CFG_IEN) }, { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x2, 1, PIN_CFG_IEN) }, { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_C= FG_SOFT_PS) }, - { "I3C_SDA", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IEN | PIN_CFG_IO_VMC_= I3C)) }, - { "I3C_SCL", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IEN | PIN_CFG_IO_VMC_= I3C)) }, + { "I3C_SDA", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IEN | PIN_CFG_IO_VMC_= I3C | + PIN_CFG_I3C_STANDBY_RZG3S)) }, + { "I3C_SCL", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IEN | PIN_CFG_IO_VMC_= I3C | + PIN_CFG_I3C_STANDBY_RZG3S)) }, { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_= VMC_SD0)) }, { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN= | PIN_CFG_IO_VMC_SD0)) }, @@ -3934,6 +3973,7 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg =3D { .oen =3D 0x3018, }, .masks =3D { + .i3c_set_stbn =3D BIT(0), .i3c_set_poc =3D BIT(2), }, .iolh_groupa_ua =3D { @@ -4020,6 +4060,11 @@ static struct rzg2l_pinctrl_data r9a08g045_data =3D { .pin_to_oen_bit =3D &rzg3s_pin_to_oen_bit, .hw_to_bias_param =3D &rzg2l_hw_to_bias_param, .bias_param_to_hw =3D &rzg2l_bias_param_to_hw, + .num_custom_params =3D ARRAY_SIZE(renesas_rzg3s_custom_bindings), + .custom_params =3D renesas_rzg3s_custom_bindings, +#ifdef CONFIG_DEBUG_FS + .custom_conf_items =3D renesas_rzg3s_conf_items, +#endif }; =20 static struct rzg2l_pinctrl_data r9a08g046_data =3D { --=20 2.43.0 From nobody Sun May 24 18:42:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 404FA3F54AA; Fri, 22 May 2026 10:23:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779445417; cv=none; b=tCg6pkLU/bxL24yQapci48S4UiRIPVbhIBd3f+lnJ4jSmDkGPP46xWFuUytfip6OoxoBcszmCBHeK8VCYMT4ikimdFw1DwN4PF5/HDI7I0EdQYAAdpztpryr7eAYF7NKJX7eiDwkvLWKEmd9Wa3U4Hk2kj0UNOufa55Zph+TYfU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779445417; c=relaxed/simple; bh=W9lPTgx6mDxArcLHARU/ZZqLqgXOeySBXq57O5dffOs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SWGCi6tKDzwYC4IGVBTBB04zlenHDZLugup0pzQYK8hXg8O7G4lVuUfgyY/mhsvk8Iupkh1rjTL//VRDaZU0A5CZ5m28yX4KbSXQH1olu0wZ6USIEoJIDmZngmrcB6KTNDlKx6mc/tP9WwmCBuG5HDMVU1u4dTnwQvzT9/c1u7I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BaUCIE1k; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BaUCIE1k" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D34031F00A3F; Fri, 22 May 2026 10:23:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779445416; bh=6QEWAjHSDHCKnr4dwU2wD6RoMsBK3plNIjm7Iq3i+s8=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=BaUCIE1kfn+KGCxtZcLLpv0Y863cq/kKP75/p17kFXApysgQCbjRPhocHhu/IaBFN 3u66CR12I398qeXH123vQMeXsT+Ew+gTqLuQco5rm8IupF5I5mGPQkBfgbXMBRP6x5 Hoig1NUC+STlw353HUNCDqKw916OGcdRq32uXaTCCDek+qt3vO5tahJNeXDa+u4eFD QFXTjNs8/Q2WozqWzgREVGFySQ7BeVjnk4I1GloLYcqTa6AqANo7q4cWAtWbHv45fP RFr9AZPd+22TYJP3SWaSsu9Ho4XjnWWWBM0SgyjrMQSxHRVsrnSQ+TXvj5No3yAWde XOhgQYSCP1Yxg== From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, wsa+renesas@sang-engineering.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH 9/9] arm64: dts: renesas: rzg3s-smarc-som: Enable I3C Date: Fri, 22 May 2026 13:22:51 +0300 Message-ID: <20260522102251.1723392-10-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522102251.1723392-1-claudiu.beznea@kernel.org> References: <20260522102251.1723392-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The Renesas RZ/G3S SMARC SoM board has a connector for I3C interface. Enable I3C. Signed-off-by: Claudiu Beznea --- .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 30 +++++++++++++++++++ .../boot/dts/renesas/rzg3s-smarc-switches.h | 4 +++ 2 files changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3s-smarc-som.dtsi index b45acfe6288a..370b39b6a33d 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -168,6 +168,15 @@ a0 80 30 30 9c }; }; =20 +&i3c { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&i3c_pins>; + pinctrl-1 =3D <&i3c_standby_pins>; + i2c-scl-hz =3D <400000>; + i3c-scl-hz =3D <12500000>; + status =3D "okay"; +}; + &pcie_port0 { clocks =3D <&versa3 5>; clock-names =3D "ref"; @@ -302,6 +311,27 @@ mux { }; }; =20 + i3c_pins: i3c { + pins =3D "I3C_SDA", "I3C_SCL"; +#if SW_CONFIG4 =3D=3D SW_ON + power-source =3D <1200>; +#else + power-source =3D <1800>; +#endif + input-enable; + renesas,i3c-standby =3D <0>; + }; + + i3c_standby_pins: i3c-standby { + pins =3D "I3C_SDA", "I3C_SCL"; +#if SW_CONFIG4 =3D=3D SW_ON + power-source =3D <1200>; +#else + power-source =3D <1800>; +#endif + renesas,i3c-standby =3D <1>; + }; + sdhi0_pins: sd0 { data { pins =3D "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h b/arch/arm6= 4/boot/dts/renesas/rzg3s-smarc-switches.h index bbf908a5322c..9cccc87da057 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h @@ -25,9 +25,13 @@ * @SW_CONFIG3: * SW_OFF - SD2 is connected to SoC * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC + * @SW_CONFIG4: + * SW_OFF - I3C voltage is 1.8V + * SW_ON - I3C voltage is 1.2V */ #define SW_CONFIG2 SW_OFF #define SW_CONFIG3 SW_ON +#define SW_CONFIG4 SW_OFF =20 /* * SW_OPT_MUX[x] switches' states: --=20 2.43.0