From nobody Sun May 24 19:34:49 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5897D23AB9D; Fri, 22 May 2026 06:49:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779432595; cv=none; b=oNMCJKTsT7OVA0eBNd+CIXrE45Tg9aOY+f2CUb1d1d6kiuumpV6MAvqoJHLSu23RQyGPI2qp44KdQLmmk5DzvPZPUCDNkVB98uQeqnwfvstULE2ipU/2zDlxslx7zY6e+0YK7UcnzLO9OQfWqUP7xyLz2jsklhlHGBXgrHs9yxM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779432595; c=relaxed/simple; bh=xf2yltQCPL4KYbVDKfNIsg8mC4dPbeakx6my0quoUbs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=r5n+StEDp11NnxS6JDaShtVNdLWRnWMrP1ELM72Ugl2YIFLcJlvJoW14siEPGhoAL8G5RgfNnFx6TbfOi7+/tjiyQ4EtV1h/xy61McWF8BFmFm5JJ/JzmMOV5ny8ZE+sFsGBvOyEW7cnyMZVGT7RWtqHGwcqeqLrHPEsir9djog= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8DxBOmP_A9qT0sMAA--.29718S3; Fri, 22 May 2026 14:49:51 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxpsCL_A9qKU6MAA--.34947S3; Fri, 22 May 2026 14:49:51 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH v4 1/5] LoongArch: KVM: Check irq validility in kvm_vcpu_ioctl_interrupt() Date: Fri, 22 May 2026 14:49:41 +0800 Message-Id: <20260522064945.614486-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260522064945.614486-1-maobibo@loongson.cn> References: <20260522064945.614486-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxpsCL_A9qKU6MAA--.34947S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" Function kvm_vcpu_ioctl_interrupt() can be called from userspace, here add irq validility cheking in kvm_vcpu_ioctl_interrupt(). Fixes: f45ad5b8aa93 ("LoongArch: KVM: Implement vcpu interrupt operations") Cc: stable@vger.kernel.org Signed-off-by: Bibo Mao --- arch/loongarch/kvm/vcpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c index e28084c49e68..df5be9b265e8 100644 --- a/arch/loongarch/kvm/vcpu.c +++ b/arch/loongarch/kvm/vcpu.c @@ -1487,6 +1487,11 @@ void kvm_lose_fpu(struct kvm_vcpu *vcpu) int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, struct kvm_interrupt *= irq) { int intr =3D (int)irq->irq; + unsigned int vector; + + vector =3D abs(intr); + if (vector >=3D EXCCODE_INT_NUM) + return -EINVAL; =20 if (intr > 0) kvm_queue_irq(vcpu, intr); --=20 2.39.3 From nobody Sun May 24 19:34:49 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EC2B3382F16; Fri, 22 May 2026 06:49:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779432595; cv=none; b=rIIj7PAKCVenKAhj1IcOSjgExMQDYHCh+S7ldbU7jPfenvMjVYoPFW+0/tY5DNu7ZDPIDOvsc6lfLofh+WRVqfcJlxo9Ako61CLa+3d2mXb/Koa0OOxvV7Xf6/q00Ymaw7+bAjbqkVIOLaI7jyD3E1M4gSK7yon8CLr/T2p4Toc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779432595; c=relaxed/simple; bh=YXvPAAq9mWglp8bbJDg6RlfHdjGIxJI5tkxM4tuS3Vk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=AIzPvBh8ZTRevOUpBdvzPaTqbOhtvsQfGgFgai26ALI7OsQWaOv0bYfjtZ2xHZoVbMu99+Wghb1+BHP8FwbLMoTq1ovrsyOShuKCK7Z9thfd9eMkjUYmMnrZBLNbmKIuJBLmTIdIgP40ludFCccCYxJd2BOdb9Z4M7asXqb68MA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Cx3emP_A9qU0sMAA--.35477S3; Fri, 22 May 2026 14:49:51 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxpsCL_A9qKU6MAA--.34947S4; Fri, 22 May 2026 14:49:51 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/5] LoongArch: KVM: Check msgint feature in interrupt post Date: Fri, 22 May 2026 14:49:42 +0800 Message-Id: <20260522064945.614486-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260522064945.614486-1-maobibo@loongson.cn> References: <20260522064945.614486-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxpsCL_A9qKU6MAA--.34947S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" Interrupt AVEC is valid only if VM has msgint feature, and this feature is checked in interrupt handling. Since interrupt handling is executing in VM context switch, and it is hot path, here move the feature checking in interrupt post rather than interrupt handling. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/interrupt.c | 5 ----- arch/loongarch/kvm/vcpu.c | 14 +++++++++----- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/arch/loongarch/kvm/interrupt.c b/arch/loongarch/kvm/interrupt.c index a18c60dffbba..48dd56aa4dc5 100644 --- a/arch/loongarch/kvm/interrupt.c +++ b/arch/loongarch/kvm/interrupt.c @@ -36,8 +36,6 @@ static int kvm_irq_deliver(struct kvm_vcpu *vcpu, unsigne= d int priority) =20 switch (priority) { case INT_AVEC: - if (!kvm_guest_has_msgint(&vcpu->arch)) - break; dmsintc_inject_irq(vcpu); fallthrough; case INT_TI: @@ -75,9 +73,6 @@ static int kvm_irq_clear(struct kvm_vcpu *vcpu, unsigned = int priority) =20 switch (priority) { case INT_AVEC: - if (!kvm_guest_has_msgint(&vcpu->arch)) - break; - fallthrough; case INT_TI: case INT_IPI: case INT_SWI0: diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c index df5be9b265e8..ebd432da3ca4 100644 --- a/arch/loongarch/kvm/vcpu.c +++ b/arch/loongarch/kvm/vcpu.c @@ -1493,14 +1493,18 @@ int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,= struct kvm_interrupt *irq) if (vector >=3D EXCCODE_INT_NUM) return -EINVAL; =20 - if (intr > 0) + if (!kvm_guest_has_msgint(&vcpu->arch) && (vector =3D=3D INT_AVEC)) + return -EINVAL; + + /* + * Clear irq with INT_SWI0 (which is 0) is missing from SW side + * INT_SWI0 is cleared by guest kernel with the similar instruction + * clear_csr_estat(1 << INT_SWI0) + */ + if (intr >=3D 0) kvm_queue_irq(vcpu, intr); else if (intr < 0) kvm_dequeue_irq(vcpu, -intr); - else { - kvm_err("%s: invalid interrupt ioctl %d\n", __func__, irq->irq); - return -EINVAL; - } =20 kvm_vcpu_kick(vcpu); =20 --=20 2.39.3 From nobody Sun May 24 19:34:49 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9DD0A3403F8; Fri, 22 May 2026 06:49:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779432595; cv=none; b=CY2t7Mr7JwzqVaF3N5vaZYI5MJzkBBb3e4BZ1y3TJckQQcg88xIj0EoHLBqmC7+uhhvcl/lDA/TxYwKPV3O9RoHsgiUux5J+VTM9gDsc3iXYEHHSSTpRXhY/du77JKT5IsDExJFBJN3yUh2QBmZwM9hX+b0yIUvBXZO3v16VxYI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779432595; c=relaxed/simple; bh=5v/YhmDMLJUxGqRTdK6KcWlJJbiOgeKq9doSJA+sBG4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OD9l+AxaLMX8j4GI/VxAo6wfTqRztADakfMBQrtpOnlyu9y+rNh5iZ0z0coR1/l5pItXd1mYYWXgNr5xJBcGhkzJP144727MRSjfwwuu/2Jdla9kt9ZT/xO8qecVt6BG69QomhIKgLCjU37sIzgv+m/VZzTB4iMqCxU2oAdKICw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Cx3sCQ_A9qV0sMAA--.12089S3; Fri, 22 May 2026 14:49:52 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxpsCL_A9qKU6MAA--.34947S5; Fri, 22 May 2026 14:49:51 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v4 3/5] LoongArch: KVM: Use existing macro about interrupt bit mask Date: Fri, 22 May 2026 14:49:43 +0800 Message-Id: <20260522064945.614486-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260522064945.614486-1-maobibo@loongson.cn> References: <20260522064945.614486-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxpsCL_A9qKU6MAA--.34947S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" With interrupt post, register CSR_GINTC and CSR_ESTAT is used, and CSR_ESTAT is used for percpu interrupt injection and CSR_GINTC is for external hardware interrupt injection. Here use existing macro about interrupt bit of register CSR_GINTC and CSR_ESTAT, rather than hard coded constant value. Signed-off-by: Bibo Mao --- arch/loongarch/include/asm/kvm_vcpu.h | 43 ++++++++++++++++++--------- 1 file changed, 29 insertions(+), 14 deletions(-) diff --git a/arch/loongarch/include/asm/kvm_vcpu.h b/arch/loongarch/include= /asm/kvm_vcpu.h index 3784ab4ccdb5..efe26b04b35f 100644 --- a/arch/loongarch/include/asm/kvm_vcpu.h +++ b/arch/loongarch/include/asm/kvm_vcpu.h @@ -10,22 +10,37 @@ #include =20 /* Controlled by 0x5 guest estat */ -#define CPU_SIP0 (_ULCAST_(1)) -#define CPU_SIP1 (_ULCAST_(1) << 1) -#define CPU_PMU (_ULCAST_(1) << 10) -#define CPU_TIMER (_ULCAST_(1) << 11) -#define CPU_IPI (_ULCAST_(1) << 12) -#define CPU_AVEC (_ULCAST_(1) << 14) +#define CPU_SIP0 BIT(INT_SWI0) +#define CPU_SIP1 BIT(INT_SWI1) +#define CPU_HWI0 BIT(INT_HWI0) +#define CPU_HWI1 BIT(INT_HWI1) +#define CPU_HWI2 BIT(INT_HWI2) +#define CPU_HWI3 BIT(INT_HWI3) +#define CPU_HWI4 BIT(INT_HWI4) +#define CPU_HWI5 BIT(INT_HWI5) +#define CPU_HWI6 BIT(INT_HWI6) +#define CPU_HWI7 BIT(INT_HWI7) +#define CPU_PMU BIT(INT_PCOV) +#define CPU_TIMER BIT(INT_TI) +#define CPU_IPI BIT(INT_IPI) +#define CPU_AVEC BIT(INT_AVEC) +#define KVM_ESTAT_IRQ_MASK (CPU_SIP0 | CPU_SIP1 | CPU_PMU | CPU_TIMER \ + | CPU_IPI | CPU_AVEC) +#define KVM_ESTAT_HWI_MASK (CPU_HWI0 | CPU_HWI1 | CPU_HWI2 | CPU_HWI3 \ + | CPU_HWI4 | CPU_HWI5 | CPU_HWI6 | CPU_HWI7) =20 /* Controlled by 0x52 guest exception VIP aligned to estat bit 5~12 */ -#define CPU_IP0 (_ULCAST_(1)) -#define CPU_IP1 (_ULCAST_(1) << 1) -#define CPU_IP2 (_ULCAST_(1) << 2) -#define CPU_IP3 (_ULCAST_(1) << 3) -#define CPU_IP4 (_ULCAST_(1) << 4) -#define CPU_IP5 (_ULCAST_(1) << 5) -#define CPU_IP6 (_ULCAST_(1) << 6) -#define CPU_IP7 (_ULCAST_(1) << 7) +#define GINTC_VIP_DELTA (INT_HWI0 - CSR_GINTC_VIP_SHIFT) +#define CPU_IP0 BIT(INT_HWI0 - GINTC_VIP_DELTA) +#define CPU_IP1 BIT(INT_HWI1 - GINTC_VIP_DELTA) +#define CPU_IP2 BIT(INT_HWI2 - GINTC_VIP_DELTA) +#define CPU_IP3 BIT(INT_HWI3 - GINTC_VIP_DELTA) +#define CPU_IP4 BIT(INT_HWI4 - GINTC_VIP_DELTA) +#define CPU_IP5 BIT(INT_HWI5 - GINTC_VIP_DELTA) +#define CPU_IP6 BIT(INT_HWI6 - GINTC_VIP_DELTA) +#define CPU_IP7 BIT(INT_HWI7 - GINTC_VIP_DELTA) +#define KVM_GINTC_IRQ_MASK (CPU_IP0 | CPU_IP1 | CPU_IP2 | CPU_IP3 \ + | CPU_IP4 | CPU_IP5 | CPU_IP6 | CPU_IP7) =20 #define MNSEC_PER_SEC (NSEC_PER_SEC >> 20) =20 --=20 2.39.3 From nobody Sun May 24 19:34:49 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 015742475D0; Fri, 22 May 2026 06:49:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779432601; cv=none; b=mfPQVzotdikOK/YdY9Mwe3soFHQd+Bvb0ovIN9R9iER/8QgTVTk96NE16GhvQwK6+Pb5zOP7oKB9rlcB7Qj1/AhRQOapElDvn4XdMIpFqimHVcGdwElKtTTHxr1x1X3xKqsy+PEKuJe3+u9LYROwYrCBU/IbRk1jO/ml0u4zIEk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779432601; c=relaxed/simple; bh=wj/qtmUBFDJXJl+feziJsWCY0e3g91f1/I35t8+55Bk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=po+Z7pYnxMac7PVDWQFZyomoggZXG7Bj48GFSrad5HNTUIfGY5KGcWlz/0mIPt0kszOVDM/sXYQfSX/7liB3XqoHTMgsMxCgEWzYlWBAS46tSQ2S6A+jVs+u8jY5grx9ixsVbrFvvEeCRzFffs4Qx5UGsjslZEohYCcKXkWQyvI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8DxBOmS_A9qW0sMAA--.29721S3; Fri, 22 May 2026 14:49:54 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxjcKS_A9qVE6MAA--.1808S2; Fri, 22 May 2026 14:49:54 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v4 4/5] LoongArch: KVM: Inject interrupt with batch method Date: Fri, 22 May 2026 14:49:44 +0800 Message-Id: <20260522064945.614486-5-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260522064945.614486-1-maobibo@loongson.cn> References: <20260522064945.614486-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxjcKS_A9qVE6MAA--.1808S2 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" With bitmask method, interrupt can be injected with batch mode, rather than one by one. Also remove unused array priority_to_irqp[] here. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/interrupt.c | 95 ++++++++++------------------------ 1 file changed, 28 insertions(+), 67 deletions(-) diff --git a/arch/loongarch/kvm/interrupt.c b/arch/loongarch/kvm/interrupt.c index 48dd56aa4dc5..380aabb3d4d0 100644 --- a/arch/loongarch/kvm/interrupt.c +++ b/arch/loongarch/kvm/interrupt.c @@ -9,39 +9,16 @@ #include #include =20 -static unsigned int priority_to_irq[EXCCODE_INT_NUM] =3D { - [INT_TI] =3D CPU_TIMER, - [INT_IPI] =3D CPU_IPI, - [INT_SWI0] =3D CPU_SIP0, - [INT_SWI1] =3D CPU_SIP1, - [INT_HWI0] =3D CPU_IP0, - [INT_HWI1] =3D CPU_IP1, - [INT_HWI2] =3D CPU_IP2, - [INT_HWI3] =3D CPU_IP3, - [INT_HWI4] =3D CPU_IP4, - [INT_HWI5] =3D CPU_IP5, - [INT_HWI6] =3D CPU_IP6, - [INT_HWI7] =3D CPU_IP7, - [INT_AVEC] =3D CPU_AVEC, -}; - -static int kvm_irq_deliver(struct kvm_vcpu *vcpu, unsigned int priority) +static void kvm_irq_deliver(struct kvm_vcpu *vcpu, unsigned long mask) { - unsigned int irq =3D 0; + unsigned long irq; unsigned long old, new; =20 - clear_bit(priority, &vcpu->arch.irq_pending); - if (priority < EXCCODE_INT_NUM) - irq =3D priority_to_irq[priority]; - - switch (priority) { - case INT_AVEC: - dmsintc_inject_irq(vcpu); - fallthrough; - case INT_TI: - case INT_IPI: - case INT_SWI0: - case INT_SWI1: + irq =3D mask & KVM_ESTAT_IRQ_MASK; + if (irq) { + if (irq & CPU_AVEC) + dmsintc_inject_irq(vcpu); + old =3D kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); set_gcsr_estat(irq); new =3D kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); @@ -49,34 +26,20 @@ static int kvm_irq_deliver(struct kvm_vcpu *vcpu, unsig= ned int priority) /* Inject TI if TVAL inverted */ if (new > old) set_gcsr_estat(CPU_TIMER); - break; - - case INT_HWI0 ... INT_HWI7: - set_csr_gintc(irq); - break; - - default: - break; } =20 - return 1; + irq =3D (mask >> 2) & KVM_GINTC_IRQ_MASK; + if (irq) + set_csr_gintc(irq); } =20 -static int kvm_irq_clear(struct kvm_vcpu *vcpu, unsigned int priority) +static void kvm_irq_clear(struct kvm_vcpu *vcpu, unsigned long mask) { - unsigned int irq =3D 0; + unsigned long irq; unsigned long old, new; =20 - clear_bit(priority, &vcpu->arch.irq_clear); - if (priority < EXCCODE_INT_NUM) - irq =3D priority_to_irq[priority]; - - switch (priority) { - case INT_AVEC: - case INT_TI: - case INT_IPI: - case INT_SWI0: - case INT_SWI1: + irq =3D mask & KVM_ESTAT_IRQ_MASK; + if (irq) { old =3D kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); clear_gcsr_estat(irq); new =3D kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); @@ -84,30 +47,28 @@ static int kvm_irq_clear(struct kvm_vcpu *vcpu, unsigne= d int priority) /* Inject TI if TVAL inverted */ if (new > old) set_gcsr_estat(CPU_TIMER); - break; - - case INT_HWI0 ... INT_HWI7: - clear_csr_gintc(irq); - break; - - default: - break; } =20 - return 1; + irq =3D (mask >> 2) & KVM_GINTC_IRQ_MASK; + if (irq) + clear_csr_gintc(irq); } =20 void kvm_deliver_intr(struct kvm_vcpu *vcpu) { - unsigned int priority; - unsigned long *pending =3D &vcpu->arch.irq_pending; - unsigned long *pending_clr =3D &vcpu->arch.irq_clear; + unsigned long mask; =20 - for_each_set_bit(priority, pending_clr, EXCCODE_INT_NUM) - kvm_irq_clear(vcpu, priority); + mask =3D READ_ONCE(vcpu->arch.irq_clear); + if (mask) { + mask =3D xchg_relaxed(&vcpu->arch.irq_clear, 0); + kvm_irq_clear(vcpu, mask); + } =20 - for_each_set_bit(priority, pending, EXCCODE_INT_NUM) - kvm_irq_deliver(vcpu, priority); + mask =3D READ_ONCE(vcpu->arch.irq_pending); + if (mask) { + mask =3D xchg_relaxed(&vcpu->arch.irq_pending, 0); + kvm_irq_deliver(vcpu, mask); + } } =20 int kvm_pending_timer(struct kvm_vcpu *vcpu) --=20 2.39.3 From nobody Sun May 24 19:34:49 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4D67538947E; Fri, 22 May 2026 06:49:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779432601; cv=none; b=LsIdVhqFp2eAhFi4MRkFRXuoDHY6xwRwTA3fBQzLWXIotnAsgVu6j2VMRBMEbvlUETd9bxK2z0q995iDzxeKbhyIHZOxPpHFr5lTTrXm2we4iQ1xfbFdGxOvxI48r6JxZD1GdsFbIVJdu1HMY5BF5RlWCjLKhc+I3oBWEw5rWZc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779432601; c=relaxed/simple; bh=CBqQxGdIvhIfPBzQFWPT/YD6REeTP3Wo80HuLCKTVNQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=R5vR3jpwnH5xeLkhVXbsEXGyAEc3MuAWyDM4m5xeCHobEUfTsyAufgiSwS9ezznfdHpjujkZ2RS0IXCrGtSYdgODV44iosoNv7eDT4k6ajI6FV2xFL/cSml4yoQU3Bxb0Bzcuuv0EPpBBhjNaV2HNcjEhunf4mp4RS2Jp2JPqb4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxRXiT_A9qX0sMAA--.11269S3; Fri, 22 May 2026 14:49:55 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxjcKS_A9qVE6MAA--.1808S3; Fri, 22 May 2026 14:49:54 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v4 5/5] LoongArch: KVM: Add valid bit check when set ESTAT CSR register Date: Fri, 22 May 2026 14:49:45 +0800 Message-Id: <20260522064945.614486-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260522064945.614486-1-maobibo@loongson.cn> References: <20260522064945.614486-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxjcKS_A9qVE6MAA--.1808S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" When set ESTAT CSR register in function _kvm_setcsr(), valid bit check is added here. Also interrupt CPU_AVEC is checked by msgint feature. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/vcpu.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c index ebd432da3ca4..2bda2d2f7acc 100644 --- a/arch/loongarch/kvm/vcpu.c +++ b/arch/loongarch/kvm/vcpu.c @@ -602,7 +602,7 @@ struct kvm_vcpu *kvm_get_vcpu_by_cpuid(struct kvm *kvm,= int cpuid) =20 static int _kvm_getcsr(struct kvm_vcpu *vcpu, unsigned int id, u64 *val) { - unsigned long gintc; + unsigned long gintc, estat; struct loongarch_csrs *csr =3D vcpu->arch.csr; =20 if (get_gcsr_flag(id) & INVALID_GCSR) @@ -621,8 +621,9 @@ static int _kvm_getcsr(struct kvm_vcpu *vcpu, unsigned = int id, u64 *val) preempt_enable(); =20 /* ESTAT IP0~IP7 get from GINTC */ - gintc =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_GINTC) & 0xff; - *val =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_ESTAT) | (gintc << 2); + gintc =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_GINTC) & KVM_GINTC_IRQ_MAS= K; + estat =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_ESTAT) & ~KVM_ESTAT_HWI_MA= SK; + *val =3D estat | (gintc << 2); return 0; } =20 @@ -637,7 +638,8 @@ static int _kvm_getcsr(struct kvm_vcpu *vcpu, unsigned = int id, u64 *val) =20 static int _kvm_setcsr(struct kvm_vcpu *vcpu, unsigned int id, u64 val) { - int ret =3D 0, gintc; + int ret =3D 0; + unsigned long gintc, estat; struct loongarch_csrs *csr =3D vcpu->arch.csr; =20 if (get_gcsr_flag(id) & INVALID_GCSR) @@ -648,11 +650,15 @@ static int _kvm_setcsr(struct kvm_vcpu *vcpu, unsigne= d int id, u64 val) =20 if (id =3D=3D LOONGARCH_CSR_ESTAT) { /* ESTAT IP0~IP7 inject through GINTC */ - gintc =3D (val >> 2) & 0xff; - kvm_set_sw_gcsr(csr, LOONGARCH_CSR_GINTC, gintc); - - gintc =3D val & ~(0xffUL << 2); - kvm_set_sw_gcsr(csr, LOONGARCH_CSR_ESTAT, gintc); + gintc =3D (val >> 2) & KVM_GINTC_IRQ_MASK; + kvm_write_sw_gcsr(csr, LOONGARCH_CSR_GINTC, gintc); + + /* only set valid ESTAT bits */ + estat =3D val & ~KVM_ESTAT_HWI_MASK; + estat &=3D CSR_ESTAT_IS | CSR_ESTAT_EXC | CSR_ESTAT_ESUBCODE; + if (!kvm_guest_has_msgint(&vcpu->arch)) + estat &=3D ~CPU_AVEC; + kvm_write_sw_gcsr(csr, LOONGARCH_CSR_ESTAT, estat); =20 return ret; } --=20 2.39.3