From nobody Sun May 24 19:33:41 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BA3084039 for ; Fri, 22 May 2026 03:11:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779419512; cv=none; b=kZEKI2uqVaXvtMQdHKA9QKUxpAGP+9eCJLWYxI7m0nKdcAqoqJNC0ltFpaY2TqNWmyE6Z8XopOzYjAt+f11iTMnSy1qsOi/8rubv4Ucv7fdRnIlDILF+jqsKi+KR1Kitkpducpv20dN7NgDBfdroKqusCICQHQsHH/IXySmdXnQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779419512; c=relaxed/simple; bh=CRbTs5UgcIlx5aE76EvpRjynzotkkCEf8cZ8dFsdk68=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=J6C4pcLq6bDpxy3J8WDJdjNOqzVghIFbHNQGSSg046LqeechF+7NKPYg2UB/DO0dnCwZl7bQLodkb0zNX/Ba/BGzIen1WtkcWAQXUNddgsDGgZDBy4XkMVySLg3aXYY6o3YKbm0vqq45SyErmCnV9iFi2uTOSxn7zMWghSYLcrA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=eIeXoGd3; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="eIeXoGd3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1779419510; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6sUm+tYMbIZeehN9wnhHAZ+AqsmFHAZfxn1W+83HFwY=; b=eIeXoGd3KR8eSI1iEG0vWdXLZ0TvgEiBuuo78O4HFWt8x6hHj04xxluwHNUg5bKsOuTbHK JGQIskuayeJnQV8u1uThcRWbdvODKJLIA4POtTDgtR4QtZDDpvTzD48dqv1it9fODPQABZ 9n/okeFUfhoLmg0YWuUzn8369Se6JBY= Received: from mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-304-xlDG_BlsP1acUQpkLPAGCg-1; Thu, 21 May 2026 23:11:43 -0400 X-MC-Unique: xlDG_BlsP1acUQpkLPAGCg-1 X-Mimecast-MFC-AGG-ID: xlDG_BlsP1acUQpkLPAGCg_1779419502 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id C5F0818005B5; Fri, 22 May 2026 03:11:41 +0000 (UTC) Received: from fedora.redhat.com (unknown [10.67.32.61]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 8BD7519560A3; Fri, 22 May 2026 03:11:37 +0000 (UTC) From: Kate Hsuan To: Mauro Carvalho Chehab , Hans de Goede , Hans Verkuil , Sakari Ailus , Serin Yeh Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Kate Hsuan Subject: [PATCH v3 1/3] media: ipu-bridge: Add DMI information of Lenovo X9 to the image upside-down list Date: Fri, 22 May 2026 11:11:19 +0800 Message-ID: <20260522031121.11968-2-hpa@redhat.com> In-Reply-To: <20260522031121.11968-1-hpa@redhat.com> References: <20260522031121.11968-1-hpa@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Content-Type: text/plain; charset="utf-8" The Lenovo X9 has an upside-down-mounted Sony IMX471 sensor so the image was displayed upside-down. Add the DMI information of Lenovo X9 to resolve the issue. Signed-off-by: Kate Hsuan --- drivers/media/pci/intel/ipu-bridge.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/media/pci/intel/ipu-bridge.c b/drivers/media/pci/intel= /ipu-bridge.c index 32cc95a766b7..1c3364451fa3 100644 --- a/drivers/media/pci/intel/ipu-bridge.c +++ b/drivers/media/pci/intel/ipu-bridge.c @@ -118,6 +118,20 @@ static const struct dmi_system_id upside_down_sensor_d= mi_ids[] =3D { }, .driver_data =3D "OVTI02C1", }, + { + .matches =3D { + DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), + DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X9-14"), + }, + .driver_data =3D "SONY471A", + }, + { + .matches =3D { + DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), + DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X9-15"), + }, + .driver_data =3D "SONY471A", + }, {} /* Terminating entry */ }; =20 --=20 2.54.0 From nobody Sun May 24 19:33:41 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDA172C3768 for ; Fri, 22 May 2026 03:11:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779419520; cv=none; b=EMyI1EkpxHN2H2dNFXuK7MgfSoPf9YPI59ctBM4+N7oXMPtjNGAkeMMMKlW7pliII7dC8iHhVItggxiCHlcwK9L385nyLtzffLJHTNcsJLf1UooPM61uTFMUq8eoQVMQpRMcNDrcPYqzntGXhDQbz/KcKEDzL2yIP+J//hSK9dM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779419520; c=relaxed/simple; bh=81pC1MUHqNa8eToiHGWnmE5/PvCjuqNMftHKOGK9mGY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MU2v36Bn51idcGTyZepBunyl5VapFzqOcHhLebqwfYvuMT/AI/q52hqax2FO1usWG1o2Cgv8fi1oTfLuTbMDdYuV1taaHfm1/vfmgX/Pn0PaGMB8R+BuTOtWLGtHx/+Ix2rGAmu+U4++P9ZTWR2FDcmQZrpKi42Y3ta9Qzha14g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=cPc4jGEm; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="cPc4jGEm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1779419517; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6pE7Qb5WnrIFvBG6zZyQKXVQvgXBtTE2ivZjbDAH0a4=; b=cPc4jGEmX/KnFJuwZYaTdrGfT3x8YKnIgnapiUkM7xniuqG26it/b2Fs17YAR0O8HfeUN9 ffEQmGTu4QohJIuk65GJrfmVFfE/tdyx8hWisVHRwg3TIKWsv2cbJ/StsjzgiTSB/gqUOB Eh80uJ2+7M9rL3lyudaGKMwahNL7BeI= Received: from mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-450-n77tyeADPxWkRhzmzNoahw-1; Thu, 21 May 2026 23:11:52 -0400 X-MC-Unique: n77tyeADPxWkRhzmzNoahw-1 X-Mimecast-MFC-AGG-ID: n77tyeADPxWkRhzmzNoahw_1779419509 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 25F70180044D; Fri, 22 May 2026 03:11:49 +0000 (UTC) Received: from fedora.redhat.com (unknown [10.67.32.61]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 33B4F19560A3; Fri, 22 May 2026 03:11:43 +0000 (UTC) From: Kate Hsuan To: Mauro Carvalho Chehab , Hans de Goede , Hans Verkuil , Sakari Ailus , Serin Yeh Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Kate Hsuan Subject: [PATCH v3 2/3] media: i2c: imx471: Add Sony IMX471 image sensor driver Date: Fri, 22 May 2026 11:11:20 +0800 Message-ID: <20260522031121.11968-3-hpa@redhat.com> In-Reply-To: <20260522031121.11968-1-hpa@redhat.com> References: <20260522031121.11968-1-hpa@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Content-Type: text/plain; charset="utf-8" Add a new driver for Sony imx471 camera sensor. It is based on Jimmy Su implementation and the driver can be found in the following URL. https://github.com/intel/ipu6-drivers/commits/master/drivers/media/i2c/imx4= 71.c This sensor can be found on Lenovo X9-14 and X9-15 laptop and it is a part of IPU7 solution. The driver was tested on Lenovo X9-14 and X9-15 laptops. Signed-off-by: Kate Hsuan --- MAINTAINERS | 6 + drivers/media/i2c/Kconfig | 10 + drivers/media/i2c/Makefile | 1 + drivers/media/i2c/imx471.c | 1006 ++++++++++++++++++++++++++++++++++++ 4 files changed, 1023 insertions(+) create mode 100644 drivers/media/i2c/imx471.c diff --git a/MAINTAINERS b/MAINTAINERS index 1126fdd639ad..d597337e7c24 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -24735,6 +24735,12 @@ T: git git://linuxtv.org/media.git F: Documentation/devicetree/bindings/media/i2c/sony,imx415.yaml F: drivers/media/i2c/imx415.c =20 +SONY IMX471 SENSOR DRIVER +M: Kate Hsuan +L: linux-media@vger.kernel.org +S: Maintained +F: drivers/media/i2c/imx471.c + SONY MEMORYSTICK SUBSYSTEM M: Maxim Levitsky M: Alex Dubov diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 5eb1e0e0a87a..1c28c498a9f1 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -287,6 +287,16 @@ config VIDEO_IMX415 To compile this driver as a module, choose M here: the module will be called imx415. =20 +config VIDEO_IMX471 + tristate "Sony IMX471 sensor support" + select V4L2_CCI_I2C + help + This is a Video4Linux2 sensor driver for the Sony + IMX471 camera. + + To compile this driver as a module, choose M here: the + module will be called imx471. + config VIDEO_MAX9271_LIB tristate =20 diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index a3a6396df3c4..0539e9171030 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_VIDEO_IMX335) +=3D imx335.o obj-$(CONFIG_VIDEO_IMX355) +=3D imx355.o obj-$(CONFIG_VIDEO_IMX412) +=3D imx412.o obj-$(CONFIG_VIDEO_IMX415) +=3D imx415.o +obj-$(CONFIG_VIDEO_IMX471) +=3D imx471.o obj-$(CONFIG_VIDEO_IR_I2C) +=3D ir-kbd-i2c.o obj-$(CONFIG_VIDEO_ISL7998X) +=3D isl7998x.o obj-$(CONFIG_VIDEO_KS0127) +=3D ks0127.o diff --git a/drivers/media/i2c/imx471.c b/drivers/media/i2c/imx471.c new file mode 100644 index 000000000000..f3c7fdce2d50 --- /dev/null +++ b/drivers/media/i2c/imx471.c @@ -0,0 +1,1006 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * imx471.c - imx471 sensor driver + * + * Copyright (C) 2025 Intel Corporation + * Copyright (C) 2026 Kate Hsuan + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IMX471_REG_MODE_SELECT CCI_REG8(0x0100) +#define IMX471_MODE_STANDBY 0x00 +#define IMX471_MODE_STREAMING 0x01 + +/* Chip ID */ +#define IMX471_REG_CHIP_ID CCI_REG16(0x0016) +#define IMX471_CHIP_ID 0x0471 + +/* V_TIMING internal */ +#define IMX471_REG_FLL CCI_REG16(0x0340) +#define IMX471_FLL_MAX 0xffff + +/* Exposure control */ +#define IMX471_REG_EXPOSURE CCI_REG16(0x0202) +#define IMX471_EXPOSURE_MIN 1 +#define IMX471_EXPOSURE_STEP 1 +#define IMX471_EXPOSURE_DEFAULT 0x04f6 + +/* + * the digital control register for all color control looks like: + * +-----------------+------------------+ + * | [7:0] | [15:8] | + * +-----------------+------------------+ + * | 0x020f | 0x020e | + * -------------------------------------- + * it is used to calculate the digital gain times value(integral + fracti= onal) + * the [15:8] bits is the fractional part and [7:0] bits is the integral + * calculation equation is: + * gain value (unit: times) =3D REG[15:8] + REG[7:0]/0x100 + * Only value in 0x0100 ~ 0x0FFF range is allowed. + * Analog gain use 10 bits in the registers and allowed range is 0 ~ 960 + */ +/* Analog gain control */ +#define IMX471_REG_ANALOG_GAIN CCI_REG16(0x0204) +#define IMX471_ANA_GAIN_MIN 0 +#define IMX471_ANA_GAIN_MAX 960 +#define IMX471_ANA_GAIN_STEP 1 +#define IMX471_ANA_GAIN_DEFAULT 0 + +/* Digital gain control */ +#define IMX471_REG_DPGA_USE_GLOBAL_GAIN CCI_REG16(0x3ff9) +#define IMX471_REG_DIG_GAIN_GLOBAL CCI_REG16(0x020e) +#define IMX471_DGTL_GAIN_MIN 256 +#define IMX471_DGTL_GAIN_MAX 4095 +#define IMX471_DGTL_GAIN_STEP 1 +#define IMX471_DGTL_GAIN_DEFAULT 256 + +#define IMX471_VALUE_08BIT 1 + +/* HFLIP and VFLIP control */ +#define IMX471_REG_ORIENTATION CCI_REG8(0x0101) +#define IMX471_HFLIP_BIT BIT(0) +#define IMX471_VFLIP_BIT BIT(1) + +/* Default exposure margin */ +#define IMX471_EXPOSURE_MARGIN 18 + +/* Horizontal crop window offset */ +#define IMX471_REG_H_WIN_OFFSET CCI_REG8(0x0409) + +/* Vertical crop window offset */ +#define IMX471_REG_V_WIN_OFFSET CCI_REG8(0x034b) + +/* Test Pattern Control */ +#define IMX471_REG_TEST_PATTERN CCI_REG8(0x0600) +#define IMX471_TEST_PATTERN_DISABLED 0 +#define IMX471_TEST_PATTERN_SOLID_COLOR 1 +#define IMX471_TEST_PATTERN_COLOR_BARS 2 +#define IMX471_TEST_PATTERN_GRAY_COLOR_BARS 3 +#define IMX471_TEST_PATTERN_PN9 4 + +/* default link frequency and external clock */ +#define IMX471_LINK_FREQ_DEFAULT 200000000LL +#define IMX471_EXT_CLK 19200000 +#define IMX471_LINK_FREQ_INDEX 0 + +/* IMX471 native and active pixel array size */ +#define IMX471_NATIVE_WIDTH 4672 +#define IMX471_NATIVE_HEIGHT 3512 +#define IMX471_PIXEL_ARRAY_LEFT 8 +#define IMX471_PIXEL_ARRAY_TOP 8 +#define IMX471_PIXEL_ARRAY_WIDTH 4656 +#define IMX471_PIXEL_ARRAY_HEIGHT 3496 + +#define to_imx471(_sd) container_of_const(_sd, struct imx471, sd) + +static const char * const imx471_supply_name[] =3D { + "avdd", +}; + +#define IMX471_NUM_SUPPLIES ARRAY_SIZE(imx471_supply_name) + +/* Mode : resolution and related config&values */ +struct imx471_mode { + /* Frame width */ + u32 width; + /* Frame height */ + u32 height; + + /* V-timing */ + u32 fll_def; + u32 fll_min; + + /* H-timing */ + u32 llp; + + /* index of link frequency */ + u32 link_freq_index; + + /* Default register values */ + const struct cci_reg_sequence *default_mode_regs; + const int default_mode_regs_length; +}; + +struct imx471 { + struct v4l2_subdev sd; + struct media_pad pad; + + struct v4l2_ctrl_handler ctrl_handler; + /* V4L2 Controls */ + struct v4l2_ctrl *link_freq; + struct v4l2_ctrl *pixel_rate; + struct v4l2_ctrl *vblank; + struct v4l2_ctrl *hblank; + struct v4l2_ctrl *vflip; + struct v4l2_ctrl *hflip; + struct v4l2_ctrl *exposure; + + struct gpio_desc *reset_gpio; + struct regulator_bulk_data supplies[IMX471_NUM_SUPPLIES]; + struct clk *img_clk; + + struct device *dev; + struct regmap *regmap; +}; + +static const struct cci_reg_sequence imx471_global_regs[] =3D { + { CCI_REG8(0x0136), 0x13 }, + { CCI_REG8(0x0137), 0x33 }, + { CCI_REG8(0x3c7e), 0x08 }, + { CCI_REG8(0x3c7f), 0x05 }, + { CCI_REG8(0x3e35), 0x00 }, + { CCI_REG8(0x3e36), 0x00 }, + { CCI_REG8(0x3e37), 0x00 }, + { CCI_REG8(0x3f7f), 0x01 }, + { CCI_REG8(0x4431), 0x04 }, + { CCI_REG8(0x531c), 0x01 }, + { CCI_REG8(0x531d), 0x02 }, + { CCI_REG8(0x531e), 0x04 }, + { CCI_REG8(0x5928), 0x00 }, + { CCI_REG8(0x5929), 0x2f }, + { CCI_REG8(0x592a), 0x00 }, + { CCI_REG8(0x592b), 0x85 }, + { CCI_REG8(0x592c), 0x00 }, + { CCI_REG8(0x592d), 0x32 }, + { CCI_REG8(0x592e), 0x00 }, + { CCI_REG8(0x592f), 0x88 }, + { CCI_REG8(0x5930), 0x00 }, + { CCI_REG8(0x5931), 0x3d }, + { CCI_REG8(0x5932), 0x00 }, + { CCI_REG8(0x5933), 0x93 }, + { CCI_REG8(0x5938), 0x00 }, + { CCI_REG8(0x5939), 0x24 }, + { CCI_REG8(0x593a), 0x00 }, + { CCI_REG8(0x593b), 0x7a }, + { CCI_REG8(0x593c), 0x00 }, + { CCI_REG8(0x593d), 0x24 }, + { CCI_REG8(0x593e), 0x00 }, + { CCI_REG8(0x593f), 0x7a }, + { CCI_REG8(0x5940), 0x00 }, + { CCI_REG8(0x5941), 0x2f }, + { CCI_REG8(0x5942), 0x00 }, + { CCI_REG8(0x5943), 0x85 }, + { CCI_REG8(0x5f0e), 0x6e }, + { CCI_REG8(0x5f11), 0xc6 }, + { CCI_REG8(0x5f17), 0x5e }, + { CCI_REG8(0x7990), 0x01 }, + { CCI_REG8(0x7993), 0x5d }, + { CCI_REG8(0x7994), 0x5d }, + { CCI_REG8(0x7995), 0xa1 }, + { CCI_REG8(0x799a), 0x01 }, + { CCI_REG8(0x799d), 0x00 }, + { CCI_REG8(0x8169), 0x01 }, + { CCI_REG8(0x8359), 0x01 }, + { CCI_REG8(0x9302), 0x1e }, + { CCI_REG8(0x9306), 0x1f }, + { CCI_REG8(0x930a), 0x26 }, + { CCI_REG8(0x930e), 0x23 }, + { CCI_REG8(0x9312), 0x23 }, + { CCI_REG8(0x9316), 0x2c }, + { CCI_REG8(0x9317), 0x19 }, + { CCI_REG8(0xb046), 0x01 }, + { CCI_REG8(0xb048), 0x01 }, +}; + +static const struct cci_reg_sequence mode_1928x1088_regs[] =3D { + { CCI_REG8(0x0101), 0x00 }, + { CCI_REG8(0x0112), 0x0a }, + { CCI_REG8(0x0113), 0x0a }, + { CCI_REG8(0x0114), 0x03 }, + { CCI_REG8(0x0342), 0x0a }, + { CCI_REG8(0x0343), 0x00 }, + { CCI_REG8(0x0340), 0x13 }, + { CCI_REG8(0x0341), 0xb0 }, + { CCI_REG8(0x0344), 0x00 }, + { CCI_REG8(0x0345), 0x00 }, + { CCI_REG8(0x0346), 0x01 }, + { CCI_REG8(0x0347), 0xbc }, + { CCI_REG8(0x0348), 0x12 }, + { CCI_REG8(0x0349), 0x2f }, + { CCI_REG8(0x034a), 0x0b }, + { CCI_REG8(0x034b), 0xeb }, + { CCI_REG8(0x0381), 0x01 }, + { CCI_REG8(0x0383), 0x01 }, + { CCI_REG8(0x0385), 0x01 }, + { CCI_REG8(0x0387), 0x01 }, + { CCI_REG8(0x0900), 0x01 }, + { CCI_REG8(0x0901), 0x22 }, + { CCI_REG8(0x0902), 0x08 }, + { CCI_REG8(0x3f4c), 0x81 }, + { CCI_REG8(0x3f4d), 0x81 }, + { CCI_REG8(0x0408), 0x00 }, + { CCI_REG8(0x0409), 0xc8 }, + { CCI_REG8(0x040a), 0x00 }, + { CCI_REG8(0x040b), 0x6c }, + { CCI_REG8(0x040c), 0x07 }, + { CCI_REG8(0x040d), 0x88 }, + { CCI_REG8(0x040e), 0x04 }, + { CCI_REG8(0x040f), 0x40 }, + { CCI_REG8(0x034c), 0x07 }, + { CCI_REG8(0x034d), 0x88 }, + { CCI_REG8(0x034e), 0x04 }, + { CCI_REG8(0x034f), 0x40 }, + { CCI_REG8(0x0301), 0x06 }, + { CCI_REG8(0x0303), 0x02 }, + { CCI_REG8(0x0305), 0x02 }, + { CCI_REG8(0x0306), 0x00 }, + { CCI_REG8(0x0307), 0x79 }, + { CCI_REG8(0x030b), 0x01 }, + { CCI_REG8(0x030d), 0x02 }, + { CCI_REG8(0x030e), 0x00 }, + { CCI_REG8(0x030f), 0x53 }, + { CCI_REG8(0x0310), 0x01 }, + { CCI_REG8(0x0202), 0x13 }, + { CCI_REG8(0x0203), 0x9e }, + { CCI_REG8(0x0204), 0x00 }, + { CCI_REG8(0x0205), 0x00 }, + { CCI_REG8(0x020e), 0x01 }, + { CCI_REG8(0x020f), 0x00 }, + { CCI_REG8(0x3f78), 0x01 }, + { CCI_REG8(0x3f79), 0x31 }, + { CCI_REG8(0x3ffe), 0x00 }, + { CCI_REG8(0x3fff), 0x8a }, + { CCI_REG8(0x5f0a), 0xb6 }, +}; + +static const char * const imx471_test_pattern_menu[] =3D { + "Disabled", + "Solid Colour", + "Eight Vertical Colour Bars", + "Colour Bars With Fade to Grey", + "Pseudorandom Sequence (PN9)", +}; + +/* + * When adding more than the one below, make sure the disallowed ones will + * actually be disabled in the LINK_FREQ control. + */ +static const s64 link_freq_menu_items[] =3D { + IMX471_LINK_FREQ_DEFAULT, +}; + +/* + * The Bayer formats for the flipping. + * - no flip + * - h flip + * - v flip + * - h and v flips + */ +static const u32 imx471_hv_flips_bayer_order[] =3D { + MEDIA_BUS_FMT_SRGGB10_1X10, + MEDIA_BUS_FMT_SGRBG10_1X10, + MEDIA_BUS_FMT_SGBRG10_1X10, + MEDIA_BUS_FMT_SBGGR10_1X10, +}; + +/* Mode configs */ +static const struct imx471_mode imx471_modes[] =3D { + { + .width =3D 1928, + .height =3D 1088, + .fll_def =3D 1308, + .fll_min =3D 1308, + .llp =3D 2328, + .link_freq_index =3D IMX471_LINK_FREQ_INDEX, + .default_mode_regs =3D mode_1928x1088_regs, + .default_mode_regs_length =3D ARRAY_SIZE(mode_1928x1088_regs), + }, +}; + +static int imx471_get_regulators(struct device *dev, struct imx471 *sensor) +{ + for (unsigned int i =3D 0; i < IMX471_NUM_SUPPLIES; i++) + sensor->supplies[i].supply =3D imx471_supply_name[i]; + + return devm_regulator_bulk_get(dev, IMX471_NUM_SUPPLIES, + sensor->supplies); +} + +static int imx471_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct imx471 *sensor =3D container_of(ctrl->handler, + struct imx471, + ctrl_handler); + struct v4l2_subdev_state *state =3D + v4l2_subdev_get_locked_active_state(&sensor->sd); + const struct v4l2_mbus_framefmt *format =3D + v4l2_subdev_state_get_format(state, 0); + s64 exposure_max; + int ret; + + /* Propagate change of current control to all related controls */ + if (ctrl->id =3D=3D V4L2_CID_VBLANK) { + /* Update max exposure while meeting expected vblanking */ + exposure_max =3D + format->height + ctrl->val - IMX471_EXPOSURE_MARGIN; + __v4l2_ctrl_modify_range(sensor->exposure, + sensor->exposure->minimum, + exposure_max, + sensor->exposure->step, + exposure_max); + } + + /* V4L2 controls values will be applied only when power is already up */ + if (!pm_runtime_get_if_in_use(sensor->dev)) + return 0; + + switch (ctrl->id) { + case V4L2_CID_ANALOGUE_GAIN: + cci_write(sensor->regmap, IMX471_REG_ANALOG_GAIN, + ctrl->val, &ret); + break; + case V4L2_CID_DIGITAL_GAIN: + cci_write(sensor->regmap, IMX471_REG_DIG_GAIN_GLOBAL, + ctrl->val, &ret); + break; + case V4L2_CID_EXPOSURE: + cci_write(sensor->regmap, IMX471_REG_EXPOSURE, + ctrl->val, &ret); + break; + case V4L2_CID_VBLANK: + /* Update FLL that meets expected vertical blanking */ + cci_write(sensor->regmap, IMX471_REG_FLL, + format->height + ctrl->val, &ret); + break; + case V4L2_CID_TEST_PATTERN: + cci_write(sensor->regmap, IMX471_REG_TEST_PATTERN, + ctrl->val, &ret); + break; + case V4L2_CID_HFLIP: + case V4L2_CID_VFLIP: + cci_write(sensor->regmap, IMX471_REG_ORIENTATION, + sensor->hflip->val | sensor->vflip->val << 1, &ret); + break; + default: + ret =3D -EINVAL; + dev_info(sensor->dev, "ctrl(id:0x%x,val:0x%x) is not handled", + ctrl->id, ctrl->val); + break; + } + + pm_runtime_put(sensor->dev); + + return ret; +} + +static const struct v4l2_ctrl_ops imx471_ctrl_ops =3D { + .s_ctrl =3D imx471_set_ctrl, +}; + +static u32 imx471_get_format_code(struct imx471 *sensor) +{ + unsigned int i; + + i =3D (sensor->vflip->val ? 2 : 0) | (sensor->hflip->val ? 1 : 0); + + return imx471_hv_flips_bayer_order[i]; +} + +static int imx471_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct imx471 *sensor =3D to_imx471(sd); + + if (code->index >=3D (ARRAY_SIZE(imx471_hv_flips_bayer_order) / 4)) + return -EINVAL; + + code->code =3D imx471_get_format_code(sensor); + + return 0; +} +static int imx471_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +{ + if (fse->index >=3D ARRAY_SIZE(imx471_modes)) + return -EINVAL; + + fse->min_width =3D imx471_modes[fse->index].width; + fse->max_width =3D fse->min_width; + fse->min_height =3D imx471_modes[fse->index].height; + fse->max_height =3D fse->min_height; + + return 0; +} + +static void imx471_update_pad_format(struct imx471 *sensor, + const struct imx471_mode *mode, + struct v4l2_subdev_format *fmt) +{ + fmt->format.code =3D imx471_get_format_code(sensor); + fmt->format.width =3D mode->width; + fmt->format.height =3D mode->height; + fmt->format.field =3D V4L2_FIELD_NONE; +} + +static int imx471_set_pad_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct imx471 *sensor =3D to_imx471(sd); + const struct imx471_mode *mode; + int h_blank; + u64 pixel_rate; + + mode =3D v4l2_find_nearest_size(imx471_modes, + ARRAY_SIZE(imx471_modes), + width, height, + fmt->format.width, fmt->format.height); + + imx471_update_pad_format(sensor, mode, fmt); + + *v4l2_subdev_state_get_format(sd_state, fmt->pad) =3D fmt->format; + + if (fmt->which =3D=3D V4L2_SUBDEV_FORMAT_TRY) + return 0; + + if (media_entity_is_streaming(&sensor->sd.entity)) + return -EBUSY; + + pixel_rate =3D IMX471_LINK_FREQ_DEFAULT * 2 * 4; + div_u64(pixel_rate, 10); + __v4l2_ctrl_modify_range(sensor->pixel_rate, + V4L2_CID_PIXEL_RATE, + pixel_rate, 1, pixel_rate); + + __v4l2_ctrl_modify_range(sensor->vblank, + mode->fll_min - mode->height, + IMX471_FLL_MAX - mode->height, + 1, + mode->fll_def - mode->height); + + h_blank =3D mode->llp - mode->width; + /* + * Currently hblank is not changeable. + * So FPS control is done only by vblank. + */ + __v4l2_ctrl_modify_range(sensor->hblank, h_blank, + h_blank, 1, h_blank); + + return 0; +} + +static int imx471_get_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_selection *sel) +{ + switch (sel->target) { + case V4L2_SEL_TGT_CROP: + sel->r =3D *v4l2_subdev_state_get_crop(sd_state, sel->pad); + break; + + case V4L2_SEL_TGT_NATIVE_SIZE: + sel->r.top =3D 0; + sel->r.left =3D 0; + sel->r.width =3D IMX471_NATIVE_WIDTH; + sel->r.height =3D IMX471_NATIVE_HEIGHT; + return 0; + + case V4L2_SEL_TGT_CROP_DEFAULT: + case V4L2_SEL_TGT_CROP_BOUNDS: + sel->r.top =3D IMX471_PIXEL_ARRAY_TOP; + sel->r.left =3D IMX471_PIXEL_ARRAY_LEFT; + sel->r.width =3D IMX471_PIXEL_ARRAY_WIDTH; + sel->r.height =3D IMX471_PIXEL_ARRAY_HEIGHT; + return 0; + } + + return -EINVAL; +} + +static int imx471_init_state(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state) +{ + struct v4l2_subdev_format fmt =3D { + .which =3D V4L2_SUBDEV_FORMAT_ACTIVE, + .format =3D { + .code =3D MEDIA_BUS_FMT_SRGGB10_1X10, + .width =3D imx471_modes[0].width, + .height =3D imx471_modes[0].height, + }, + }; + + imx471_set_pad_format(sd, sd_state, &fmt); + + return 0; +} + +static int imx471_identify_module(struct imx471 *sensor) +{ + int ret; + u64 val; + + ret =3D cci_read(sensor->regmap, IMX471_REG_CHIP_ID, &val, NULL); + if (ret) + return dev_err_probe(sensor->dev, ret, + "failed to read chip id\n"); + + if (val !=3D IMX471_CHIP_ID) + return dev_err_probe(sensor->dev, -EIO, + "chip id mismatch: %x!=3D%llx\n", + IMX471_CHIP_ID, val); + + return 0; +} + +static int imx471_power_off(struct device *dev) +{ + struct v4l2_subdev *sd =3D dev_get_drvdata(dev); + struct imx471 *sensor =3D to_imx471(sd); + + clk_disable_unprepare(sensor->img_clk); + gpiod_set_value_cansleep(sensor->reset_gpio, 1); + + regulator_bulk_disable(IMX471_NUM_SUPPLIES, sensor->supplies); + + return 0; +} + +static int imx471_power_on(struct device *dev) +{ + struct v4l2_subdev *sd =3D dev_get_drvdata(dev); + struct imx471 *sensor =3D to_imx471(sd); + int ret; + + ret =3D regulator_bulk_enable(IMX471_NUM_SUPPLIES, sensor->supplies); + if (ret < 0) { + dev_err(dev, "failed to enable regulators: %d\n", ret); + return ret; + } + + ret =3D clk_prepare_enable(sensor->img_clk); + if (ret < 0) { + regulator_bulk_disable(IMX471_NUM_SUPPLIES, sensor->supplies); + dev_err(dev, "failed to enable imaging clock: %d", ret); + return ret; + } + + gpiod_set_value_cansleep(sensor->reset_gpio, 0); + + usleep_range(10000, 15000); + + return 0; +} + +/* Start streaming */ +static int imx471_enable_stream(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + u32 pad, u64 streams_mask) +{ + struct imx471 *sensor =3D to_imx471(sd); + const struct imx471_mode *mode; + struct v4l2_mbus_framefmt *fmt; + int ret; + + ret =3D pm_runtime_resume_and_get(sensor->dev); + if (ret) + goto error_powerdown; + + ret =3D imx471_identify_module(sensor); + if (ret) + return ret; + + /* Global Setting */ + cci_multi_reg_write(sensor->regmap, imx471_global_regs, + ARRAY_SIZE(imx471_global_regs), &ret); + if (ret) { + dev_err(sensor->dev, "failed to set global settings"); + goto error_powerdown; + } + + state =3D v4l2_subdev_get_locked_active_state(&sensor->sd); + fmt =3D v4l2_subdev_state_get_format(state, 0); + mode =3D v4l2_find_nearest_size(imx471_modes, ARRAY_SIZE(imx471_modes), + width, height, fmt->width, fmt->height); + + /* Apply default values of current mode */ + cci_multi_reg_write(sensor->regmap, mode->default_mode_regs, + mode->default_mode_regs_length, &ret); + if (ret) { + dev_err(sensor->dev, "failed to set mode"); + goto error_powerdown; + } + + /* set digital gain control to all color mode */ + cci_write(sensor->regmap, IMX471_REG_DPGA_USE_GLOBAL_GAIN, 1, &ret); + if (ret) + goto error_powerdown; + + /* Apply customized values from user */ + ret =3D __v4l2_ctrl_handler_setup(&sensor->ctrl_handler); + if (ret) + goto error_powerdown; + + cci_write(sensor->regmap, IMX471_REG_MODE_SELECT, + IMX471_MODE_STREAMING, &ret); + if (ret) + goto error_powerdown; + + __v4l2_ctrl_grab(sensor->vflip, true); + __v4l2_ctrl_grab(sensor->hflip, true); + + return ret; + +error_powerdown: + pm_runtime_put(sensor->dev); + + return ret; +} + +/* Stop streaming */ +static int imx471_disable_stream(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + u32 pad, u64 streams_mask) +{ + struct imx471 *sensor =3D to_imx471(sd); + int ret; + + cci_write(sensor->regmap, IMX471_REG_MODE_SELECT, + IMX471_MODE_STANDBY, &ret); + pm_runtime_put(sensor->dev); + + if (ret) + dev_err(sensor->dev, + "failed to disable stream with return value: %d\n", + ret); + __v4l2_ctrl_grab(sensor->vflip, false); + __v4l2_ctrl_grab(sensor->hflip, false); + + return 0; +} + +static const struct v4l2_subdev_core_ops imx471_subdev_core_ops =3D { + .subscribe_event =3D v4l2_ctrl_subdev_subscribe_event, + .unsubscribe_event =3D v4l2_event_subdev_unsubscribe, +}; + +static const struct v4l2_subdev_video_ops imx471_video_ops =3D { + .s_stream =3D v4l2_subdev_s_stream_helper, +}; + +static const struct v4l2_subdev_pad_ops imx471_pad_ops =3D { + .enum_mbus_code =3D imx471_enum_mbus_code, + .get_fmt =3D v4l2_subdev_get_fmt, + .set_fmt =3D imx471_set_pad_format, + .get_selection =3D imx471_get_selection, + .enum_frame_size =3D imx471_enum_frame_size, + .enable_streams =3D imx471_enable_stream, + .disable_streams =3D imx471_disable_stream, +}; + +static const struct v4l2_subdev_ops imx471_subdev_ops =3D { + .core =3D &imx471_subdev_core_ops, + .video =3D &imx471_video_ops, + .pad =3D &imx471_pad_ops, +}; + +static const struct v4l2_subdev_internal_ops imx471_internal_ops =3D { + .init_state =3D imx471_init_state, +}; + +/* Initialize control handlers */ +static int imx471_init_controls(struct imx471 *sensor) +{ + const struct imx471_mode *mode =3D &imx471_modes[0]; + struct v4l2_ctrl_handler *ctrl_hdlr; + struct v4l2_fwnode_device_properties props; + s64 exposure_max, hblank; + u64 pixel_rate; + int ret; + + ctrl_hdlr =3D &sensor->ctrl_handler; + ret =3D v4l2_ctrl_handler_init(ctrl_hdlr, 10); + if (ret) + return ret; + + ret =3D v4l2_fwnode_device_parse(sensor->dev, &props); + if (ret) { + dev_err(sensor->dev, "failed to parse fwnode: %d", ret); + return ret; + } + + v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx471_ctrl_ops, &props); + + sensor->link_freq =3D v4l2_ctrl_new_int_menu(ctrl_hdlr, + &imx471_ctrl_ops, + V4L2_CID_LINK_FREQ, + ARRAY_SIZE(link_freq_menu_items) - 1, + 0, + link_freq_menu_items); + if (sensor->link_freq) + sensor->link_freq->flags |=3D V4L2_CTRL_FLAG_READ_ONLY; + + /* pixel_rate =3D link_freq * 2 * nr_of_lanes / bits_per_sample */ + pixel_rate =3D IMX471_LINK_FREQ_DEFAULT * 2 * 4; + div_u64(pixel_rate, 10); + /* By default, PIXEL_RATE is read only */ + sensor->pixel_rate =3D v4l2_ctrl_new_std(ctrl_hdlr, &imx471_ctrl_ops, + V4L2_CID_PIXEL_RATE, pixel_rate, + pixel_rate, 1, pixel_rate); + + /* Initial vblank/hblank/exposure parameters based on current mode */ + sensor->vblank =3D v4l2_ctrl_new_std(ctrl_hdlr, + &imx471_ctrl_ops, + V4L2_CID_VBLANK, + mode->fll_min - mode->height, + IMX471_FLL_MAX - mode->height, + 1, + mode->fll_def - mode->height); + + hblank =3D mode->llp - mode->width; + sensor->hblank =3D v4l2_ctrl_new_std(ctrl_hdlr, &imx471_ctrl_ops, + V4L2_CID_HBLANK, hblank, hblank, + 1, hblank); + if (sensor->hblank) + sensor->hblank->flags |=3D V4L2_CTRL_FLAG_READ_ONLY; + + /* fll >=3D exposure time + adjust parameter (default value is 18) */ + exposure_max =3D mode->fll_def - IMX471_EXPOSURE_MARGIN; + sensor->exposure =3D v4l2_ctrl_new_std(ctrl_hdlr, &imx471_ctrl_ops, + V4L2_CID_EXPOSURE, + IMX471_EXPOSURE_MIN, exposure_max, + IMX471_EXPOSURE_STEP, + IMX471_EXPOSURE_DEFAULT); + + v4l2_ctrl_new_std(ctrl_hdlr, &imx471_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, + IMX471_ANA_GAIN_MIN, IMX471_ANA_GAIN_MAX, + IMX471_ANA_GAIN_STEP, IMX471_ANA_GAIN_DEFAULT); + + /* Digital gain */ + v4l2_ctrl_new_std(ctrl_hdlr, &imx471_ctrl_ops, V4L2_CID_DIGITAL_GAIN, + IMX471_DGTL_GAIN_MIN, IMX471_DGTL_GAIN_MAX, + IMX471_DGTL_GAIN_STEP, IMX471_DGTL_GAIN_DEFAULT); + + v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx471_ctrl_ops, + V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(imx471_test_pattern_menu) - 1, + 0, 0, imx471_test_pattern_menu); + + /* HFLIP & VFLIP */ + sensor->hflip =3D v4l2_ctrl_new_std(ctrl_hdlr, &imx471_ctrl_ops, + V4L2_CID_HFLIP, 0, 1, 1, 0); + + sensor->vflip =3D v4l2_ctrl_new_std(ctrl_hdlr, &imx471_ctrl_ops, + V4L2_CID_VFLIP, 0, 1, 1, 0); + + if (ctrl_hdlr->error) { + dev_err(sensor->dev, "%s control init failed: %d", + __func__, ctrl_hdlr->error); + goto error; + } + + sensor->hflip->flags |=3D V4L2_CTRL_FLAG_MODIFY_LAYOUT; + sensor->vflip->flags |=3D V4L2_CTRL_FLAG_MODIFY_LAYOUT; + + sensor->sd.ctrl_handler =3D ctrl_hdlr; + + return 0; + +error: + v4l2_ctrl_handler_free(ctrl_hdlr); + + return ctrl_hdlr->error; +} + +static int imx471_check_hwcfg(struct imx471 *sensor) +{ + struct v4l2_fwnode_endpoint bus_cfg =3D { + .bus_type =3D V4L2_MBUS_CSI2_DPHY, + }; + struct fwnode_handle *ep, *fwnode =3D dev_fwnode(sensor->dev); + struct clk *clk; + unsigned long link_freq_bitmap; + int ret; + + clk =3D devm_v4l2_sensor_clk_get(sensor->dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(sensor->dev, PTR_ERR(clk), + "can't get clock frequency\n"); + + if (clk_get_rate(clk) !=3D IMX471_EXT_CLK) + return dev_err_probe(sensor->dev, -EINVAL, + "external clock %lu is not supported\n", + clk_get_rate(clk)); + + ep =3D fwnode_graph_get_endpoint_by_id(fwnode, 0, 0, 0); + ret =3D v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); + fwnode_handle_put(ep); + if (ret) + return dev_err_probe(sensor->dev, ret, + "parsing endpoint failed"); + + ret =3D v4l2_link_freq_to_bitmap(sensor->dev, bus_cfg.link_frequencies, + bus_cfg.nr_of_link_frequencies, + link_freq_menu_items, + ARRAY_SIZE(link_freq_menu_items), + &link_freq_bitmap); + + v4l2_fwnode_endpoint_free(&bus_cfg); + + return ret; +} + +static int imx471_probe(struct i2c_client *client) +{ + struct imx471 *sensor; + int ret; + + sensor =3D devm_kzalloc(&client->dev, sizeof(*sensor), GFP_KERNEL); + if (!sensor) + return dev_err_probe(&client->dev, -ENOMEM, + "failed to allocate memory\n"); + + sensor->dev =3D &client->dev; + + /* Check HW config */ + ret =3D imx471_check_hwcfg(sensor); + if (ret) + return dev_err_probe(sensor->dev, ret, + "failed to check hwcfg: %d\n", ret); + + ret =3D imx471_get_regulators(sensor->dev, sensor); + if (ret) + return dev_err_probe(sensor->dev, ret, + "failed to get regulators\n"); + + sensor->reset_gpio =3D devm_gpiod_get_optional(sensor->dev, "reset", + GPIOD_OUT_HIGH); + if (IS_ERR(sensor->reset_gpio)) + return dev_err_probe(sensor->dev, PTR_ERR(sensor->reset_gpio), + "failed to get reset gpio\n"); + + sensor->img_clk =3D devm_clk_get_optional(sensor->dev, NULL); + if (IS_ERR(sensor->img_clk)) + return dev_err_probe(sensor->dev, PTR_ERR(sensor->img_clk), + "failed to get imaging clock\n"); + + /* Initialize subdev */ + v4l2_i2c_subdev_init(&sensor->sd, client, &imx471_subdev_ops); + + /* Initialize regmap */ + sensor->regmap =3D devm_cci_regmap_init_i2c(client, 16); + if (IS_ERR(sensor->regmap)) + return PTR_ERR(sensor->regmap); + + ret =3D imx471_power_on(sensor->dev); + if (ret) + return dev_err_probe(sensor->dev, ret, + "failed to power on\n"); + + /* Check module identity */ + ret =3D imx471_identify_module(sensor); + if (ret) { + dev_err(&client->dev, "failed to find sensor: %d", ret); + goto error_power_off; + } + + ret =3D imx471_init_controls(sensor); + if (ret) { + dev_err(sensor->dev, "failed to init controls: %d", ret); + goto error_power_off; + } + + /* Initialize subdev */ + sensor->sd.internal_ops =3D &imx471_internal_ops; + sensor->sd.flags |=3D V4L2_SUBDEV_FL_HAS_DEVNODE | + V4L2_SUBDEV_FL_HAS_EVENTS; + sensor->sd.entity.function =3D MEDIA_ENT_F_CAM_SENSOR; + + /* Initialize source pad */ + sensor->pad.flags =3D MEDIA_PAD_FL_SOURCE; + ret =3D media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad); + if (ret) { + dev_err(&client->dev, "failed to init entity pads: %d", ret); + goto error_v4l2_ctrl_handler_free; + } + + sensor->sd.state_lock =3D sensor->ctrl_handler.lock; + ret =3D v4l2_subdev_init_finalize(&sensor->sd); + if (ret < 0) { + dev_err(&client->dev, "failed to init subdev: %d", ret); + goto error_media_entity_pm; + } + + pm_runtime_set_active(sensor->dev); + pm_runtime_enable(sensor->dev); + pm_runtime_idle(sensor->dev); + + ret =3D v4l2_async_register_subdev_sensor(&sensor->sd); + if (ret < 0) + goto error_v4l2_subdev_cleanup; + + return 0; + +error_v4l2_subdev_cleanup: + pm_runtime_disable(sensor->dev); + pm_runtime_set_suspended(sensor->dev); + v4l2_subdev_cleanup(&sensor->sd); + +error_media_entity_pm: + media_entity_cleanup(&sensor->sd.entity); + +error_v4l2_ctrl_handler_free: + v4l2_ctrl_handler_free(sensor->sd.ctrl_handler); + +error_power_off: + imx471_power_off(sensor->dev); + + return ret; +} + +static void imx471_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd =3D i2c_get_clientdata(client); + struct imx471 *sensor =3D to_imx471(sd); + + v4l2_async_unregister_subdev(sd); + v4l2_subdev_cleanup(sd); + media_entity_cleanup(&sd->entity); + v4l2_ctrl_handler_free(sd->ctrl_handler); + + pm_runtime_disable(&client->dev); + + if (!pm_runtime_status_suspended(sensor->dev)) { + imx471_power_off(sensor->dev); + pm_runtime_set_suspended(sensor->dev); + } +} + +static DEFINE_RUNTIME_DEV_PM_OPS(imx471_pm_ops, imx471_power_off, + imx471_power_on, NULL); + +static const struct acpi_device_id imx471_acpi_ids[] __maybe_unused =3D { + { "SONY471A" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(acpi, imx471_acpi_ids); + +static struct i2c_driver imx471_i2c_driver =3D { + .driver =3D { + .name =3D "imx471", + .acpi_match_table =3D ACPI_PTR(imx471_acpi_ids), + .pm =3D pm_sleep_ptr(&imx471_pm_ops), + }, + .probe =3D imx471_probe, + .remove =3D imx471_remove, +}; +module_i2c_driver(imx471_i2c_driver); + +MODULE_AUTHOR("Jimmy Su "); +MODULE_AUTHOR("Serin Yeh "); +MODULE_AUTHOR("Kate Hsuan "); +MODULE_DESCRIPTION("Sony imx471 sensor driver"); +MODULE_LICENSE("GPL"); --=20 2.54.0 From nobody Sun May 24 19:33:41 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client 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[10.67.32.61]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 0FC0819560A3; Fri, 22 May 2026 03:11:50 +0000 (UTC) From: Kate Hsuan To: Mauro Carvalho Chehab , Hans de Goede , Hans Verkuil , Sakari Ailus , Serin Yeh Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Kate Hsuan Subject: [PATCH v3 3/3] media: i2c: imx471: Naming the register Date: Fri, 22 May 2026 11:11:21 +0800 Message-ID: <20260522031121.11968-4-hpa@redhat.com> In-Reply-To: <20260522031121.11968-1-hpa@redhat.com> References: <20260522031121.11968-1-hpa@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Content-Type: text/plain; charset="utf-8" Name the register addresses and set up the value with correct value length. Signed-off-by: Kate Hsuan --- drivers/media/i2c/imx471.c | 96 ++++++++++++++++++++------------------ 1 file changed, 50 insertions(+), 46 deletions(-) diff --git a/drivers/media/i2c/imx471.c b/drivers/media/i2c/imx471.c index f3c7fdce2d50..e8bc3487370f 100644 --- a/drivers/media/i2c/imx471.c +++ b/drivers/media/i2c/imx471.c @@ -76,12 +76,6 @@ /* Default exposure margin */ #define IMX471_EXPOSURE_MARGIN 18 =20 -/* Horizontal crop window offset */ -#define IMX471_REG_H_WIN_OFFSET CCI_REG8(0x0409) - -/* Vertical crop window offset */ -#define IMX471_REG_V_WIN_OFFSET CCI_REG8(0x034b) - /* Test Pattern Control */ #define IMX471_REG_TEST_PATTERN CCI_REG8(0x0600) #define IMX471_TEST_PATTERN_DISABLED 0 @@ -103,6 +97,32 @@ #define IMX471_PIXEL_ARRAY_WIDTH 4656 #define IMX471_PIXEL_ARRAY_HEIGHT 3496 =20 +#define IMX471_REG_EXCK_FREQ CCI_REG16(0x0136) +#define IMX471_EXCK_FREQ(n) ((n) * 256) /* n in MHz */ + +#define IMX471_REG_CSI_DATA_FORMAT CCI_REG16(0x0112) +#define IMX471_CSI_DATA_FORMAT_RAW10 0x0a0a + +#define IMX471_REG_CSI_LANE_MODE CCI_REG8(0x0114) +#define IMX471_CSI_2_LANE_MODE 1 +#define IMX471_CSI_4_LANE_MODE 3 + +#define IMX471_REG_X_ADD_STA CCI_REG16(0x0344) +#define IMX471_REG_Y_ADD_STA CCI_REG16(0x0346) +#define IMX471_REG_X_ADD_END CCI_REG16(0x0348) +#define IMX471_REG_Y_ADD_END CCI_REG16(0x034a) +#define IMX471_REG_X_OUTPUT_SIZE CCI_REG16(0x034c) +#define IMX471_REG_Y_OUTPUT_SIZE CCI_REG16(0x034e) +#define IMX471_REG_X_EVEN_INC CCI_REG8(0x0381) +#define IMX471_REG_X_ODD_INC CCI_REG8(0x0383) +#define IMX471_REG_Y_EVEN_INC CCI_REG8(0x0385) +#define IMX471_REG_Y_ODD_INC CCI_REG8(0x0387) + +#define IMX471_REG_DIG_CROP_X_OFFSET CCI_REG16(0x0408) +#define IMX471_REG_DIG_CROP_Y_OFFSET CCI_REG16(0x040a) +#define IMX471_REG_DIG_CROP_WIDTH CCI_REG16(0x040c) +#define IMX471_REG_DIG_CROP_HEIGHT CCI_REG16(0x040e) + #define to_imx471(_sd) container_of_const(_sd, struct imx471, sd) =20 static const char * const imx471_supply_name[] =3D { @@ -156,8 +176,7 @@ struct imx471 { }; =20 static const struct cci_reg_sequence imx471_global_regs[] =3D { - { CCI_REG8(0x0136), 0x13 }, - { CCI_REG8(0x0137), 0x33 }, + { IMX471_REG_EXCK_FREQ, IMX471_EXCK_FREQ(19.2) }, { CCI_REG8(0x3c7e), 0x08 }, { CCI_REG8(0x3c7f), 0x05 }, { CCI_REG8(0x3e35), 0x00 }, @@ -215,43 +234,29 @@ static const struct cci_reg_sequence imx471_global_re= gs[] =3D { }; =20 static const struct cci_reg_sequence mode_1928x1088_regs[] =3D { - { CCI_REG8(0x0101), 0x00 }, - { CCI_REG8(0x0112), 0x0a }, - { CCI_REG8(0x0113), 0x0a }, - { CCI_REG8(0x0114), 0x03 }, + { IMX471_REG_ORIENTATION, 0x00 }, + { IMX471_REG_CSI_DATA_FORMAT, IMX471_CSI_DATA_FORMAT_RAW10 }, + { IMX471_REG_CSI_LANE_MODE, IMX471_CSI_4_LANE_MODE }, { CCI_REG8(0x0342), 0x0a }, { CCI_REG8(0x0343), 0x00 }, - { CCI_REG8(0x0340), 0x13 }, - { CCI_REG8(0x0341), 0xb0 }, - { CCI_REG8(0x0344), 0x00 }, - { CCI_REG8(0x0345), 0x00 }, - { CCI_REG8(0x0346), 0x01 }, - { CCI_REG8(0x0347), 0xbc }, - { CCI_REG8(0x0348), 0x12 }, - { CCI_REG8(0x0349), 0x2f }, - { CCI_REG8(0x034a), 0x0b }, - { CCI_REG8(0x034b), 0xeb }, - { CCI_REG8(0x0381), 0x01 }, - { CCI_REG8(0x0383), 0x01 }, - { CCI_REG8(0x0385), 0x01 }, - { CCI_REG8(0x0387), 0x01 }, + { IMX471_REG_FLL, 0x13b0 }, + { IMX471_REG_X_ADD_STA, 8 }, + { IMX471_REG_Y_ADD_STA, 444 }, + { IMX471_REG_X_ADD_END, 4647 }, + { IMX471_REG_Y_ADD_END, 3051 }, + { IMX471_REG_X_EVEN_INC, 1 }, + { IMX471_REG_X_ODD_INC, 1 }, + { IMX471_REG_Y_EVEN_INC, 1 }, + { IMX471_REG_Y_ODD_INC, 1 }, { CCI_REG8(0x0900), 0x01 }, { CCI_REG8(0x0901), 0x22 }, { CCI_REG8(0x0902), 0x08 }, - { CCI_REG8(0x3f4c), 0x81 }, - { CCI_REG8(0x3f4d), 0x81 }, - { CCI_REG8(0x0408), 0x00 }, - { CCI_REG8(0x0409), 0xc8 }, - { CCI_REG8(0x040a), 0x00 }, - { CCI_REG8(0x040b), 0x6c }, - { CCI_REG8(0x040c), 0x07 }, - { CCI_REG8(0x040d), 0x88 }, - { CCI_REG8(0x040e), 0x04 }, - { CCI_REG8(0x040f), 0x40 }, - { CCI_REG8(0x034c), 0x07 }, - { CCI_REG8(0x034d), 0x88 }, - { CCI_REG8(0x034e), 0x04 }, - { CCI_REG8(0x034f), 0x40 }, + { IMX471_REG_DIG_CROP_X_OFFSET, 208 }, + { IMX471_REG_DIG_CROP_Y_OFFSET, 108 }, + { IMX471_REG_DIG_CROP_WIDTH, 1928 }, + { IMX471_REG_DIG_CROP_HEIGHT, 1088 }, + { IMX471_REG_X_OUTPUT_SIZE, 1928 }, + { IMX471_REG_Y_OUTPUT_SIZE, 1088 }, { CCI_REG8(0x0301), 0x06 }, { CCI_REG8(0x0303), 0x02 }, { CCI_REG8(0x0305), 0x02 }, @@ -262,12 +267,11 @@ static const struct cci_reg_sequence mode_1928x1088_r= egs[] =3D { { CCI_REG8(0x030e), 0x00 }, { CCI_REG8(0x030f), 0x53 }, { CCI_REG8(0x0310), 0x01 }, - { CCI_REG8(0x0202), 0x13 }, - { CCI_REG8(0x0203), 0x9e }, - { CCI_REG8(0x0204), 0x00 }, - { CCI_REG8(0x0205), 0x00 }, - { CCI_REG8(0x020e), 0x01 }, - { CCI_REG8(0x020f), 0x00 }, + { IMX471_REG_EXPOSURE, 5022 }, + { IMX471_REG_ANALOG_GAIN, 0 }, + { IMX471_REG_DIG_GAIN_GLOBAL, 256 }, + { CCI_REG8(0x3f4c), 0x81 }, + { CCI_REG8(0x3f4d), 0x81 }, { CCI_REG8(0x3f78), 0x01 }, { CCI_REG8(0x3f79), 0x31 }, { CCI_REG8(0x3ffe), 0x00 }, --=20 2.54.0