From nobody Sun May 24 20:33:05 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C620B220F3E; Fri, 22 May 2026 02:21:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779416521; cv=none; b=s9wAOWA5vGHZcPFbPe/dEzs79eCBsJi7klgMWtG+o0tAFX3yVGt77Hr+7ZRvfEO/kR1sZFcIKqCQJxRrUGBWIvfWHf9tYW3jADEMvanyy6e/u+MGgROGDUr2uVLXdJg6xBkIvzWfxyXJyErFNJb1IgZ3XWF149LcDjBfwedz6tU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779416521; c=relaxed/simple; bh=fYU0zGHiGtxlVCCoAo+7bJL5ghw7FQLLKSEl/IrE5Jc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZZQUXEEdmyQHq+j3djdw5lrpvbdaxIFmRJp5TL13ak53xpuf0bmbdgFBJNKkoQXPy7c+EJtqWLc2ail8xhiKX8mXYHLrujdxQKmZFxU4m6HtDXlIoyjAIp/n+yP0ajxJZP8KTW+qIVswhsJVsBpGo+CAgYz+cFM4wizs7OaNnLE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=lRGIcaCF; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="lRGIcaCF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779416520; x=1810952520; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fYU0zGHiGtxlVCCoAo+7bJL5ghw7FQLLKSEl/IrE5Jc=; b=lRGIcaCFXE94uUCTJP3GnjGUl0XK3QNYicxnBP76qIgtTQJe8TEf5eQf olX0k+oQyFq1o1dRN+OvwBIwNAOzIgD0Oe5Ukop5cPW9HaqRE+RPC8KsR Z9pshjk/PnSsW7Pllf1SEoXIU70YYYncKfKNFmZlJzS9D7DJ5Y7B/ZVgM fUKX78cBgTnFmjWXTFIBVMKyRHcqtkKeWYupj55XvZUSbypAasIQragDo Vv5YsTVoVi7pOr/D+wjUkScpFkrlFw7iNpcbmVzjdK2/edfaaf8LK0VFT XkCTnQvDRdVwFgbP0gwGlZrhiNiEJZqF+wGIz1nh+VJA9LHOaauwchzey A==; X-CSE-ConnectionGUID: Hw8vLSR6RYGjOvq7NMfASQ== X-CSE-MsgGUID: J56a912qR86n6kpmagD28A== X-IronPort-AV: E=McAfee;i="6800,10657,11793"; a="80400513" X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="80400513" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:21:58 -0700 X-CSE-ConnectionGUID: JfVMwlgtQLet9IANxKrF3Q== X-CSE-MsgGUID: 0s/IAb32QWWNNwuourRhww== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="236335367" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:21:58 -0700 From: "David E. Box" To: Rajneesh Bhardwaj , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Hans de Goede Cc: "David E. Box" , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Xi Pardee , Srinivas Pandruvada Subject: [PATCH v5 01/16] platform/x86/intel/pmt: Add pre/post decode hooks around header parsing Date: Thu, 21 May 2026 19:21:31 -0700 Message-ID: <20260522022147.4137494-2-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522022147.4137494-1-david.e.box@linux.intel.com> References: <20260522022147.4137494-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add optional pre- and post-decode callbacks to the PMT class so namespaces can perform setup and cleanup steps around header parsing. - Add pmt_pre_decode() and pmt_post_decode() to struct intel_pmt_namespace. - Update intel_pmt_dev_create() to invoke, in order: pre =E2=86=92 header_decode() =E2=86=92 post. - Keep the existing pmt_header_decode() callback unchanged. No functional changes. This adds flexibility for upcoming decoders while preserving current behavior. Signed-off-by: David E. Box Reviewed-by: Ilpo J=C3=A4rvinen --- V5 - No changes V4 - No changes V3 - No changes V2 - No changes drivers/platform/x86/intel/pmt/class.c | 12 ++++++++++++ drivers/platform/x86/intel/pmt/class.h | 4 ++++ 2 files changed, 16 insertions(+) diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/= intel/pmt/class.c index b4c9964df807..9b315334a69b 100644 --- a/drivers/platform/x86/intel/pmt/class.c +++ b/drivers/platform/x86/intel/pmt/class.c @@ -381,10 +381,22 @@ int intel_pmt_dev_create(struct intel_pmt_entry *entr= y, struct intel_pmt_namespa if (IS_ERR(entry->disc_table)) return PTR_ERR(entry->disc_table); =20 + if (ns->pmt_pre_decode) { + ret =3D ns->pmt_pre_decode(intel_vsec_dev, entry); + if (ret) + return ret; + } + ret =3D ns->pmt_header_decode(entry, dev); if (ret) return ret; =20 + if (ns->pmt_post_decode) { + ret =3D ns->pmt_post_decode(intel_vsec_dev, entry); + if (ret) + return ret; + } + ret =3D intel_pmt_populate_entry(entry, intel_vsec_dev, disc_res); if (ret) return ret; diff --git a/drivers/platform/x86/intel/pmt/class.h b/drivers/platform/x86/= intel/pmt/class.h index 1ae56a5baad2..ff39014b208c 100644 --- a/drivers/platform/x86/intel/pmt/class.h +++ b/drivers/platform/x86/intel/pmt/class.h @@ -62,6 +62,10 @@ struct intel_pmt_namespace { struct xarray *xa; int (*pmt_header_decode)(struct intel_pmt_entry *entry, struct device *dev); + int (*pmt_pre_decode)(struct intel_vsec_device *ivdev, + struct intel_pmt_entry *entry); + int (*pmt_post_decode)(struct intel_vsec_device *ivdev, + struct intel_pmt_entry *entry); int (*pmt_add_endpoint)(struct intel_vsec_device *ivdev, struct intel_pmt_entry *entry); }; --=20 2.43.0 From nobody Sun May 24 20:33:05 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C50D32DEA86; Fri, 22 May 2026 02:22:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779416522; cv=none; b=WlvNEu2xmmRGqcXNe7Pm8xdXyXFvsUCT35qf54qCz6ttPyYOIhWc0f/YOKjZYStS9jhjfvUjnn7qsejm0xkZchNhVhJX6UU01O7XEOYwUYdlJ9J4zob2ERtb/w3XH1x8xSx0z4jRxUfh1WYBtbk+GdYMncQpZVbPCYMqftzSsfw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779416522; c=relaxed/simple; bh=upmFG+tdOWBNRk1ZmnsZiTv6RLXMTRk2LCL75DeLMew=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pCNCafQ9HvpzmKP6I5pp5T8siGbw6BtynMpPhgdzOYIpxHXKqdeFCNMb1HLQieKMi51HZK8UclvYRZhCWmU/LI3lhQSKryYTQCaJ3TrDfKCo8pfalR52osXOpyE6ACpRf3UgidJrfyFrJnaQo2XvBSWIL2C9eMDGS44SO9ZXYVU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=VY28zyu4; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="VY28zyu4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779416521; x=1810952521; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=upmFG+tdOWBNRk1ZmnsZiTv6RLXMTRk2LCL75DeLMew=; b=VY28zyu4AshxyEChtYVEn7W1jVWrDsLNHReRb0phFkJVbtJt/LVs+AwG MG9WIFLCgbCcrutsXbAUmg4e4mL7RyKU9KxDaqccjIv//TDohpYSG7XVm 07tVfc2T1uVNEX28gyebVgVUHy9tWNxstvSwhnTxE+Jc2mYQRclfOdOew YBEhRfAiMzsDN18UmFyUZuvvq2wE6L3S/JdRaDc9vLuYVhqKv+ZFvpnqq KsoY/2zBcraMoTB9dl8xb8vOCle4BTobXEKuTcuBuU/HTpgmI0JISVwZz HuLYGUdkMHLchieRU1JqVFAiLJmlESQVx+PdFsEauOXquMROJov/rpmgE Q==; X-CSE-ConnectionGUID: 7oqq6FHPQoi2wepWD4OmpA== X-CSE-MsgGUID: 9XUI6ThKQ56g9fOUloFtMw== X-IronPort-AV: E=McAfee;i="6800,10657,11793"; a="80400516" X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="80400516" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:21:58 -0700 X-CSE-ConnectionGUID: Sp9qT12DRjecHVIpmoQtRA== X-CSE-MsgGUID: gGxKLXjHRGuONhTp2lDv/A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="236335368" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:21:58 -0700 From: "David E. Box" To: Rajneesh Bhardwaj , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Hans de Goede Cc: "David E. Box" , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Xi Pardee , Srinivas Pandruvada Subject: [PATCH v5 02/16] platform/x86/intel/pmt/crashlog: Split init into pre-decode Date: Thu, 21 May 2026 19:21:32 -0700 Message-ID: <20260522022147.4137494-3-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522022147.4137494-1-david.e.box@linux.intel.com> References: <20260522022147.4137494-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refactor crashlog initialization to use the PMT namespace pre-decode hook: - Add pmt_crashlog_pre_decode() to parse type/version, select the crashlog_info, initialize the control mutex, and set entry->attr_grp. - Simplify pmt_crashlog_header_decode() to only read header fields from the discovery table. - Wire the namespace with .pmt_pre_decode =3D pmt_crashlog_pre_decode. This separates structural initialization from header parsing, aligning crashlog with the PMT class pre/post decode flow. Signed-off-by: David E. Box Reviewed-by: Ilpo J=C3=A4rvinen --- V5 - No changes V4 - No changes V3 - No changes V2 - No changes drivers/platform/x86/intel/pmt/crashlog.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/platform/x86/intel/pmt/crashlog.c b/drivers/platform/x= 86/intel/pmt/crashlog.c index b0393c9c5b4b..f936daf99e4d 100644 --- a/drivers/platform/x86/intel/pmt/crashlog.c +++ b/drivers/platform/x86/intel/pmt/crashlog.c @@ -496,11 +496,9 @@ static const struct crashlog_info *select_crashlog_inf= o(u32 type, u32 version) return &crashlog_type1_ver2; } =20 -static int pmt_crashlog_header_decode(struct intel_pmt_entry *entry, - struct device *dev) +static int pmt_crashlog_pre_decode(struct intel_vsec_device *ivdev, + struct intel_pmt_entry *entry) { - void __iomem *disc_table =3D entry->disc_table; - struct intel_pmt_header *header =3D &entry->header; struct crashlog_entry *crashlog; u32 version; u32 type; @@ -513,6 +511,16 @@ static int pmt_crashlog_header_decode(struct intel_pmt= _entry *entry, mutex_init(&crashlog->control_mutex); =20 crashlog->info =3D select_crashlog_info(type, version); + entry->attr_grp =3D crashlog->info->attr_grp; + + return 0; +} + +static int pmt_crashlog_header_decode(struct intel_pmt_entry *entry, + struct device *dev) +{ + void __iomem *disc_table =3D entry->disc_table; + struct intel_pmt_header *header =3D &entry->header; =20 header->access_type =3D GET_ACCESS(readl(disc_table)); header->guid =3D readl(disc_table + GUID_OFFSET); @@ -521,8 +529,6 @@ static int pmt_crashlog_header_decode(struct intel_pmt_= entry *entry, /* Size is measured in DWORDS, but accessor returns bytes */ header->size =3D GET_SIZE(readl(disc_table + SIZE_OFFSET)); =20 - entry->attr_grp =3D crashlog->info->attr_grp; - return 0; } =20 @@ -530,6 +536,7 @@ static DEFINE_XARRAY_ALLOC(crashlog_array); static struct intel_pmt_namespace pmt_crashlog_ns =3D { .name =3D "crashlog", .xa =3D &crashlog_array, + .pmt_pre_decode =3D pmt_crashlog_pre_decode, .pmt_header_decode =3D pmt_crashlog_header_decode, }; =20 --=20 2.43.0 From nobody Sun May 24 20:33:05 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C238B2DB79E; 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X-CSE-ConnectionGUID: vsmSzRVbRTqIjhUOHSGv/w== X-CSE-MsgGUID: eggXpVDXQNyEbRJIZEzr+w== X-IronPort-AV: E=McAfee;i="6800,10657,11793"; a="80400519" X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="80400519" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:21:58 -0700 X-CSE-ConnectionGUID: zd1xoSMiQk2JtcL1EYM5kg== X-CSE-MsgGUID: ECDp89LPSgytfIWEtjNP1g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="236335369" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:21:58 -0700 From: "David E. Box" To: Rajneesh Bhardwaj , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Hans de Goede Cc: "David E. Box" , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Xi Pardee , Srinivas Pandruvada Subject: [PATCH v5 03/16] platform/x86/intel/pmt/telemetry: Move overlap check to post-decode hook Date: Thu, 21 May 2026 19:21:33 -0700 Message-ID: <20260522022147.4137494-4-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522022147.4137494-1-david.e.box@linux.intel.com> References: <20260522022147.4137494-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update the telemetry namespace to use the new PMT class pre/post decode interface. The overlap check, which previously occurred during header decode, is now performed in the post-decode hook once header fields are populated. This preserves existing behavior while reusing the same header decode logic across PMT drivers. Signed-off-by: David E. Box Reviewed-by: Ilpo J=C3=A4rvinen --- V5 - No changes V4 - No changes V3 - No changes V2 - No changes drivers/platform/x86/intel/pmt/class.h | 1 + drivers/platform/x86/intel/pmt/telemetry.c | 24 ++++++++++++++-------- 2 files changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/platform/x86/intel/pmt/class.h b/drivers/platform/x86/= intel/pmt/class.h index ff39014b208c..8a0db0ef58c1 100644 --- a/drivers/platform/x86/intel/pmt/class.h +++ b/drivers/platform/x86/intel/pmt/class.h @@ -37,6 +37,7 @@ struct intel_pmt_header { u32 size; u32 guid; u8 access_type; + u8 telem_type; }; =20 struct intel_pmt_entry { diff --git a/drivers/platform/x86/intel/pmt/telemetry.c b/drivers/platform/= x86/intel/pmt/telemetry.c index bdc7c24a3678..d22f633638be 100644 --- a/drivers/platform/x86/intel/pmt/telemetry.c +++ b/drivers/platform/x86/intel/pmt/telemetry.c @@ -58,14 +58,9 @@ struct pmt_telem_priv { struct intel_pmt_entry entry[]; }; =20 -static bool pmt_telem_region_overlaps(struct intel_pmt_entry *entry, - struct device *dev) +static bool pmt_telem_region_overlaps(struct device *dev, u32 guid, u32 ty= pe) { - u32 guid =3D readl(entry->disc_table + TELEM_GUID_OFFSET); - if (intel_pmt_is_early_client_hw(dev)) { - u32 type =3D TELEM_TYPE(readl(entry->disc_table)); - if ((type =3D=3D TELEM_TYPE_PUNIT_FIXED) || (guid =3D=3D TELEM_CLIENT_FIXED_BLOCK_GUID)) return true; @@ -80,15 +75,25 @@ static int pmt_telem_header_decode(struct intel_pmt_ent= ry *entry, void __iomem *disc_table =3D entry->disc_table; struct intel_pmt_header *header =3D &entry->header; =20 - if (pmt_telem_region_overlaps(entry, dev)) - return 1; - header->access_type =3D TELEM_ACCESS(readl(disc_table)); header->guid =3D readl(disc_table + TELEM_GUID_OFFSET); header->base_offset =3D readl(disc_table + TELEM_BASE_OFFSET); =20 /* Size is measured in DWORDS, but accessor returns bytes */ header->size =3D TELEM_SIZE(readl(disc_table)); + header->telem_type =3D TELEM_TYPE(readl(entry->disc_table)); + + return 0; +} + +static int pmt_telem_post_decode(struct intel_vsec_device *ivdev, + struct intel_pmt_entry *entry) +{ + struct intel_pmt_header *header =3D &entry->header; + struct device *dev =3D &ivdev->auxdev.dev; + + if (pmt_telem_region_overlaps(dev, header->guid, header->telem_type)) + return 1; =20 /* * Some devices may expose non-functioning entries that are @@ -131,6 +136,7 @@ static struct intel_pmt_namespace pmt_telem_ns =3D { .name =3D "telem", .xa =3D &telem_array, .pmt_header_decode =3D pmt_telem_header_decode, + .pmt_post_decode =3D pmt_telem_post_decode, .pmt_add_endpoint =3D pmt_telem_add_endpoint, }; =20 --=20 2.43.0 From nobody Sun May 24 20:33:05 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 791942E8DFC; Fri, 22 May 2026 02:22:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779416522; cv=none; b=oe/TIkSGF4tnRRtW5Rjzd4Dmxa+B5O74gx4arcQYXbkwpTc0FHFt5UH0CL5drcsmq+mgNacfsRutoNl2U9UOeUAFboYZWvf9iFoch6R249QgA9xuIJF04fXgtng+qaMu3dgoJy8j4UPPmB7mxUl3Jfx2IE+tPBYL+1dIws0Eb7Y= ARC-Message-Signature: i=1; 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d="scan'208";a="236335370" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:21:58 -0700 From: "David E. Box" To: Rajneesh Bhardwaj , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Hans de Goede Cc: "David E. Box" , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Xi Pardee , Srinivas Pandruvada Subject: [PATCH v5 04/16] platform/x86/intel/pmt: Pass discovery index instead of resource Date: Thu, 21 May 2026 19:21:34 -0700 Message-ID: <20260522022147.4137494-5-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522022147.4137494-1-david.e.box@linux.intel.com> References: <20260522022147.4137494-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Change PMT class code to pass a discovery index rather than a direct struct resource when creating entries. This allows the class to identify the discovery source generically without assuming PCI BAR resources. For PCI devices, the index still resolves to a resource in the intel_vsec_device. Other discovery sources, such as ACPI, can use the same index without needing a struct resource. Signed-off-by: David E. Box --- V5 - No changes V4 - No changes V3 changes: - Rebased after dropping the previous "Move header decode into common helper" patch - Adjusted the intel_pmt_populate_entry() call path to match the restored intel_pmt_dev_create() flow - Did not apply Ilpo V2 signoff due to these changes. V2 - No changes drivers/platform/x86/intel/pmt/class.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/= intel/pmt/class.c index 9b315334a69b..7da8279b54f8 100644 --- a/drivers/platform/x86/intel/pmt/class.c +++ b/drivers/platform/x86/intel/pmt/class.c @@ -206,11 +206,12 @@ EXPORT_SYMBOL_GPL(intel_pmt_class); =20 static int intel_pmt_populate_entry(struct intel_pmt_entry *entry, struct intel_vsec_device *ivdev, - struct resource *disc_res) + int idx) { struct pci_dev *pci_dev =3D to_pci_dev(ivdev->dev); struct device *dev =3D &ivdev->auxdev.dev; struct intel_pmt_header *header =3D &entry->header; + struct resource *disc_res; u8 bir; =20 /* @@ -235,6 +236,7 @@ static int intel_pmt_populate_entry(struct intel_pmt_en= try *entry, * For access_type LOCAL, the base address is as follows: * base address =3D end of discovery region + base offset */ + disc_res =3D &ivdev->resource[idx]; entry->base_addr =3D disc_res->end + 1 + header->base_offset; =20 /* @@ -397,7 +399,7 @@ int intel_pmt_dev_create(struct intel_pmt_entry *entry,= struct intel_pmt_namespa return ret; } =20 - ret =3D intel_pmt_populate_entry(entry, intel_vsec_dev, disc_res); + ret =3D intel_pmt_populate_entry(entry, intel_vsec_dev, idx); if (ret) return ret; =20 --=20 2.43.0 From nobody Sun May 24 20:33:05 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40D782F28E3; Fri, 22 May 2026 02:22:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779416527; cv=none; b=EybX23NdIH629GaZhVh8upiZQEKGTmvI1w/u3FwZk0Vss0PqMRSOJFAiX8euVKcUqLKZMJuv+JC/ZKRntnQd7Rp+UkYq67wGWNPxudKs+X2LKo+j8StDZ9kII4BoaUCJAPQkvaaINJmV15cPPgnMXbIcH/L4ESfnWIR75cxUMLU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779416527; c=relaxed/simple; bh=LI8YVMTRoNz4q2JSpYLuLeogGrOzJAXkSllN+bAB0zs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RWz3a97tOqmCOnDuf/3CIDjaHLcXJBYCStrPfv1GenJnfc6HfpGSspmSMj2EU4re/qEm8fV1XhKh9NDjacdDxVV9FREVBIfP8Qg+DAQ27LAx5Bin2qpB9RdD2egX10zO8VeDfy3c41OaR/5gUALjPlp7HwBMIeqc5+AGrvugiQ4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=GeTU1GEd; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="GeTU1GEd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779416522; x=1810952522; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LI8YVMTRoNz4q2JSpYLuLeogGrOzJAXkSllN+bAB0zs=; b=GeTU1GEdASyKTUiKIlXvgYlLLfrf4xKBnfwnAdkwWTUVRbCZ1EKzqUxb SFiS0zb/8KwLCQiP6zNWGKzJ9m4W5HkHftl6PIThUdBJrr2rrk71qYoR+ r9NPwBlnMseSMlrCEwLB215SJ68UK3/Dj6WSqi6qqHZw4yy7nI13hDUl0 8rqAKZ8VoYSWuP0XOdfUtUOfHCM5h3GbZ6IO5oNrKuDD9E6Ez2dGnejpI KtQSuKgKfzmSXrrXPsUg95DzVQAY4/FQK54U12yL56rdyeYazC13EG1Zd qsQ6yu8GyvJc2rRiYvjwsD1pfi5+3bL3iywI6sH71ktZlmJMyZaWvZi7f w==; X-CSE-ConnectionGUID: qkyemUyXRZi5szHx72D92g== X-CSE-MsgGUID: EVb2+VfnRi+tmTyTIf9vnw== X-IronPort-AV: E=McAfee;i="6800,10657,11793"; a="80400529" X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="80400529" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:21:59 -0700 X-CSE-ConnectionGUID: JjYj9bKzR36GrBEzmoN27w== X-CSE-MsgGUID: 40NKEcwtSAGQH0iMtBGC9g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="236335373" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:21:59 -0700 From: "David E. Box" To: Rajneesh Bhardwaj , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Hans de Goede Cc: "David E. Box" , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Xi Pardee , Srinivas Pandruvada Subject: [PATCH v5 05/16] platform/x86/intel/pmt: Cache the telemetry discovery header Date: Thu, 21 May 2026 19:21:35 -0700 Message-ID: <20260522022147.4137494-6-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522022147.4137494-1-david.e.box@linux.intel.com> References: <20260522022147.4137494-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" pmt_telem_header_decode() only needs the discovery header dwords, but it currently decodes them by reading directly from entry->disc_table. Cache the discovery header in intel_pmt_entry when the device is created and have telemetry decode use the cached values instead of performing MMIO reads at decode time. The DVSEC discovery resource for a namespace is sized by its per-entry entry_size (in dwords), which can be less than the 4-dword cache (e.g. telemetry uses entry_size =3D 3, i.e. 12 bytes). Cap the memcpy_fromio() to resource_size(disc_res) so the new cache does not read past the mapped region. Any unread dwords stay zero from the zero-initialized allocation of the containing struct. This keeps the telemetry header decode path independent of how the discovery data is backed and avoids baking a direct MMIO assumption into the feature-specific decode logic. Assisted-by: GitHub-Copilot:claude-opus-4.7 Signed-off-by: David E. Box --- V5 changes: - Cap memcpy_fromio() of the cached discovery header to resource_size(disc_res) so the newly introduced cache does not over-read namespaces whose DVSEC entry_size is smaller than the cache (e.g. telemetry has entry_size =3D 3, 12 bytes). V4 - No changes V3 changes: - New patch split out from PMT header-fetch rework to cache discovery header data before downstream decode/population. - Added to carry the post-v3 bug fix while preserving the original series ordering intent. drivers/platform/x86/intel/pmt/class.c | 11 +++++++++++ drivers/platform/x86/intel/pmt/class.h | 1 + drivers/platform/x86/intel/pmt/telemetry.c | 12 ++++++------ 3 files changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/= intel/pmt/class.c index 7da8279b54f8..246e11837800 100644 --- a/drivers/platform/x86/intel/pmt/class.c +++ b/drivers/platform/x86/intel/pmt/class.c @@ -383,6 +383,17 @@ int intel_pmt_dev_create(struct intel_pmt_entry *entry= , struct intel_pmt_namespa if (IS_ERR(entry->disc_table)) return PTR_ERR(entry->disc_table); =20 + /* + * The mapped discovery resource may be smaller than disc_header (its + * size is the namespace's DVSEC entry_size in dwords, which can be + * less than 4). Cap the copy to the actual resource size to avoid + * reading past the mapped region; any unread dwords stay zero from + * the zero-initialized allocation of the containing struct. + */ + memcpy_fromio(entry->disc_header, entry->disc_table, + min_t(size_t, sizeof(entry->disc_header), + resource_size(disc_res))); + if (ns->pmt_pre_decode) { ret =3D ns->pmt_pre_decode(intel_vsec_dev, entry); if (ret) diff --git a/drivers/platform/x86/intel/pmt/class.h b/drivers/platform/x86/= intel/pmt/class.h index 8a0db0ef58c1..84202fc7920c 100644 --- a/drivers/platform/x86/intel/pmt/class.h +++ b/drivers/platform/x86/intel/pmt/class.h @@ -44,6 +44,7 @@ struct intel_pmt_entry { struct telem_endpoint *ep; struct pci_dev *pcidev; struct intel_pmt_header header; + u32 disc_header[4]; struct bin_attribute pmt_bin_attr; const struct attribute_group *attr_grp; struct kobject *kobj; diff --git a/drivers/platform/x86/intel/pmt/telemetry.c b/drivers/platform/= x86/intel/pmt/telemetry.c index d22f633638be..953f35b6daec 100644 --- a/drivers/platform/x86/intel/pmt/telemetry.c +++ b/drivers/platform/x86/intel/pmt/telemetry.c @@ -72,16 +72,16 @@ static bool pmt_telem_region_overlaps(struct device *de= v, u32 guid, u32 type) static int pmt_telem_header_decode(struct intel_pmt_entry *entry, struct device *dev) { - void __iomem *disc_table =3D entry->disc_table; struct intel_pmt_header *header =3D &entry->header; + u32 *disc_header =3D entry->disc_header; =20 - header->access_type =3D TELEM_ACCESS(readl(disc_table)); - header->guid =3D readl(disc_table + TELEM_GUID_OFFSET); - header->base_offset =3D readl(disc_table + TELEM_BASE_OFFSET); + header->access_type =3D TELEM_ACCESS(disc_header[0]); + header->guid =3D disc_header[1]; + header->base_offset =3D disc_header[2]; =20 /* Size is measured in DWORDS, but accessor returns bytes */ - header->size =3D TELEM_SIZE(readl(disc_table)); - header->telem_type =3D TELEM_TYPE(readl(entry->disc_table)); + header->size =3D TELEM_SIZE(disc_header[0]); + header->telem_type =3D TELEM_TYPE(disc_header[0]); =20 return 0; } --=20 2.43.0 From nobody Sun May 24 20:33:05 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6ABD82F549C; Fri, 22 May 2026 02:22:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a="80400532" X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="80400532" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:21:59 -0700 X-CSE-ConnectionGUID: Ejk82xCwR0+gCcAFEdqqFQ== X-CSE-MsgGUID: Lg3taeelR1qCPF+TajA5xg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="236335374" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:21:59 -0700 From: "David E. Box" To: Rajneesh Bhardwaj , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Hans de Goede Cc: "David E. Box" , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Xi Pardee , Srinivas Pandruvada Subject: [PATCH v5 06/16] platform/x86/intel/pmt: Unify header fetch and add ACPI source Date: Thu, 21 May 2026 19:21:36 -0700 Message-ID: <20260522022147.4137494-7-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522022147.4137494-1-david.e.box@linux.intel.com> References: <20260522022147.4137494-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow the PMT class to read discovery headers from either PCI MMIO or ACPI-provided entries, depending on the discovery source. The new source-aware fetch helper retrieves the first two QWORDs for both paths while keeping the mapped discovery table available for users such as crashlog. Split intel_pmt_populate_entry() into source-specific resolvers: - pmt_resolve_access_pci(): handles both ACCESS_LOCAL and ACCESS_BARID for PCI-backed devices and sets entry->pcidev. Same existing functionality. - pmt_resolve_access_acpi(): handles only ACCESS_BARID for ACPI-backed devices, rejecting ACCESS_LOCAL which has no valid semantics without a physical discovery resource. Also, when copying discovery headers, bind the copy size to the canonical discovery header definition instead of relying on separate literals. This maintains existing PCI behavior and makes no functional changes for PCI devices. Assisted-by: GitHub-Copilot:claude-opus-4.7 Signed-off-by: David E. Box --- V5 changes: - Cap memcpy_fromio() in pmt_get_headers() PCI branch to resource_size() of the discovery resource, matching the cap added in the cache-introducing patch. - Documented in the ACPI branch that disc_table is intentionally NULL on that source, so consumers that dereference disc_table must only be wired to INTEL_VSEC_DISC_PCI namespaces. V4 changes: - Added discovery header width macro, INTEL_VSEC_ACPI_DISC_DWORDS, in shared intel_vsec header and in definitions. - Aliased to PMT_DISC_HEADER_DWORDS and converted PMT discovery header arrays to use it. - Replaced literal header copy sizes with entry->disc_header size in pmt_get_headers() for PCI and ACPI paths. V3 changes: - Folded the header fetch rework back into intel_pmt_dev_create() after dropping the previous common header decode helper patch - Cleaned up line wrapping/indentation V2 changes: - In pmt_resolve_access_acpi(), moved dev_err() call to single line instead of split across two lines - Restructured error handling in intel_pmt_populate_entry(), moving error returns from after switch/case into each case statement for better readability - Addressed Ilpo's feedback on error message formatting and error handling patterns drivers/platform/x86/intel/pmt/class.c | 157 +++++++++++++++++++++---- drivers/platform/x86/intel/pmt/class.h | 3 +- include/linux/intel_vsec.h | 5 +- 3 files changed, 142 insertions(+), 23 deletions(-) diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/= intel/pmt/class.c index 246e11837800..1a77709edc6a 100644 --- a/drivers/platform/x86/intel/pmt/class.c +++ b/drivers/platform/x86/intel/pmt/class.c @@ -204,9 +204,9 @@ struct class intel_pmt_class =3D { }; EXPORT_SYMBOL_GPL(intel_pmt_class); =20 -static int intel_pmt_populate_entry(struct intel_pmt_entry *entry, - struct intel_vsec_device *ivdev, - int idx) +static int pmt_resolve_access_pci(struct intel_pmt_entry *entry, + struct intel_vsec_device *ivdev, + int idx) { struct pci_dev *pci_dev =3D to_pci_dev(ivdev->dev); struct device *dev =3D &ivdev->auxdev.dev; @@ -286,6 +286,81 @@ static int intel_pmt_populate_entry(struct intel_pmt_e= ntry *entry, } =20 entry->pcidev =3D pci_dev; + + return 0; +} + +static int pmt_resolve_access_acpi(struct intel_pmt_entry *entry, + struct intel_vsec_device *ivdev) +{ + struct pci_dev *pci_dev =3D NULL; + struct device *dev =3D &ivdev->auxdev.dev; + struct intel_pmt_header *header =3D &entry->header; + u8 bir; + + if (dev_is_pci(ivdev->dev)) + pci_dev =3D to_pci_dev(ivdev->dev); + + /* + * The base offset should always be 8 byte aligned. + * + * For non-local access types the lower 3 bits of base offset + * contains the index of the base address register where the + * telemetry can be found. + */ + bir =3D GET_BIR(header->base_offset); + + switch (header->access_type) { + case ACCESS_BARID: + /* ACPI platform drivers use base_addr */ + if (ivdev->base_addr) { + entry->base_addr =3D ivdev->base_addr + + GET_ADDRESS(header->base_offset); + break; + } + + /* If base_addr is not provided, then this is an ACPI companion device */ + if (!pci_dev) { + dev_err(dev, "ACCESS_BARID requires PCI BAR resources or base_addr\n"); + return -EINVAL; + } + + entry->base_addr =3D pci_resource_start(pci_dev, bir) + + GET_ADDRESS(header->base_offset); + break; + default: + dev_err(dev, "Unsupported access type %d for ACPI based PMT\n", + header->access_type); + return -EINVAL; + } + + return 0; +} + +static int intel_pmt_populate_entry(struct intel_pmt_entry *entry, + struct intel_vsec_device *ivdev, + int idx) +{ + struct intel_pmt_header *header =3D &entry->header; + struct device *dev =3D &ivdev->auxdev.dev; + int ret; + + switch (ivdev->src) { + case INTEL_VSEC_DISC_PCI: + ret =3D pmt_resolve_access_pci(entry, ivdev, idx); + if (ret) + return ret; + break; + case INTEL_VSEC_DISC_ACPI: + ret =3D pmt_resolve_access_acpi(entry, ivdev); + if (ret) + return ret; + break; + default: + dev_err(dev, "Unknown discovery source: %d\n", ivdev->src); + return -EINVAL; + } + entry->guid =3D header->guid; entry->size =3D header->size; entry->cb =3D ivdev->priv_data; @@ -370,29 +445,71 @@ static int intel_pmt_dev_register(struct intel_pmt_en= try *entry, return ret; } =20 +static int pmt_get_headers(struct intel_vsec_device *ivdev, int idx, + struct intel_pmt_entry *entry, + u32 headers[PMT_DISC_HEADER_DWORDS]) +{ + struct device *dev =3D &ivdev->auxdev.dev; + size_t header_bytes =3D sizeof(entry->disc_header); + + switch (ivdev->src) { + case INTEL_VSEC_DISC_PCI: { + struct resource *disc_res =3D &ivdev->resource[idx]; + void __iomem *disc_table; + + disc_table =3D devm_ioremap_resource(dev, disc_res); + if (IS_ERR(disc_table)) + return PTR_ERR(disc_table); + + /* + * The mapped resource is sized by the namespace's DVSEC + * entry_size (in dwords), which can be less than + * PMT_DISC_HEADER_DWORDS (e.g. telemetry uses entry_size =3D 3, + * 12 bytes). Cap the copy to resource_size() to avoid reading + * past the mapped region; any unread dwords stay zero from + * the zero-initialized allocation of the containing struct. + */ + memcpy_fromio(headers, disc_table, + min_t(size_t, header_bytes, + resource_size(disc_res))); + memcpy(entry->disc_header, headers, header_bytes); + + /* Used by crashlog driver */ + entry->disc_table =3D disc_table; + + return 0; + } + case INTEL_VSEC_DISC_ACPI: { + memcpy(headers, &ivdev->acpi_disc[idx][0], header_bytes); + memcpy(entry->disc_header, headers, header_bytes); + /* + * No MMIO mapping exists on the ACPI source path; the cached + * headers are the only view of the discovery record. Consumers + * that dereference disc_table (e.g. crashlog) must therefore + * only be wired to namespaces backed by INTEL_VSEC_DISC_PCI. + */ + entry->disc_table =3D NULL; + + return 0; + } + default: + dev_err(dev, "Unknown discovery source type: %d\n", ivdev->src); + break; + } + + return -EINVAL; +} + int intel_pmt_dev_create(struct intel_pmt_entry *entry, struct intel_pmt_n= amespace *ns, struct intel_vsec_device *intel_vsec_dev, int idx) { struct device *dev =3D &intel_vsec_dev->auxdev.dev; - struct resource *disc_res; + u32 headers[PMT_DISC_HEADER_DWORDS]; int ret; =20 - disc_res =3D &intel_vsec_dev->resource[idx]; - - entry->disc_table =3D devm_ioremap_resource(dev, disc_res); - if (IS_ERR(entry->disc_table)) - return PTR_ERR(entry->disc_table); - - /* - * The mapped discovery resource may be smaller than disc_header (its - * size is the namespace's DVSEC entry_size in dwords, which can be - * less than 4). Cap the copy to the actual resource size to avoid - * reading past the mapped region; any unread dwords stay zero from - * the zero-initialized allocation of the containing struct. - */ - memcpy_fromio(entry->disc_header, entry->disc_table, - min_t(size_t, sizeof(entry->disc_header), - resource_size(disc_res))); + ret =3D pmt_get_headers(intel_vsec_dev, idx, entry, headers); + if (ret) + return ret; =20 if (ns->pmt_pre_decode) { ret =3D ns->pmt_pre_decode(intel_vsec_dev, entry); diff --git a/drivers/platform/x86/intel/pmt/class.h b/drivers/platform/x86/= intel/pmt/class.h index 84202fc7920c..950fa4ee300d 100644 --- a/drivers/platform/x86/intel/pmt/class.h +++ b/drivers/platform/x86/intel/pmt/class.h @@ -18,6 +18,7 @@ /* PMT discovery base address/offset register layout */ #define GET_BIR(v) ((v) & GENMASK(2, 0)) #define GET_ADDRESS(v) ((v) & GENMASK(31, 3)) +#define PMT_DISC_HEADER_DWORDS INTEL_VSEC_ACPI_DISC_DWORDS =20 struct device; struct pci_dev; @@ -44,7 +45,7 @@ struct intel_pmt_entry { struct telem_endpoint *ep; struct pci_dev *pcidev; struct intel_pmt_header header; - u32 disc_header[4]; + u32 disc_header[PMT_DISC_HEADER_DWORDS]; struct bin_attribute pmt_bin_attr; const struct attribute_group *attr_grp; struct kobject *kobj; diff --git a/include/linux/intel_vsec.h b/include/linux/intel_vsec.h index 1fe5665a9d02..4c58a7f5031e 100644 --- a/include/linux/intel_vsec.h +++ b/include/linux/intel_vsec.h @@ -28,6 +28,7 @@ #define INTEL_DVSEC_TABLE_BAR(x) ((x) & GENMASK(2, 0)) #define INTEL_DVSEC_TABLE_OFFSET(x) ((x) & GENMASK(31, 3)) #define TABLE_OFFSET_SHIFT 3 +#define INTEL_VSEC_ACPI_DISC_DWORDS 4 =20 struct device; struct pci_dev; @@ -122,7 +123,7 @@ struct intel_vsec_platform_info { struct device *parent; struct intel_vsec_header **headers; const struct vsec_feature_dependency *deps; - u32 (*acpi_disc)[4]; + u32 (*acpi_disc)[INTEL_VSEC_ACPI_DISC_DWORDS]; enum intel_vsec_disc_source src; void *priv_data; unsigned long caps; @@ -154,7 +155,7 @@ struct intel_vsec_device { struct auxiliary_device auxdev; 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21 May 2026 19:21:59 -0700 From: "David E. Box" To: Rajneesh Bhardwaj , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Hans de Goede Cc: "David E. Box" , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Xi Pardee , Srinivas Pandruvada Subject: [PATCH v5 07/16] platform/x86/intel/pmc: Add PMC SSRAM Kconfig description Date: Thu, 21 May 2026 19:21:37 -0700 Message-ID: <20260522022147.4137494-8-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522022147.4137494-1-david.e.box@linux.intel.com> References: <20260522022147.4137494-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a proper description for the intel_pmc_ssram driver. Signed-off-by: David E. Box Reviewed-by: Ilpo J=C3=A4rvinen --- V5 - No changes V4 - No changes V3 - No changes V2 - No changes drivers/platform/x86/intel/pmc/Kconfig | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/Kconfig b/drivers/platform/x86/= intel/pmc/Kconfig index c6ef0bcf76af..0f19dc7edcf9 100644 --- a/drivers/platform/x86/intel/pmc/Kconfig +++ b/drivers/platform/x86/intel/pmc/Kconfig @@ -28,3 +28,14 @@ config INTEL_PMC_CORE =20 config INTEL_PMC_SSRAM_TELEMETRY tristate + help + This PCI driver discovers PMC SSRAM telemetry regions through the + PMC's MMIO interface and registers them with the Intel VSEC framework + as Intel PMT telemetry devices. + + It probes the PMC SSRAM device, extracts DVSEC information from MMIO, + reads device IDs and base addresses for multiple PMCs (main, IOE, PCH), + and exposes the discovered telemetry through Intel PMT interfaces + (including sysfs). + + This option is selected by INTEL_PMC_CORE. --=20 2.43.0 From nobody Sun May 24 20:33:05 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABA07302750; Fri, 22 May 2026 02:22:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779416532; cv=none; b=bDfec0wj401jTA/zDHf6oBFY1d+XfagYZ7tgd4USmRGZwpSI+6RHPkyaDDVdEWcnYebFQ5ohg/d/linnwfxfZwPJ2t917f3yxKyYXWktZ1nNUA2XYPzJcCPvTW6q81yEoEx31vSzVybChbavX2iBGCRhzbM+nmxpL2JwiASmPFs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779416532; c=relaxed/simple; bh=pxP0710UqCEAgnduapsN4AC6HkjKOjUq3GR5fHYaioI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=orUyiwAtbHVju8J/6lJ5zPBU+g7IDd9KIdVZAAcTjwlxPrA8QpWtwVjNPjlC7VT7PXt6ytj6wLin+PrY7Xv4Xs7UTKFsXtQXdDBLAZbS6CwkNQlGr+Gn65jhpLf619mLDbJER3k+H3NDHZsZXwoKYqaDKO1+FBcpGMo9jZnVLQU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=PWFS2lMB; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="PWFS2lMB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779416527; x=1810952527; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pxP0710UqCEAgnduapsN4AC6HkjKOjUq3GR5fHYaioI=; b=PWFS2lMBhlR5SokUFnLkudxN/u/59wfxkF2ZkmYdpC4P+ZavRG+o51O+ 1hXOg1n4K9QUoYE6GBs4+aJzmoZfwl+5q6rBJcp+VimPFY0Ssfsg9DXzq HYn8BoEhzct9le0WMCUWtECw7jo8O1QUycmSeE7BzZUPeqD6cL6Sni+DT OOoxaWyYh1K7r+acbJshkRG5FC85JPIVtlxhAJrXkxYX79Q8s65RwWMT2 1HIY9pgtM9HJTEV7Won/uJlsA7FgLs1RU7rV4LSNS9/WnInmstp9QzvwM oyI93InjM+R3xB2FKw7craZ3gYJ1/r81clmPJ0iuOFSe1yS8LDNdkYwIM g==; X-CSE-ConnectionGUID: Q8JKaLxkSbmf4Nqf6/LADA== X-CSE-MsgGUID: 1jkqAoibSPO90ZOZzRDoyQ== X-IronPort-AV: E=McAfee;i="6800,10657,11793"; a="80400538" X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="80400538" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:21:59 -0700 X-CSE-ConnectionGUID: tJn8vqrvRYCg/oG+LNglvQ== X-CSE-MsgGUID: X1r9oKDPS1SrtRpWnhh2Bg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="236335378" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:21:59 -0700 From: "David E. Box" To: Rajneesh Bhardwaj , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Hans de Goede Cc: "David E. Box" , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Xi Pardee , Srinivas Pandruvada Subject: [PATCH v5 08/16] platform/x86/intel/pmc: Add ACPI PWRM telemetry driver for Nova Lake S Date: Thu, 21 May 2026 19:21:38 -0700 Message-ID: <20260522022147.4137494-9-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522022147.4137494-1-david.e.box@linux.intel.com> References: <20260522022147.4137494-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add an ACPI-based PMC PWRM telemetry driver for Nova Lake S. The driver locates PMT discovery data in _DSD under the Intel VSEC UUID, parses it, and registers telemetry regions with the PMT/VSEC framework so PMC telemetry is exposed via existing PMT interfaces. Export pmc_parse_telem_dsd() and pmc_find_telem_guid() to support ACPI discovery in other PMC drivers (e.g., ssram_telemetry) without duplicating ACPI parsing logic. Also export acpi_disc_t typedef from core.h for callers to properly declare discovery table arrays. Selected by INTEL_PMC_CORE. Existing PCI functionality is preserved. Assisted-by: GitHub-Copilot:claude-opus-4.7 Signed-off-by: David E. Box --- V5 changes: - Added #include for U16_MAX (Ilpo). - Split acpi_handle declaration from ACPI_HANDLE() assignment and placed the assignment immediately before the !handle check (Ilpo). - Reordered local variables in pmc_pwrm_acpi_probe() in reverse-xmas-tree order (Ilpo). V4 changes: - These changes were supposed to be in V3 - Updated pmc_parse_telem_dsd() in pwrm_telemetry.c to use acpi_disc_t in the function return type for consistency with the exported typedef - In pmc_parse_telem_dsd(), change acpi_disc declaration to happen at the allocation site as specified by cleanup.h - Style, readability and cleanup-path refinement based on review feedback V2 changes: - Added explicit include for guid_t type availability in core.h - Added explicit include in pwrm_telemetry.c for GENMASK() - Added and converted goto based cleanup to __free() attributes per Ilpo's feedback - Combined u64 hdr0 and u64 hdr1 into single declaration - Converted pmc_parse_telem_dsd() to return acpi_disc directly with ERR_PTR() for failures - Added braces around _DSD evaluation failure path drivers/platform/x86/intel/pmc/Kconfig | 14 ++ drivers/platform/x86/intel/pmc/Makefile | 2 + drivers/platform/x86/intel/pmc/core.h | 16 ++ .../platform/x86/intel/pmc/pwrm_telemetry.c | 216 ++++++++++++++++++ 4 files changed, 248 insertions(+) create mode 100644 drivers/platform/x86/intel/pmc/pwrm_telemetry.c diff --git a/drivers/platform/x86/intel/pmc/Kconfig b/drivers/platform/x86/= intel/pmc/Kconfig index 0f19dc7edcf9..937186b0b5dd 100644 --- a/drivers/platform/x86/intel/pmc/Kconfig +++ b/drivers/platform/x86/intel/pmc/Kconfig @@ -9,6 +9,7 @@ config INTEL_PMC_CORE depends on ACPI depends on INTEL_PMT_TELEMETRY select INTEL_PMC_SSRAM_TELEMETRY + select INTEL_PMC_PWRM_TELEMETRY help The Intel Platform Controller Hub for Intel Core SoCs provides access to Power Management Controller registers via various interfaces. This @@ -39,3 +40,16 @@ config INTEL_PMC_SSRAM_TELEMETRY (including sysfs). =20 This option is selected by INTEL_PMC_CORE. + +config INTEL_PMC_PWRM_TELEMETRY + tristate + help + This driver discovers PMC PWRM telemetry regions described in ACPI + _DSD and registers them with the Intel VSEC framework as Intel PMT + telemetry devices. + + It validates the ACPI discovery data and publishes the discovered + regions so they can be accessed through the Intel PMT telemetry + interfaces (including sysfs). + + This option is selected by INTEL_PMC_CORE. diff --git a/drivers/platform/x86/intel/pmc/Makefile b/drivers/platform/x86= /intel/pmc/Makefile index bb960c8721d7..fdbb768f7b09 100644 --- a/drivers/platform/x86/intel/pmc/Makefile +++ b/drivers/platform/x86/intel/pmc/Makefile @@ -12,3 +12,5 @@ obj-$(CONFIG_INTEL_PMC_CORE) +=3D intel_pmc_core_pltdrv.o # Intel PMC SSRAM driver intel_pmc_ssram_telemetry-y +=3D ssram_telemetry.o obj-$(CONFIG_INTEL_PMC_SSRAM_TELEMETRY) +=3D intel_pmc_ssram_telemetry.o +intel_pmc_pwrm_telemetry-y +=3D pwrm_telemetry.o +obj-$(CONFIG_INTEL_PMC_PWRM_TELEMETRY) +=3D intel_pmc_pwrm_telemetry.o diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/i= ntel/pmc/core.h index 118c8740ad3a..f458eb908c07 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -14,10 +14,15 @@ =20 #include #include +#include +#include #include +#include =20 struct telem_endpoint; =20 +DEFINE_FREE(pmc_acpi_free, void *, if (_T) ACPI_FREE(_T)) + #define SLP_S0_RES_COUNTER_MASK GENMASK(31, 0) =20 #define PMC_BASE_ADDR_DEFAULT 0xFE000000 @@ -562,6 +567,8 @@ int pmc_core_pmt_get_blk_sub_req(struct pmc_dev *pmcdev= , struct pmc *pmc, extern const struct file_operations pmc_core_substate_req_regs_fops; extern const struct file_operations pmc_core_substate_blk_req_fops; =20 +extern const guid_t intel_vsec_guid; + #define pmc_for_each_mode(mode, pmc) \ for (unsigned int __i =3D 0, __cond; \ __cond =3D __i < (pmc)->num_lpm_modes, \ @@ -583,4 +590,13 @@ static const struct file_operations __name ## _fops = =3D { \ .release =3D single_release, \ } =20 +struct intel_vsec_header; +union acpi_object; + +/* Avoid checkpatch warning */ +typedef u32 (*acpi_disc_t)[INTEL_VSEC_ACPI_DISC_DWORDS]; + +acpi_disc_t pmc_parse_telem_dsd(union acpi_object *obj, + struct intel_vsec_header *header); +union acpi_object *pmc_find_telem_guid(union acpi_object *dsd); #endif /* PMC_CORE_H */ diff --git a/drivers/platform/x86/intel/pmc/pwrm_telemetry.c b/drivers/plat= form/x86/intel/pmc/pwrm_telemetry.c new file mode 100644 index 000000000000..70fdc79b48a2 --- /dev/null +++ b/drivers/platform/x86/intel/pmc/pwrm_telemetry.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel PMC PWRM ACPI driver + * + * Copyright (C) 2025, Intel Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "core.h" + +#define ENTRY_LEN 5 + +/* DWORD2 */ +#define DVSEC_ID_MASK GENMASK(15, 0) +#define NUM_ENTRIES_MASK GENMASK(23, 16) +#define ENTRY_SIZE_MASK GENMASK(31, 24) + +/* DWORD3 */ +#define TBIR_MASK GENMASK(2, 0) +#define DISC_TBL_OFF_MASK GENMASK(31, 3) + +const guid_t intel_vsec_guid =3D + GUID_INIT(0x294903fb, 0x634d, 0x4fc7, 0xaf, 0x1f, 0x0f, 0xb9, + 0x56, 0xb0, 0x4f, 0xc1); + +static bool is_valid_entry(union acpi_object *pkg) +{ + int i; + + if (!pkg || pkg->type !=3D ACPI_TYPE_PACKAGE || pkg->package.count !=3D E= NTRY_LEN) + return false; + + if (pkg->package.elements[0].type !=3D ACPI_TYPE_STRING) + return false; + + for (i =3D 1; i < ENTRY_LEN; i++) + if (pkg->package.elements[i].type !=3D ACPI_TYPE_INTEGER) + return false; + + return true; +} + +acpi_disc_t pmc_parse_telem_dsd(union acpi_object *obj, + struct intel_vsec_header *header) +{ + union acpi_object *vsec_pkg; + union acpi_object *disc_pkg; + u64 hdr0, hdr1; + int num_regions; + int i; + + if (!header) + return ERR_PTR(-EINVAL); + + if (!obj || obj->type !=3D ACPI_TYPE_PACKAGE || obj->package.count !=3D 2) + return ERR_PTR(-EINVAL); + + /* First Package is DVSEC info */ + vsec_pkg =3D &obj->package.elements[0]; + if (!is_valid_entry(vsec_pkg)) + return ERR_PTR(-EINVAL); + + hdr0 =3D vsec_pkg->package.elements[3].integer.value; + hdr1 =3D vsec_pkg->package.elements[4].integer.value; + + header->id =3D FIELD_GET(DVSEC_ID_MASK, hdr0); + header->num_entries =3D FIELD_GET(NUM_ENTRIES_MASK, hdr0); + header->entry_size =3D FIELD_GET(ENTRY_SIZE_MASK, hdr0); + header->tbir =3D FIELD_GET(TBIR_MASK, hdr1); + header->offset =3D FIELD_GET(DISC_TBL_OFF_MASK, hdr1); + + /* Second Package contains the discovery tables */ + disc_pkg =3D &obj->package.elements[1]; + if (disc_pkg->type !=3D ACPI_TYPE_PACKAGE || disc_pkg->package.count < 1) + return ERR_PTR(-EINVAL); + + num_regions =3D disc_pkg->package.count; + if (header->num_entries !=3D num_regions) + return ERR_PTR(-EINVAL); + + acpi_disc_t disc __free(kfree) =3D kmalloc_array(num_regions, sizeof(*dis= c), + GFP_KERNEL); + if (!disc) + return ERR_PTR(-ENOMEM); + + for (i =3D 0; i < num_regions; i++) { + union acpi_object *pkg; + u64 value; + int j; + + pkg =3D &disc_pkg->package.elements[i]; + if (!is_valid_entry(pkg)) + return ERR_PTR(-EINVAL); + + /* Element 0 is a descriptive string; DWORD values start at index 1. */ + for (j =3D 1; j < ENTRY_LEN; j++) { + value =3D pkg->package.elements[j].integer.value; + if (value > U32_MAX) + return ERR_PTR(-ERANGE); + + disc[i][j - 1] =3D value; + } + } + + return no_free_ptr(disc); +} +EXPORT_SYMBOL_NS_GPL(pmc_parse_telem_dsd, "INTEL_PMC_CORE"); + +union acpi_object *pmc_find_telem_guid(union acpi_object *dsd) +{ + int i; + + if (!dsd || dsd->type !=3D ACPI_TYPE_PACKAGE) + return NULL; + + for (i =3D 0; i + 1 < dsd->package.count; i +=3D 2) { + union acpi_object *uuid_obj, *data_obj; + guid_t uuid; + + uuid_obj =3D &dsd->package.elements[i]; + data_obj =3D &dsd->package.elements[i + 1]; + + if (uuid_obj->type !=3D ACPI_TYPE_BUFFER || + uuid_obj->buffer.length !=3D 16) + continue; + + memcpy(&uuid, uuid_obj->buffer.pointer, 16); + if (guid_equal(&uuid, &intel_vsec_guid)) + return data_obj; + } + + return NULL; +} +EXPORT_SYMBOL_NS_GPL(pmc_find_telem_guid, "INTEL_PMC_CORE"); + +static int pmc_pwrm_acpi_probe(struct platform_device *pdev) +{ + struct intel_vsec_header header; + struct intel_vsec_header *headers[2] =3D { &header, NULL }; + struct acpi_buffer buf =3D { ACPI_ALLOCATE_BUFFER, NULL }; + struct intel_vsec_platform_info info =3D { }; + struct device *dev =3D &pdev->dev; + union acpi_object *dsd; + struct resource *res; + acpi_handle handle; + acpi_status status; + + handle =3D ACPI_HANDLE(&pdev->dev); + if (!handle) + return -ENODEV; + + status =3D acpi_evaluate_object(handle, "_DSD", NULL, &buf); + if (ACPI_FAILURE(status)) { + return dev_err_probe(dev, -ENODEV, "Could not evaluate _DSD: %s\n", + acpi_format_exception(status)); + } + + void *dsd_buf __free(pmc_acpi_free) =3D buf.pointer; + + dsd =3D pmc_find_telem_guid(dsd_buf); + if (!dsd) + return -ENODEV; + + acpi_disc_t acpi_disc __free(kfree) =3D pmc_parse_telem_dsd(dsd, &header); + if (IS_ERR(acpi_disc)) + return PTR_ERR(acpi_disc); + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, header.tbir); + if (!res) + return -EINVAL; + + info.headers =3D headers; + info.caps =3D VSEC_CAP_TELEMETRY; + info.acpi_disc =3D acpi_disc; + info.src =3D INTEL_VSEC_DISC_ACPI; + info.base_addr =3D res->start; + + return intel_vsec_register(&pdev->dev, &info); +} + +static const struct acpi_device_id pmc_pwrm_acpi_ids[] =3D { + { "INTC1122", 0 }, /* Nova Lake */ + { "INTC1129", 0 }, /* Nova Lake */ + { } +}; +MODULE_DEVICE_TABLE(acpi, pmc_pwrm_acpi_ids); + +static struct platform_driver pmc_pwrm_acpi_driver =3D { + .probe =3D pmc_pwrm_acpi_probe, + .driver =3D { + .name =3D "intel_pmc_pwrm_acpi", + .acpi_match_table =3D ACPI_PTR(pmc_pwrm_acpi_ids), + }, +}; +module_platform_driver(pmc_pwrm_acpi_driver); + +MODULE_AUTHOR("David E. Box "); +MODULE_DESCRIPTION("Intel PMC PWRM ACPI driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("INTEL_VSEC"); --=20 2.43.0 From nobody Sun May 24 20:33:05 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB7F43019AA; Fri, 22 May 2026 02:22:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779416533; cv=none; b=GIh012T52PenJGJimlCh2JwcbD9NKofEa/6dNAX/A2f15E78N8yVVhEQa+/KCzITOJRoT35ppaF5phHTpMHqD8Fp+1GYNg/OwAPHdLqZ/4vFttWKHL44sK4NX6NUu2ZMbDQLLsRCmu0Qz5bIlStHaYWYymEdDGb37csTcTk3iYQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779416533; c=relaxed/simple; bh=jozqLoZtjaWXE90lOxGErxuxrwJaGqr+Wwqf1b3r9t4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VIInfS8/yFm9dEfBxNDyFVBkmn/CwHc0/SxglDqhP4nky3jsO+eu6stXPPQUlXNPkIgN3CdTrGUl2JlQ25uuI1r1fLkB4jgHhfkUhpzmQ0LP1ruZhVcET5f3ybJjwavEbDr0c5tcAdfsFmZz2UdkAXPCn1hDPbsbExvc/QMJ0IM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EYfJP6Hn; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EYfJP6Hn" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779416527; x=1810952527; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jozqLoZtjaWXE90lOxGErxuxrwJaGqr+Wwqf1b3r9t4=; b=EYfJP6HnkWt9ywAABQ3+XwPE803IgcsAzQJkP1GmSuWogOydXKSqKsD7 UiQtTSAci9duiMOUdfQrkbkbUhNVsbc+NXJbFqx8bX5bENWhkRzB7mEi2 TKWCrJfqLhI1h+Hd+At1BFkadlzp1eBNXgLkBPToy0NTjS3fZ8TCj2omO xMCcC1BoMEwqsPtcUAWSXcRq8AGaU9M6nHz+3rRQKjJRe3OUJCKVAVcR9 snaUnuLMXm1HKYN/t60XOuaUfkXQlw+mjUPfFb9793q7wnFhpee23TgSY 5hPkhu/kIpAyyoRc61pHevi2hsrpoqg0BDPKxjwWbHWkmOr0av+yUo1/N A==; X-CSE-ConnectionGUID: yO0NAvEWS8+gwCQrTG41DA== X-CSE-MsgGUID: 0lezMgkcQJ6DomS9HddOLQ== X-IronPort-AV: E=McAfee;i="6800,10657,11793"; a="80400544" X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="80400544" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:22:00 -0700 X-CSE-ConnectionGUID: lQyKBil+S/SDpbcAQQ8SCA== X-CSE-MsgGUID: oRe4gV/DRfmYdBQieRYz9w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="236335379" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:21:59 -0700 From: "David E. Box" To: Rajneesh Bhardwaj , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Hans de Goede Cc: "David E. Box" , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Xi Pardee , Srinivas Pandruvada Subject: [PATCH v5 09/16] platform/x86/intel/pmc/ssram: Rename probe and PCI ID table for consistency Date: Thu, 21 May 2026 19:21:39 -0700 Message-ID: <20260522022147.4137494-10-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522022147.4137494-1-david.e.box@linux.intel.com> References: <20260522022147.4137494-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename intel_pmc_ssram_telemetry_probe() to pmc_ssram_telemetry_probe() and intel_pmc_ssram_telemetry_pci_ids[] to pmc_ssram_telemetry_pci_ids[], updating the MODULE_DEVICE_TABLE() and pci_driver wiring accordingly. This aligns the symbol names with the driver filename and module name, reduces redundant intel_ prefixes, and improves readability. No functional behavior changes are intended. Reviewed-by: Ilpo J=C3=A4rvinen Signed-off-by: David E. Box --- V5 - No changes V4 - No changes V3 - No changes V2 - No changes drivers/platform/x86/intel/pmc/ssram_telemetry.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.c b/drivers/pla= tform/x86/intel/pmc/ssram_telemetry.c index 6f6e83e70fc5..1deb4d71da3f 100644 --- a/drivers/platform/x86/intel/pmc/ssram_telemetry.c +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.c @@ -149,7 +149,7 @@ int pmc_ssram_telemetry_get_pmc_info(unsigned int pmc_i= dx, } EXPORT_SYMBOL_GPL(pmc_ssram_telemetry_get_pmc_info); =20 -static int intel_pmc_ssram_telemetry_probe(struct pci_dev *pcidev, const s= truct pci_device_id *id) +static int pmc_ssram_telemetry_probe(struct pci_dev *pcidev, const struct = pci_device_id *id) { int ret; =20 @@ -183,7 +183,7 @@ static int intel_pmc_ssram_telemetry_probe(struct pci_d= ev *pcidev, const struct return ret; } =20 -static const struct pci_device_id intel_pmc_ssram_telemetry_pci_ids[] =3D { +static const struct pci_device_id pmc_ssram_telemetry_pci_ids[] =3D { { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_MTL_SOCM) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCS) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCM) }, @@ -193,14 +193,14 @@ static const struct pci_device_id intel_pmc_ssram_tel= emetry_pci_ids[] =3D { { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_WCL_PCDN) }, { } }; -MODULE_DEVICE_TABLE(pci, intel_pmc_ssram_telemetry_pci_ids); +MODULE_DEVICE_TABLE(pci, pmc_ssram_telemetry_pci_ids); =20 -static struct pci_driver intel_pmc_ssram_telemetry_driver =3D { +static struct pci_driver pmc_ssram_telemetry_driver =3D { .name =3D "intel_pmc_ssram_telemetry", - .id_table =3D intel_pmc_ssram_telemetry_pci_ids, - .probe =3D intel_pmc_ssram_telemetry_probe, + .id_table =3D pmc_ssram_telemetry_pci_ids, + .probe =3D pmc_ssram_telemetry_probe, }; -module_pci_driver(intel_pmc_ssram_telemetry_driver); +module_pci_driver(pmc_ssram_telemetry_driver); =20 MODULE_IMPORT_NS("INTEL_VSEC"); MODULE_AUTHOR("Xi Pardee "); --=20 2.43.0 From nobody Sun May 24 20:33:05 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB9693019D9; Fri, 22 May 2026 02:22:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a="80400547" X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="80400547" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:22:00 -0700 X-CSE-ConnectionGUID: qKhWAkhLTkSAQHOvtbVb4A== X-CSE-MsgGUID: IRCgm1LxQP+AER2kgX3Ipw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="236335381" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:22:00 -0700 From: "David E. Box" To: Rajneesh Bhardwaj , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Hans de Goede Cc: Xi Pardee , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, "David E . Box" , Srinivas Pandruvada Subject: [PATCH v5 10/16] platform/x86/intel/pmc/ssram: Use fixed-size static pmc array Date: Thu, 21 May 2026 19:21:40 -0700 Message-ID: <20260522022147.4137494-11-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522022147.4137494-1-david.e.box@linux.intel.com> References: <20260522022147.4137494-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xi Pardee Switch pmc_ssram_telems from a devm-allocated pointer to a fixed-size static array, eliminating per-probe allocation overhead and simplifying lifetime management. Correspondingly simplify pmc_ssram_telemetry_get_pmc_info() validation to check devid availability and tighten input bounds checking. Drop null-pointer checks now that the storage is static. Signed-off-by: Xi Pardee Signed-off-by: David E. Box Reviewed-by: Ilpo J=C3=A4rvinen --- V5 - No changes V4 - No changes V3 - No changes V2 changes: - Replaced hardcoded array size [3] with MAX_NUM_PMC constant drivers/platform/x86/intel/pmc/ssram_telemetry.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.c b/drivers/pla= tform/x86/intel/pmc/ssram_telemetry.c index 1deb4d71da3f..4bfe60ee55ca 100644 --- a/drivers/platform/x86/intel/pmc/ssram_telemetry.c +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.c @@ -24,7 +24,7 @@ =20 DEFINE_FREE(pmc_ssram_telemetry_iounmap, void __iomem *, if (_T) iounmap(_= T)) =20 -static struct pmc_ssram_telemetry *pmc_ssram_telems; +static struct pmc_ssram_telemetry pmc_ssram_telems[MAX_NUM_PMC]; static bool device_probed; =20 static int @@ -140,7 +140,7 @@ int pmc_ssram_telemetry_get_pmc_info(unsigned int pmc_i= dx, if (pmc_idx >=3D MAX_NUM_PMC) return -EINVAL; =20 - if (!pmc_ssram_telems || !pmc_ssram_telems[pmc_idx].devid) + if (!pmc_ssram_telems[pmc_idx].devid) return -ENODEV; =20 pmc_ssram_telemetry->devid =3D pmc_ssram_telems[pmc_idx].devid; @@ -153,12 +153,6 @@ static int pmc_ssram_telemetry_probe(struct pci_dev *p= cidev, const struct pci_de { int ret; =20 - pmc_ssram_telems =3D devm_kzalloc(&pcidev->dev, sizeof(*pmc_ssram_telems)= * MAX_NUM_PMC, - GFP_KERNEL); - if (!pmc_ssram_telems) { - ret =3D -ENOMEM; - goto probe_finish; - } =20 ret =3D pcim_enable_device(pcidev); if (ret) { --=20 2.43.0 From nobody Sun May 24 20:33:05 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11F562EC081; Fri, 22 May 2026 02:22:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779416536; cv=none; b=skNzjBhoYt77hIwF7ut/OEl5dH2cZF9LENTA91alOAXO8AL7KdF+fy054px6RgQx7GaGC93dt6Ip8k0Ho0o9+N03rm03pykn216fccrQE47D2vm19jnobcQMb8uwkaKIv+t918+X4ylFSRoUXnaylb/aCAJu/fK1Fm+8ezQHmts= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779416536; c=relaxed/simple; bh=V30rpEqrHapXUVMTqhSdw/4Mp5eMrHyDNKl/2BvIMFM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=X2WapvYw9N9t4bE8iGps2bMBGvLA0uYZTSK6wQgSFG+2swHoqqAyOPIpvwLqiqqXMSrkqhnUJgvYxUUhEaRDAwkwoguoAKF7+8EPPwMzmHPUegb5k+fK0S0hpUq5F9p9AwmenOKmux+gzlPsCTc5QDrJyLcIYXSiapI/PiIMO0w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=HcoXBaR+; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="HcoXBaR+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779416532; x=1810952532; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=V30rpEqrHapXUVMTqhSdw/4Mp5eMrHyDNKl/2BvIMFM=; b=HcoXBaR+gA4Yzuy9Safv09/vVbVTXSR1ToCKdjc0UA1mphczpwJfFQNu OycQRf+rs4v46twCEyiBZ7pgINhh/7Mrz3DbYKCakFSJb0CT5h1inQ0t8 xd60E4iwEqIsMYxnv3N9l4sLsSOrEHqka5c9VEiZPBG/OYRMS7nHZht2P ve4NmdnrdaEFK86A3cAFoG2s18IopdCUj6/nhpWesq/nFUjAzWpRwNwRZ KXzpJyVUPfGbWPuOQLBmn6EvfG+d3nFp6hLsHMrBpfduwAYIxFzh63K+u C4UYtpcR9yp+97VCElyHki97Runtk4Qp26ij4+aq/FKwsuEEAU4lYI9g8 Q==; X-CSE-ConnectionGUID: S+/iI6hcThGsuVsCHZsHsw== X-CSE-MsgGUID: muUi66IBTUK2oaImYtXbSQ== X-IronPort-AV: E=McAfee;i="6800,10657,11793"; a="80400551" X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="80400551" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:22:00 -0700 X-CSE-ConnectionGUID: nYRH0blfSaaJnph3ARriHg== X-CSE-MsgGUID: EUUWsgXySU+rzoK6HRhlyA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="236335385" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:22:00 -0700 From: "David E. Box" To: Rajneesh Bhardwaj , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Hans de Goede Cc: "David E. Box" , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Xi Pardee , Srinivas Pandruvada Subject: [PATCH v5 11/16] platform/x86/intel/pmc/ssram: Refactor DEVID/PWRMBASE extraction into helper Date: Thu, 21 May 2026 19:21:41 -0700 Message-ID: <20260522022147.4137494-12-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522022147.4137494-1-david.e.box@linux.intel.com> References: <20260522022147.4137494-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move DEVID/PWRMBASE extraction into pmc_ssram_get_devid_pwrmbase(). This is a preparatory refactor to place functionality in a common helper for reuse by a subsequent patch. Additionally add missing bits.h include and define SSRAM_BASE_ADDR_MASK for the address extraction mask. Signed-off-by: David E. Box Reviewed-by: Ilpo J=C3=A4rvinen --- V5 - No changes V4 - No changes V3 - No changes V2 changes: - Added missing include for GENMASK_ULL() used in get_base= () - Defined SSRAM_BASE_ADDR_MASK macro to replace magic mask constant GENMASK_ULL(63, 3) .../platform/x86/intel/pmc/ssram_telemetry.c | 33 ++++++++++++------- 1 file changed, 21 insertions(+), 12 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.c b/drivers/pla= tform/x86/intel/pmc/ssram_telemetry.c index 4bfe60ee55ca..779e84c724ac 100644 --- a/drivers/platform/x86/intel/pmc/ssram_telemetry.c +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.c @@ -5,6 +5,7 @@ * Copyright (c) 2023, Intel Corporation. */ =20 +#include #include #include #include @@ -21,12 +22,30 @@ #define SSRAM_PCH_OFFSET 0x60 #define SSRAM_IOE_OFFSET 0x68 #define SSRAM_DEVID_OFFSET 0x70 +#define SSRAM_BASE_ADDR_MASK GENMASK_ULL(63, 3) =20 DEFINE_FREE(pmc_ssram_telemetry_iounmap, void __iomem *, if (_T) iounmap(_= T)) =20 static struct pmc_ssram_telemetry pmc_ssram_telems[MAX_NUM_PMC]; static bool device_probed; =20 +static inline u64 get_base(void __iomem *addr, u32 offset) +{ + return lo_hi_readq(addr + offset) & SSRAM_BASE_ADDR_MASK; +} + +static void pmc_ssram_get_devid_pwrmbase(void __iomem *ssram, unsigned int= pmc_idx) +{ + u64 pwrm_base; + u16 devid; + + pwrm_base =3D get_base(ssram, SSRAM_PWRM_OFFSET); + devid =3D readw(ssram + SSRAM_DEVID_OFFSET); + + pmc_ssram_telems[pmc_idx].devid =3D devid; + pmc_ssram_telems[pmc_idx].base_addr =3D pwrm_base; +} + static int pmc_ssram_telemetry_add_pmt(struct pci_dev *pcidev, u64 ssram_base, void _= _iomem *ssram) { @@ -63,18 +82,12 @@ pmc_ssram_telemetry_add_pmt(struct pci_dev *pcidev, u64= ssram_base, void __iomem return intel_vsec_register(&pcidev->dev, &info); } =20 -static inline u64 get_base(void __iomem *addr, u32 offset) -{ - return lo_hi_readq(addr + offset) & GENMASK_ULL(63, 3); -} - static int pmc_ssram_telemetry_get_pmc(struct pci_dev *pcidev, unsigned int pmc_idx, = u32 offset) { void __iomem __free(pmc_ssram_telemetry_iounmap) *tmp_ssram =3D NULL; void __iomem __free(pmc_ssram_telemetry_iounmap) *ssram =3D NULL; - u64 ssram_base, pwrm_base; - u16 devid; + u64 ssram_base; =20 ssram_base =3D pci_resource_start(pcidev, 0); tmp_ssram =3D ioremap(ssram_base, SSRAM_HDR_SIZE); @@ -99,11 +112,7 @@ pmc_ssram_telemetry_get_pmc(struct pci_dev *pcidev, uns= igned int pmc_idx, u32 of ssram =3D no_free_ptr(tmp_ssram); } =20 - pwrm_base =3D get_base(ssram, SSRAM_PWRM_OFFSET); - devid =3D readw(ssram + SSRAM_DEVID_OFFSET); - - pmc_ssram_telems[pmc_idx].devid =3D devid; - pmc_ssram_telems[pmc_idx].base_addr =3D pwrm_base; + pmc_ssram_get_devid_pwrmbase(ssram, pmc_idx); =20 /* Find and register and PMC telemetry entries */ return pmc_ssram_telemetry_add_pmt(pcidev, ssram_base, ssram); --=20 2.43.0 From nobody Sun May 24 20:33:05 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83EA0306757; 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Box" To: Rajneesh Bhardwaj , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Hans de Goede Cc: "David E. Box" , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Xi Pardee , Srinivas Pandruvada Subject: [PATCH v5 12/16] platform/x86/intel/pmc/ssram: Add PCI platform data Date: Thu, 21 May 2026 19:21:42 -0700 Message-ID: <20260522022147.4137494-13-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522022147.4137494-1-david.e.box@linux.intel.com> References: <20260522022147.4137494-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add per-device platform data for SSRAM telemetry PCI IDs and route probe through a method selector driven by id->driver_data. This is a preparatory refactor for follow-on discovery methods while preserving current behavior: all supported IDs continue to use the PCI initialization path. Signed-off-by: David E. Box --- V5 - No changes V4 - No changes V3 - No changes V2 changes: - Added missing include for dev_dbg() usage in probe .../platform/x86/intel/pmc/ssram_telemetry.c | 70 +++++++++++++++---- 1 file changed, 56 insertions(+), 14 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.c b/drivers/pla= tform/x86/intel/pmc/ssram_telemetry.c index 779e84c724ac..6917a10cbc80 100644 --- a/drivers/platform/x86/intel/pmc/ssram_telemetry.c +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.c @@ -7,6 +7,7 @@ =20 #include #include +#include #include #include #include @@ -26,6 +27,18 @@ =20 DEFINE_FREE(pmc_ssram_telemetry_iounmap, void __iomem *, if (_T) iounmap(_= T)) =20 +enum resource_method { + RES_METHOD_PCI, +}; + +struct ssram_type { + enum resource_method method; +}; + +static const struct ssram_type pci_main =3D { + .method =3D RES_METHOD_PCI, +}; + static struct pmc_ssram_telemetry pmc_ssram_telems[MAX_NUM_PMC]; static bool device_probed; =20 @@ -83,7 +96,7 @@ pmc_ssram_telemetry_add_pmt(struct pci_dev *pcidev, u64 s= sram_base, void __iomem } =20 static int -pmc_ssram_telemetry_get_pmc(struct pci_dev *pcidev, unsigned int pmc_idx, = u32 offset) +pmc_ssram_telemetry_get_pmc_pci(struct pci_dev *pcidev, unsigned int pmc_i= dx, u32 offset) { void __iomem __free(pmc_ssram_telemetry_iounmap) *tmp_ssram =3D NULL; void __iomem __free(pmc_ssram_telemetry_iounmap) *ssram =3D NULL; @@ -118,6 +131,20 @@ pmc_ssram_telemetry_get_pmc(struct pci_dev *pcidev, un= signed int pmc_idx, u32 of return pmc_ssram_telemetry_add_pmt(pcidev, ssram_base, ssram); } =20 +static int pmc_ssram_telemetry_pci_init(struct pci_dev *pcidev) +{ + int ret; + + ret =3D pmc_ssram_telemetry_get_pmc_pci(pcidev, PMC_IDX_MAIN, 0); + if (ret) + return ret; + + pmc_ssram_telemetry_get_pmc_pci(pcidev, PMC_IDX_IOE, SSRAM_IOE_OFFSET); + pmc_ssram_telemetry_get_pmc_pci(pcidev, PMC_IDX_PCH, SSRAM_PCH_OFFSET); + + return ret; +} + /** * pmc_ssram_telemetry_get_pmc_info() - Get a PMC devid and base_addr info= rmation * @pmc_idx: Index of the PMC @@ -160,8 +187,18 @@ EXPORT_SYMBOL_GPL(pmc_ssram_telemetry_get_pmc_info); =20 static int pmc_ssram_telemetry_probe(struct pci_dev *pcidev, const struct = pci_device_id *id) { + const struct ssram_type *ssram_type; + enum resource_method method; int ret; =20 + ssram_type =3D (const struct ssram_type *)id->driver_data; + if (!ssram_type) { + dev_dbg(&pcidev->dev, "missing driver data\n"); + ret =3D -EINVAL; + goto probe_finish; + } + + method =3D ssram_type->method; =20 ret =3D pcim_enable_device(pcidev); if (ret) { @@ -169,12 +206,10 @@ static int pmc_ssram_telemetry_probe(struct pci_dev *= pcidev, const struct pci_de goto probe_finish; } =20 - ret =3D pmc_ssram_telemetry_get_pmc(pcidev, PMC_IDX_MAIN, 0); - if (ret) - goto probe_finish; - - pmc_ssram_telemetry_get_pmc(pcidev, PMC_IDX_IOE, SSRAM_IOE_OFFSET); - pmc_ssram_telemetry_get_pmc(pcidev, PMC_IDX_PCH, SSRAM_PCH_OFFSET); + if (method =3D=3D RES_METHOD_PCI) + ret =3D pmc_ssram_telemetry_pci_init(pcidev); + else + ret =3D -EINVAL; =20 probe_finish: /* @@ -187,13 +222,20 @@ static int pmc_ssram_telemetry_probe(struct pci_dev *= pcidev, const struct pci_de } =20 static const struct pci_device_id pmc_ssram_telemetry_pci_ids[] =3D { - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_MTL_SOCM) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCS) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCM) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_LNL_SOCM) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_PTL_PCDH) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_PTL_PCDP) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_WCL_PCDN) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_MTL_SOCM), + .driver_data =3D (kernel_ulong_t)&pci_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCS), + .driver_data =3D (kernel_ulong_t)&pci_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCM), + .driver_data =3D (kernel_ulong_t)&pci_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_LNL_SOCM), + .driver_data =3D (kernel_ulong_t)&pci_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_PTL_PCDH), + .driver_data =3D (kernel_ulong_t)&pci_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_PTL_PCDP), + .driver_data =3D (kernel_ulong_t)&pci_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_WCL_PCDN), + .driver_data =3D (kernel_ulong_t)&pci_main }, { } }; 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X-CSE-ConnectionGUID: ApqVX96LR4aXMZdXLHYzKg== X-CSE-MsgGUID: O/RlRXHSTfGxLk9bUoGDaw== X-IronPort-AV: E=McAfee;i="6800,10657,11793"; a="80400557" X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="80400557" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:22:01 -0700 X-CSE-ConnectionGUID: 6IUoFVqFTRupgQo2qToEzQ== X-CSE-MsgGUID: eZW8erWjQz+Bi8djS8bD1g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="236335389" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:22:00 -0700 From: "David E. Box" To: Rajneesh Bhardwaj , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Hans de Goede Cc: Xi Pardee , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, "David E . Box" , Srinivas Pandruvada Subject: [PATCH v5 13/16] platform/x86/intel/pmc/ssram: Refactor memory barrier for reentrant probe Date: Thu, 21 May 2026 19:21:43 -0700 Message-ID: <20260522022147.4137494-14-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522022147.4137494-1-david.e.box@linux.intel.com> References: <20260522022147.4137494-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xi Pardee Previously, a single global 'device_probed' flag with memory barriers was used to prevent callers from reading PMC info before probe completion. The write barrier in probe ensured all data, devid and base_addr, was visible before signaling completion, and the read barrier in callers ensured they checked the flag before reading data. A following commit will make probe reentrant, requiring that a different synchronization flag be used since a single global flag cannot coordinate multiple concurrent probes. Switch to per-index devid publication. Each probe instance writes base_addr first, then a write barrier ensures visibility before devid is written as the completion signal. Callers check devid first, then use a read barrier before reading base_addr. This per-index approach allows multiple probes to work independently while maintaining the same memory ordering guarantees. Signed-off-by: Xi Pardee Signed-off-by: David E. Box --- V5 - No changes V4 - No changes V3 - No changes V2 changes: - Expanded commit message to explain synchronization rationale - Remove unused probe_finish label associated with the old global flag .../platform/x86/intel/pmc/ssram_telemetry.c | 40 ++++++++----------- 1 file changed, 16 insertions(+), 24 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.c b/drivers/pla= tform/x86/intel/pmc/ssram_telemetry.c index 6917a10cbc80..597bfb7ad822 100644 --- a/drivers/platform/x86/intel/pmc/ssram_telemetry.c +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.c @@ -40,7 +40,6 @@ static const struct ssram_type pci_main =3D { }; =20 static struct pmc_ssram_telemetry pmc_ssram_telems[MAX_NUM_PMC]; -static bool device_probed; =20 static inline u64 get_base(void __iomem *addr, u32 offset) { @@ -55,8 +54,13 @@ static void pmc_ssram_get_devid_pwrmbase(void __iomem *s= sram, unsigned int pmc_i pwrm_base =3D get_base(ssram, SSRAM_PWRM_OFFSET); devid =3D readw(ssram + SSRAM_DEVID_OFFSET); =20 - pmc_ssram_telems[pmc_idx].devid =3D devid; pmc_ssram_telems[pmc_idx].base_addr =3D pwrm_base; + /* + * Memory barrier is used to ensure the correct write order between base_= addr + * and devid. + */ + smp_wmb(); + pmc_ssram_telems[pmc_idx].devid =3D devid; } =20 static int @@ -154,32 +158,28 @@ static int pmc_ssram_telemetry_pci_init(struct pci_de= v *pcidev) * * 0 - Success * * -EAGAIN - Probe function has not finished yet. Try again. * * -EINVAL - Invalid pmc_idx - * * -ENODEV - PMC device is not available */ int pmc_ssram_telemetry_get_pmc_info(unsigned int pmc_idx, struct pmc_ssram_telemetry *pmc_ssram_telemetry) { + if (pmc_idx >=3D MAX_NUM_PMC) + return -EINVAL; + /* * PMCs are discovered in probe function. If this function is called befo= re - * probe function complete, the result would be invalid. Use device_probed - * variable to avoid this case. Return -EAGAIN to inform the consumer to = call + * probe function complete, the result would be invalid. Use devid to avo= id + * this case. Return -EAGAIN to inform the consumer to call * again later. */ - if (!device_probed) + if (!pmc_ssram_telems[pmc_idx].devid) return -EAGAIN; =20 + pmc_ssram_telemetry->devid =3D pmc_ssram_telems[pmc_idx].devid; /* * Memory barrier is used to ensure the correct read order between - * device_probed variable and PMC info. + * devid variable and base_addr. */ smp_rmb(); - if (pmc_idx >=3D MAX_NUM_PMC) - return -EINVAL; - - if (!pmc_ssram_telems[pmc_idx].devid) - return -ENODEV; - - pmc_ssram_telemetry->devid =3D pmc_ssram_telems[pmc_idx].devid; pmc_ssram_telemetry->base_addr =3D pmc_ssram_telems[pmc_idx].base_addr; return 0; } @@ -194,8 +194,7 @@ static int pmc_ssram_telemetry_probe(struct pci_dev *pc= idev, const struct pci_de ssram_type =3D (const struct ssram_type *)id->driver_data; if (!ssram_type) { dev_dbg(&pcidev->dev, "missing driver data\n"); - ret =3D -EINVAL; - goto probe_finish; + return -EINVAL; } =20 method =3D ssram_type->method; @@ -203,7 +202,7 @@ static int pmc_ssram_telemetry_probe(struct pci_dev *pc= idev, const struct pci_de ret =3D pcim_enable_device(pcidev); if (ret) { dev_dbg(&pcidev->dev, "failed to enable PMC SSRAM device\n"); - goto probe_finish; + return ret; } =20 if (method =3D=3D RES_METHOD_PCI) @@ -211,13 +210,6 @@ static int pmc_ssram_telemetry_probe(struct pci_dev *p= cidev, const struct pci_de else ret =3D -EINVAL; =20 -probe_finish: - /* - * Memory barrier is used to ensure the correct write order between PMC i= nfo - * and device_probed variable. - */ - smp_wmb(); - device_probed =3D true; return ret; } =20 --=20 2.43.0 From nobody Sun May 24 20:33:05 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE23F303CAB; Fri, 22 May 2026 02:22:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779416538; cv=none; b=V8IMoHDhKUu6KVbdo0z28DFLSrW3V2Se+dgjcEFtAwAA3ewjSGPZOUHCNORtBTJlqKrdaF/VKhIht0XWO2fmnv+hOBdqXXYEs5xJebb+jm4PJSnIapKJVyZoX8YF9a/XS8sz5mFrGQoZhm4DuAefqthnKqn7gcl8a+beJmWQk1I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779416538; c=relaxed/simple; bh=tmeJ+WXY0BWC6W/I2Hzy7tRHN3mPL3ta4fHoMj/2qmc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bLiXaMMQb5AvZllyX0vt5FZMrFkNFtyRjCaZnzo7/7r3sjiOtGnAJVAUYplgV/vNIxjJs3BthN8hzOAvopCGosRI1LAfZD4ifo9HJ78to3CKRMdlxzR5XI1PbyMl2GIAM2QU/282n4ADZAmE9V6Y0qR5okCcsEFWvS8DMwztAZw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=epUCvJf7; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="epUCvJf7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779416537; x=1810952537; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tmeJ+WXY0BWC6W/I2Hzy7tRHN3mPL3ta4fHoMj/2qmc=; b=epUCvJf7NdwrY/0qmkBkJUm7IDxhPuEnFQ7M+cJGkMCF/+n0ZwwTgTIH 8nUmeX4PLP8nxBAq+6r12G02OMmj45eWnoGv7VvjF7ECVnI49OkKvgy4f ARMO3lSKmDi8ElbX4K969A0ZSxdvOdsL/TzshJhMmhKmf/TaaADy63Gk/ Q/QNsXD7NCt8No7CjXCpv05ZwwjYjGV3FbvWYFSzKHNxHtajKy6hQQJT9 twQ5o7ZgbiNRCE7+vhKcMFsBtMosbvbJSlN2/RoKSJg/SsDzMFaTKxJBR w47N6lgDLHp80aLG61XkiXug5/hSBcuFoMazPTMybAp6EbCwUYC8MLq7y A==; X-CSE-ConnectionGUID: 9xKD0yeiSpSgzGS9C9qMZw== X-CSE-MsgGUID: Ms4CF3fMRBiqJ6NmRmTDsQ== X-IronPort-AV: E=McAfee;i="6800,10657,11793"; a="80400562" X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="80400562" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:22:01 -0700 X-CSE-ConnectionGUID: 8CD55Ya6QkmgoT4Fo5Y6pw== X-CSE-MsgGUID: 9QRnOH6LTY2w0dxnh1jUrA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="236335390" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:22:00 -0700 From: "David E. Box" To: Rajneesh Bhardwaj , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Hans de Goede Cc: "David E. Box" , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Xi Pardee , Srinivas Pandruvada Subject: [PATCH v5 14/16] platform/x86/intel/pmc/ssram: Add ACPI discovery scaffolding Date: Thu, 21 May 2026 19:21:44 -0700 Message-ID: <20260522022147.4137494-15-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522022147.4137494-1-david.e.box@linux.intel.com> References: <20260522022147.4137494-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Prepare the SSRAM telemetry driver for ACPI-based discovery by adding the common initialization path and selection framework needed for both PCI and ACPI resource discovery. At this stage, existing supported devices continue to use the PCI path. This change lays the groundwork for follow-on patches that wire platform IDs to the ACPI policy path. Assisted-by: GitHub-Copilot:claude-opus-4.7 Signed-off-by: Xi Pardee Signed-off-by: David E. Box --- V5 changes: - Fix dsd_buf leak by moving the __free(pmc_acpi_free) declaration after acpi_evaluate_object() populates buf.pointer, and switched pmc_find_telem_guid(buf.pointer) to operate on dsd_buf so cleanup releases the actual allocation. - Split acpi_handle declaration from ACPI_HANDLE() assignment and placed the assignment immediately before the !handle check (Ilpo). - Reordered local variables in pmc_ssram_telemetry_acpi_init() in reverse-xmas-tree order (Ilpo). V4 - Replaced local raw ACPI discovery pointer type u32 (*)[4] with acpi_disc_t in SSRAM ACPI initialization path. V3 - No changes V2 changes: - Fixed cleanup patterns using __free() attributes - Addressed Ilpo's recommendations for safer cleanup.h patterns .../platform/x86/intel/pmc/ssram_telemetry.c | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.c b/drivers/pla= tform/x86/intel/pmc/ssram_telemetry.c index 597bfb7ad822..ac330f7df649 100644 --- a/drivers/platform/x86/intel/pmc/ssram_telemetry.c +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.c @@ -5,6 +5,7 @@ * Copyright (c) 2023, Intel Corporation. */ =20 +#include #include #include #include @@ -29,14 +30,17 @@ DEFINE_FREE(pmc_ssram_telemetry_iounmap, void __iomem *= , if (_T) iounmap(_T)) =20 enum resource_method { RES_METHOD_PCI, + RES_METHOD_ACPI, }; =20 struct ssram_type { enum resource_method method; + enum pmc_index p_index; }; =20 static const struct ssram_type pci_main =3D { .method =3D RES_METHOD_PCI, + .p_index =3D PMC_IDX_MAIN, }; =20 static struct pmc_ssram_telemetry pmc_ssram_telems[MAX_NUM_PMC]; @@ -149,6 +153,69 @@ static int pmc_ssram_telemetry_pci_init(struct pci_dev= *pcidev) return ret; } =20 +static int pmc_ssram_telemetry_get_pmc_acpi(struct pci_dev *pcidev, unsig= ned int pmc_idx) +{ + u64 ssram_base; + + ssram_base =3D pci_resource_start(pcidev, 0); + if (!ssram_base) + return -ENODEV; + + void __iomem __free(pmc_ssram_telemetry_iounmap) *ssram =3D + ioremap(ssram_base, SSRAM_HDR_SIZE); + if (!ssram) + return -ENOMEM; + + pmc_ssram_get_devid_pwrmbase(ssram, pmc_idx); + + return 0; +} + +static int pmc_ssram_telemetry_acpi_init(struct pci_dev *pcidev, + enum pmc_index index) +{ + struct intel_vsec_header header; + struct intel_vsec_header *headers[2] =3D { &header, NULL }; + struct acpi_buffer buf =3D { ACPI_ALLOCATE_BUFFER, NULL }; + struct intel_vsec_platform_info info =3D { }; + union acpi_object *dsd; + acpi_handle handle; + acpi_status status; + int ret; + + handle =3D ACPI_HANDLE(&pcidev->dev); + if (!handle) + return -ENODEV; + + status =3D acpi_evaluate_object(handle, "_DSD", NULL, &buf); + if (ACPI_FAILURE(status)) + return -ENODEV; + + void *dsd_buf __free(pmc_acpi_free) =3D buf.pointer; + + dsd =3D pmc_find_telem_guid(dsd_buf); + if (!dsd) + return -ENODEV; + + acpi_disc_t disc __free(kfree) =3D pmc_parse_telem_dsd(dsd, &header); + if (IS_ERR(disc)) + return PTR_ERR(disc); + + info.headers =3D headers; + info.caps =3D VSEC_CAP_TELEMETRY; + info.acpi_disc =3D disc; + info.src =3D INTEL_VSEC_DISC_ACPI; + + /* This is an ACPI companion device. PCI BAR will be used for base addr. = */ + info.base_addr =3D 0; + + ret =3D intel_vsec_register(&pcidev->dev, &info); + if (ret) + return ret; + + return pmc_ssram_telemetry_get_pmc_acpi(pcidev, index); +} + /** * pmc_ssram_telemetry_get_pmc_info() - Get a PMC devid and base_addr info= rmation * @pmc_idx: Index of the PMC @@ -189,6 +256,7 @@ static int pmc_ssram_telemetry_probe(struct pci_dev *pc= idev, const struct pci_de { const struct ssram_type *ssram_type; enum resource_method method; + enum pmc_index index; int ret; =20 ssram_type =3D (const struct ssram_type *)id->driver_data; @@ -198,6 +266,7 @@ static int pmc_ssram_telemetry_probe(struct pci_dev *pc= idev, const struct pci_de } =20 method =3D ssram_type->method; + index =3D ssram_type->p_index; =20 ret =3D pcim_enable_device(pcidev); if (ret) { @@ -207,6 +276,8 @@ static int pmc_ssram_telemetry_probe(struct pci_dev *pc= idev, const struct pci_de =20 if (method =3D=3D RES_METHOD_PCI) ret =3D pmc_ssram_telemetry_pci_init(pcidev); + else if (method =3D=3D RES_METHOD_ACPI) + ret =3D pmc_ssram_telemetry_acpi_init(pcidev, index); else ret =3D -EINVAL; =20 @@ -239,6 +310,7 @@ static struct pci_driver pmc_ssram_telemetry_driver =3D= { }; module_pci_driver(pmc_ssram_telemetry_driver); =20 +MODULE_IMPORT_NS("INTEL_PMC_CORE"); MODULE_IMPORT_NS("INTEL_VSEC"); MODULE_AUTHOR("Xi Pardee "); MODULE_DESCRIPTION("Intel PMC SSRAM Telemetry driver"); --=20 2.43.0 From nobody Sun May 24 20:33:05 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4180730ACF0; Fri, 22 May 2026 02:22:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779416538; cv=none; b=N3XcQcAvF7cA5ona+BN1E/8sfXSEGrfk5dS4qfi0xRKPAvpBvWFn9OGEFWtOKC0bWmh1m1OV9AjtxlSA3lzLkPNLLG2c/5QtyPEUoAVwXJ+YaAXcY4lQQUOPC9QInP/cMEnF5q6obSXDneg79P7fEubfc60q1sFQIMw6/Gy/8VA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779416538; c=relaxed/simple; bh=oknUfrrsvhjlI2wS0WGt5lQDxEja8y1+dwcnUHq234c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Sd40QoCT9WIk0fa6p1/bSk42HgESuw/GsuxsiJYpErwxDXDfu86F6ReBaW+8btgnSdAPMlTBBmUzvBCHMVd/mFAG5chxf1OYF2rYmZUyfCLsGnGQ2Co4O77eYrRO4qXuZBL/RUjPAdO1VVYeUX1NFdiDc6+BVcFQYmz+mYA2xsA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=IaxEX2CE; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="IaxEX2CE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779416537; x=1810952537; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oknUfrrsvhjlI2wS0WGt5lQDxEja8y1+dwcnUHq234c=; b=IaxEX2CE8R61HsDVVcVKlRPXEsCVNTQ6phhoNGbX5xaE45EMQfHu1RqU AvVwzHbqzR3zqJcjRCF44OP7664EEktEGa6a/UZuluNNOLl2SQRpOL8K1 MUC56S+uWxd0G893o1QUHOR3X794ACz5IqDH9Ovf4pMoqytgACcacmqGy 1Pmqbh8LCZVXhQ5Us8ubLWesPEpw2gifFZYdU3tOIx2IGgwBikuW4ncRU RjzywcFyeexMXYDtx4WloOiyWHWqQ7A77ldI954LHUKDMWoFdhI6A05kt LtFtgrhlJ06ak1Z+aFzgYQUuh/OQUR7mQmpS72EEvVmKa88rVxFyM48qR Q==; X-CSE-ConnectionGUID: jl2UOG0cTL+dHSCxHBFVsw== X-CSE-MsgGUID: vfdTdB4PT2KLtMpfrFgu6g== X-IronPort-AV: E=McAfee;i="6800,10657,11793"; a="80400565" X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="80400565" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:22:01 -0700 X-CSE-ConnectionGUID: ZXIZiS/3Q4uiyuXEwikZ3Q== X-CSE-MsgGUID: Fe5INISLR2yAjA2wCRndvA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="236335393" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:22:01 -0700 From: "David E. Box" To: Rajneesh Bhardwaj , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Hans de Goede Cc: "David E. Box" , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Xi Pardee , Srinivas Pandruvada Subject: [PATCH v5 15/16] platform/x86/intel/pmc/ssram: Make PMT registration optional Date: Thu, 21 May 2026 19:21:45 -0700 Message-ID: <20260522022147.4137494-16-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522022147.4137494-1-david.e.box@linux.intel.com> References: <20260522022147.4137494-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SSRAM telemetry driver extracts essential PMC device ID and power management base address information that intel_pmc_core depends on for core functionality. If PMT registration failure prevents this critical data from being available, intel_pmc_core operation would break entirely. Therefore, PMT registration failures must not block access to this data. Change the behavior to log a warning when PMT registration fails but continue with successful driver initialization, ensuring the primary telemetry data remains accessible to dependent drivers. Signed-off-by: David E. Box --- V5 - No changes V4 - No changes V3 changes: - Dropped the standalone cleanup-pattern patch from this refreshed series retaining the simpler ssram pointer flow requested in review. - Folded PMT-registration-optional handling onto that simpler flow with no intended functional change. V2 changes: - Update commit message for clarity - Also apply the PCI telemetry path drivers/platform/x86/intel/pmc/ssram_telemetry.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.c b/drivers/pla= tform/x86/intel/pmc/ssram_telemetry.c index ac330f7df649..7bb699116bd0 100644 --- a/drivers/platform/x86/intel/pmc/ssram_telemetry.c +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.c @@ -109,6 +109,7 @@ pmc_ssram_telemetry_get_pmc_pci(struct pci_dev *pcidev,= unsigned int pmc_idx, u3 void __iomem __free(pmc_ssram_telemetry_iounmap) *tmp_ssram =3D NULL; void __iomem __free(pmc_ssram_telemetry_iounmap) *ssram =3D NULL; u64 ssram_base; + int ret; =20 ssram_base =3D pci_resource_start(pcidev, 0); tmp_ssram =3D ioremap(ssram_base, SSRAM_HDR_SIZE); @@ -128,7 +129,6 @@ pmc_ssram_telemetry_get_pmc_pci(struct pci_dev *pcidev,= unsigned int pmc_idx, u3 ssram =3D ioremap(ssram_base, SSRAM_HDR_SIZE); if (!ssram) return -ENOMEM; - } else { ssram =3D no_free_ptr(tmp_ssram); } @@ -136,7 +136,11 @@ pmc_ssram_telemetry_get_pmc_pci(struct pci_dev *pcidev= , unsigned int pmc_idx, u3 pmc_ssram_get_devid_pwrmbase(ssram, pmc_idx); =20 /* Find and register and PMC telemetry entries */ - return pmc_ssram_telemetry_add_pmt(pcidev, ssram_base, ssram); + ret =3D pmc_ssram_telemetry_add_pmt(pcidev, ssram_base, ssram); + if (ret) + dev_warn(&pcidev->dev, "could not register PMT\n"); + + return 0; } =20 static int pmc_ssram_telemetry_pci_init(struct pci_dev *pcidev) @@ -211,7 +215,7 @@ static int pmc_ssram_telemetry_acpi_init(struct pci_dev= *pcidev, =20 ret =3D intel_vsec_register(&pcidev->dev, &info); if (ret) - return ret; + dev_warn(&pcidev->dev, "could not register PMT\n"); =20 return pmc_ssram_telemetry_get_pmc_acpi(pcidev, index); } --=20 2.43.0 From nobody Sun May 24 20:33:05 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3777330BB97; Fri, 22 May 2026 02:22:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779416539; cv=none; b=s9ktKbVqD7YLtz0mu4Co6l2S12tFxbnBxq+oCltd/uyhdrP69u7WvQWGyJiuVN5ETMApcNv+KFjFfKUJPvx9TtcpSMaCipCdrQ5VzjOTuqTmxqEQOCaYdKCRUZ3okuX73XLC4Nr6bGzLHR8mjDAK6ehb++cmYHbKt3Olj69ejLM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779416539; c=relaxed/simple; bh=cQfS+I4QZv9Gn9FVk+M5JCg2z7p+A+zFXw+A6GIqIWo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=d+QMNO/rxcPuMyHkxj+uK8ooRnW9e2OI3JIKs5U1xCBL/F1oAALMIDlShxFBFhICNY+L2a5TreHgsHmtfhiHH4AWYSPlMgpffGUxCrn7R9DI4gsKvKHntO5vBTxRALkfK7pX8w/XPDx5hfGAbc/376JpXPj2zgfatM7UHjEzvqo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=IY97ox0u; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="IY97ox0u" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779416538; x=1810952538; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cQfS+I4QZv9Gn9FVk+M5JCg2z7p+A+zFXw+A6GIqIWo=; b=IY97ox0uvibgamOxn3+FzBlKK4xoVc7iD6lKEnoFnjdihmeUy1VVfFc6 ZgcfQ9/Ync8KjneJQwq6FJjwTrs8yPdSpAeq9nG0ISQL0o3QkJ6VHMsx5 SddUpcwZL8Pt0d2sd+f9wseqA9f3C5nUYEJ1NfwrH0uZWfkrUNpnkHsUl O+hwCXDCKQkpMujJS6PlHwYs+kJkz/C+gWtNrBT62M83zLVxEz/W8EoAL l2LsHlM2stOoAlorDmhz+OKm0pfzMInvAA8k0BzUiLDny8zIgzJ3Mk82u NxLo44h477l1kpjKKGP/a7ePchm6GzKgou7q+I5gTtwKtFTFnLbpITEwq w==; X-CSE-ConnectionGUID: z8m9EsCuRzuNDaVF1EB+zw== X-CSE-MsgGUID: CC+CzwIRQMGnRNboDXJz6g== X-IronPort-AV: E=McAfee;i="6800,10657,11793"; a="80400569" X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="80400569" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:22:01 -0700 X-CSE-ConnectionGUID: kIPw94bpSk20fmD55yRcFg== X-CSE-MsgGUID: h329mbXHS6q9QnDzK/eGGQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,161,1774335600"; d="scan'208";a="236335395" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 19:22:01 -0700 From: "David E. Box" To: Rajneesh Bhardwaj , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Hans de Goede Cc: "David E. Box" , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Xi Pardee , Srinivas Pandruvada Subject: [PATCH v5 16/16] platform/x86/intel/pmc: Add NVL PCI IDs for SSRAM telemetry discovery Date: Thu, 21 May 2026 19:21:46 -0700 Message-ID: <20260522022147.4137494-17-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522022147.4137494-1-david.e.box@linux.intel.com> References: <20260522022147.4137494-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Nova Lake S PMC device IDs to enable binding of the SSRAM telemetry driver on NVL platforms, and map them to the ACPI-based discovery policy. Signed-off-by: David E. Box --- V5 - No changes V4 - No changes V3 - No changes V2 - No changes drivers/platform/x86/intel/pmc/core.h | 5 +++++ drivers/platform/x86/intel/pmc/ssram_telemetry.c | 16 ++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/i= ntel/pmc/core.h index f458eb908c07..eb2e1030dbf3 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -334,6 +334,11 @@ enum ppfear_regs { #define PMC_DEVID_MTL_IOEP 0x7ecf #define PMC_DEVID_MTL_IOEM 0x7ebf =20 +/* NVL */ +#define PMC_DEVID_NVL_PCDH 0xd37e +#define PMC_DEVID_NVL_PCDS 0xd47e +#define PMC_DEVID_NVL_PCHS 0x6e27 + extern const char *pmc_lpm_modes[]; =20 struct pmc_bit_map { diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.c b/drivers/pla= tform/x86/intel/pmc/ssram_telemetry.c index 7bb699116bd0..3ca577fb0eb8 100644 --- a/drivers/platform/x86/intel/pmc/ssram_telemetry.c +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.c @@ -43,6 +43,16 @@ static const struct ssram_type pci_main =3D { .p_index =3D PMC_IDX_MAIN, }; =20 +static const struct ssram_type acpi_main =3D { + .method =3D RES_METHOD_ACPI, + .p_index =3D PMC_IDX_MAIN, +}; + +static const struct ssram_type acpi_pch =3D { + .method =3D RES_METHOD_ACPI, + .p_index =3D PMC_IDX_PCH, +}; + static struct pmc_ssram_telemetry pmc_ssram_telems[MAX_NUM_PMC]; =20 static inline u64 get_base(void __iomem *addr, u32 offset) @@ -303,6 +313,12 @@ static const struct pci_device_id pmc_ssram_telemetry_= pci_ids[] =3D { .driver_data =3D (kernel_ulong_t)&pci_main }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_WCL_PCDN), .driver_data =3D (kernel_ulong_t)&pci_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_NVL_PCDH), + .driver_data =3D (kernel_ulong_t)&acpi_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_NVL_PCDS), + .driver_data =3D (kernel_ulong_t)&acpi_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_NVL_PCHS), + .driver_data =3D (kernel_ulong_t)&acpi_pch }, { } }; MODULE_DEVICE_TABLE(pci, pmc_ssram_telemetry_pci_ids); --=20 2.43.0