From nobody Sun May 24 18:45:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 395E73D3D0B; Fri, 22 May 2026 10:56:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779447399; cv=none; b=ZwffUqvrBh+/3e5Ivh8S3/rMmupCstIcsoUmImME7G5MVtiL8fwipud2miFVV1G1nCth4U2KHrL1CGh6K10sKFhWfSSHq/lHPgMfGBJOImPEhMLNQ3WJvure8RLRGod6rg2+Dyjwks2K6+5r/rTguDwmONBOJvAcOR6HdbaHgCc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779447399; c=relaxed/simple; bh=qvZkhlsuEcZSEcwblgQKPCcuS85u2WzNyPhtl+l61pM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=G3TGnIyz5hofbFoecg+i48vFqtWbojMnYpJlNDBkpXvTjHrfbK6ZC7NalOhv57nzY/Kep2FT2bqbGBKn7y/c2wTWlBuWCE4hhxBVtn0SzDJfvM7W21qmMDOBSzkV+blBDgQxw5sKIj1+4Zb/1hA307bU5+AVr/F80pEDZTCElxU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eTzmN3Bv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eTzmN3Bv" Received: by smtp.kernel.org (Postfix) with ESMTPS id E42C0C2BCB8; Fri, 22 May 2026 10:56:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779447399; bh=qvZkhlsuEcZSEcwblgQKPCcuS85u2WzNyPhtl+l61pM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=eTzmN3BvNAZpQt6KH+mOS+9uSpdKo/MRgdlg8hsRnB9NEf+08TvlfMg0TALMxKl/v 9Iujx/QEqWE198amR3dZ0SP/ji/S50HPK/XCsvamHiiEACvZLHZwbCWTX+jbUEfc2t EJliJGnMlL8RoIYHzDLfuXekSjA8Mz2rJYC1zLY7VsDqZEvoqGZ1h8vOM8asE2iBkK Gp4tzNFti2DWTbaM8XLp0V3UDdJnXAp6m8DPel51XNOpDWFdv5AiTv8IfzuTx1QgeX Zw3588dBF22sYjTR8UjGtgnSRqqunRdPmUyBayiSGgq+5OmEwRUNiZ95QgN7bn5c8L J9JJ+b/jd+2Pw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEB76CD5BB0; Fri, 22 May 2026 10:56:38 +0000 (UTC) From: Cedric Jehasse via B4 Relay Date: Fri, 22 May 2026 12:56:22 +0200 Subject: [PATCH net-next 1/2] net: dsa: mv88e6xxx: use the hw tx queues Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260522-net-next-mv88e6xxx-cbs-v1-1-c87a8e6bcc0c@luminex.be> References: <20260522-net-next-mv88e6xxx-cbs-v1-0-c87a8e6bcc0c@luminex.be> In-Reply-To: <20260522-net-next-mv88e6xxx-cbs-v1-0-c87a8e6bcc0c@luminex.be> To: Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Cedric Jehasse X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779447397; l=5690; i=cedric.jehasse@luminex.be; s=20260213; h=from:subject:message-id; bh=weJ0Zyvyvl6ZsDGuiTxfE/omgcZa+1TFkl/4LE6ZKXM=; b=hlErBP1KeucV7W1+3Qh82MJaPO2KntUuYh7DGJKqdz6c4hRZoGqLjfR4C0lvOUwvUHv9IGBPE KKsvsV/MoH6C8/jOq2UMgbtcvKH+bosc+DMqRrOAH66uvlNDQleArRl X-Developer-Key: i=cedric.jehasse@luminex.be; a=ed25519; pk=DL2RaHc2bc7tTDTMJdugm42BtJk4Ip+7V41Gkj+Avjk= X-Endpoint-Received: by B4 Relay for cedric.jehasse@luminex.be/20260213 with auth_id=638 X-Original-From: Cedric Jehasse Reply-To: cedric.jehasse@luminex.be From: Cedric Jehasse From the datasheets i've looked at these switches have 4 or 8 transmit queues per port. There's a PRI field in the dsa tag used to indicate which egress queue the frame is to be sent to. This isn't done for vlan tagged frames because this would overwrite the PCP value in the vlan tag (The PRI field in the dsa tag is used as the PCP value in the vlan tag). Signed-off-by: Cedric Jehasse --- drivers/net/dsa/mv88e6xxx/chip.c | 14 ++++++++++++++ drivers/net/dsa/mv88e6xxx/chip.h | 1 + net/dsa/tag_dsa.c | 3 ++- 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/c= hip.c index 8ca5fd40df92..277efe24edf4 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -3979,6 +3979,7 @@ static int mv88e6xxx_setup(struct dsa_switch *ds) =20 chip->ds =3D ds; ds->user_mii_bus =3D mv88e6xxx_default_mdio_bus(chip); + ds->num_tx_queues =3D chip->info->num_tx_queues; =20 /* Since virtual bridges are mapped in the PVT, the number we support * depends on the physical switch topology. We need to let DSA figure @@ -6051,6 +6052,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .num_ports =3D 11, /* 10 + Z80 */ .num_internal_phys =3D 9, .num_gpio =3D 16, + .num_tx_queues =3D 8, .max_vid =3D 8191, .max_sid =3D 63, .port_base_addr =3D 0x0, @@ -6076,6 +6078,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .num_ports =3D 11, /* 10 + Z80 */ .num_internal_phys =3D 9, .num_gpio =3D 16, + .num_tx_queues =3D 8, .max_vid =3D 8191, .max_sid =3D 63, .port_base_addr =3D 0x0, @@ -6125,6 +6128,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .num_ports =3D 11, /* 10 + Z80 */ .num_internal_phys =3D 8, .internal_phys_offset =3D 1, + .num_tx_queues =3D 8, .max_vid =3D 8191, .max_sid =3D 63, .port_base_addr =3D 0x0, @@ -6151,6 +6155,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .num_internal_phys =3D 8, .num_tcam_entries =3D 256, .internal_phys_offset =3D 1, + .num_tx_queues =3D 8, .max_vid =3D 8191, .max_sid =3D 63, .port_base_addr =3D 0x0, @@ -6181,6 +6186,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .num_ports =3D 7, .num_internal_phys =3D 2, .invalid_port_mask =3D BIT(2) | BIT(3) | BIT(4), + .num_tx_queues =3D 4, .max_vid =3D 4095, .port_base_addr =3D 0x08, .phy_base_addr =3D 0x00, @@ -6205,6 +6211,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .num_ports =3D 7, .num_internal_phys =3D 5, .num_gpio =3D 15, + .num_tx_queues =3D 4, .max_vid =3D 4095, .max_sid =3D 63, .port_base_addr =3D 0x10, @@ -6230,6 +6237,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .num_databases =3D 64, .num_ports =3D 7, .num_internal_phys =3D 5, + .num_tx_queues =3D 4, .max_vid =3D 4095, .port_base_addr =3D 0x08, .phy_base_addr =3D 0x00, @@ -6282,6 +6290,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .num_internal_phys =3D 2, .internal_phys_offset =3D 3, .num_gpio =3D 15, + .num_tx_queues =3D 4, .max_vid =3D 4095, .max_sid =3D 63, .port_base_addr =3D 0x10, @@ -6310,6 +6319,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .num_internal_phys =3D 2, .internal_phys_offset =3D 3, .num_gpio =3D 15, + .num_tx_queues =3D 4, .max_vid =3D 4095, .max_sid =3D 63, .port_base_addr =3D 0x10, @@ -6414,6 +6424,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .num_ports =3D 7, .num_internal_phys =3D 5, .num_gpio =3D 15, + .num_tx_queues =3D 4, .max_vid =3D 4095, .max_sid =3D 63, .port_base_addr =3D 0x10, @@ -6468,6 +6479,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .num_internal_phys =3D 9, .num_gpio =3D 16, .num_tcam_entries =3D 256, + .num_tx_queues =3D 8, .max_vid =3D 8191, .max_sid =3D 63, .port_base_addr =3D 0x0, @@ -6495,6 +6507,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .num_ports =3D 11, /* 10 + Z80 */ .num_internal_phys =3D 9, .num_gpio =3D 16, + .num_tx_queues =3D 8, .max_vid =3D 8191, .max_sid =3D 63, .port_base_addr =3D 0x0, @@ -6521,6 +6534,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .num_ports =3D 11, /* 10 + Z80 */ .num_internal_phys =3D 8, .num_tcam_entries =3D 256, + .num_tx_queues =3D 8, .internal_phys_offset =3D 1, .max_vid =3D 8191, .max_sid =3D 63, diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/c= hip.h index cde71828e9d9..19d8eda19b78 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.h +++ b/drivers/net/dsa/mv88e6xxx/chip.h @@ -136,6 +136,7 @@ struct mv88e6xxx_info { unsigned int num_internal_phys; unsigned int num_gpio; unsigned int num_tcam_entries; + unsigned int num_tx_queues; unsigned int max_vid; unsigned int max_sid; unsigned int port_base_addr; diff --git a/net/dsa/tag_dsa.c b/net/dsa/tag_dsa.c index 2a2c4fb61a65..96c8fbedbd3b 100644 --- a/net/dsa/tag_dsa.c +++ b/net/dsa/tag_dsa.c @@ -179,6 +179,7 @@ static struct sk_buff *dsa_xmit_ll(struct sk_buff *skb,= struct net_device *dev, dsa_header[2] &=3D ~0x10; } } else { + u16 queue =3D skb_get_queue_mapping(skb) & 0x7; u16 vid; =20 vid =3D br_dev ? MV88E6XXX_VID_BRIDGED : MV88E6XXX_VID_STANDALONE; @@ -191,7 +192,7 @@ static struct sk_buff *dsa_xmit_ll(struct sk_buff *skb,= struct net_device *dev, =20 dsa_header[0] =3D (cmd << 6) | tag_dev; dsa_header[1] =3D tag_port << 3; - dsa_header[2] =3D vid >> 8; + dsa_header[2] =3D (queue << 5) | vid >> 8; dsa_header[3] =3D vid & 0xff; } =20 --=20 2.43.0 From nobody Sun May 24 18:45:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 396EB3D3D15; Fri, 22 May 2026 10:56:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779447399; cv=none; b=QvAwl0IVgO/Hsc615NHy9DfHkMlFlCiOdutuzntDtPFRRXRpm+zQ4h402eob3aRBUFNzRjJ9bmF/XezFSNEsQaY5MZmcQNAy7q4X0x0SsC3tWn/GiYqZgTY6JLyG4PB94sXhpPIxr3V3ywED3gAJLDSZL84XQjpgIFzK1MK2bcA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779447399; c=relaxed/simple; bh=Eccir+L/ynB6UXt2UEd+YQqamh3dZIa4jbLNUU6lIxg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HejddeWCWx8ORIpeMKNpvsUCsMzy4j8oqD1/b+Wf+pjuw2SEiFEK0pkN+Y8/nind7SNHZ1usVYrjk0Nwoeb+x28HE8AzRsKlKHFFgoqx6/bcdvw37L3GWHQpAcEH6kIDZhlbs6VctA9BaPZJep8zdacbC5s6798F9QBUR0p0JjU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SD29LU2a; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SD29LU2a" Received: by smtp.kernel.org (Postfix) with ESMTPS id F1780C2BCB9; Fri, 22 May 2026 10:56:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779447399; bh=Eccir+L/ynB6UXt2UEd+YQqamh3dZIa4jbLNUU6lIxg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=SD29LU2ajqwk+G6CK9v0/IKQrw9j36sfg+bC5VhvSaU+vjY77tmROXHF6D3AK8dzS U0rVMj2HGbYiyrADTwG2z051ewgu7RFPsND5ftmfJFiv09jD1RB5YiYD7itYH/iQXR vpjJobiQu8SqZuS2Z5BJUbVCgCCN7LdMrbozcfrazWsR9tZf5MeBy026w31k3f0q2L nnqqob6rrookfYxrhk3RLF0+YOxo6ybIwqs3Y9HCuHrw8cFCuFSM/yaHhpUfGw8qBW WHpzB/phymFVVVVIp3MvdsbTNrMYT9ZKHkxfREC0mv7uUPNQH/GiGpPcYIf8MUTDvR nH72f4eA9LScQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDFA2CD5BB5; Fri, 22 May 2026 10:56:38 +0000 (UTC) From: Cedric Jehasse via B4 Relay Date: Fri, 22 May 2026 12:56:23 +0200 Subject: [PATCH net-next 2/2] net: dsa: mv88e6xxx: add support for credit based shaper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260522-net-next-mv88e6xxx-cbs-v1-2-c87a8e6bcc0c@luminex.be> References: <20260522-net-next-mv88e6xxx-cbs-v1-0-c87a8e6bcc0c@luminex.be> In-Reply-To: <20260522-net-next-mv88e6xxx-cbs-v1-0-c87a8e6bcc0c@luminex.be> To: Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Cedric Jehasse X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779447397; l=16836; i=cedric.jehasse@luminex.be; s=20260213; h=from:subject:message-id; bh=a2nzZRsan9vPMcGHCePo50OttjHHB7486Gi2UIgJNqQ=; b=+j7wDcH7gtTwdxkYQ0UHxULYp6Sx9kxgiB3o2l6DXSHC8SX58CZ7z03fQ2Vn1KRL0b4U4DxJq PtUC1JCYjzxDK46mddnP53rQyVbWiTm6AHhQmDz3lsUOYJQ0Uv4E/dl X-Developer-Key: i=cedric.jehasse@luminex.be; a=ed25519; pk=DL2RaHc2bc7tTDTMJdugm42BtJk4Ip+7V41Gkj+Avjk= X-Endpoint-Received: by B4 Relay for cedric.jehasse@luminex.be/20260213 with auth_id=638 X-Original-From: Cedric Jehasse Reply-To: cedric.jehasse@luminex.be From: Cedric Jehasse Some of the chips supported by this driver have credit based shaper support. Support is added for the 6352, 6390 and 6393 families. This is configured using the Qav registers in the AVB register block. There are small differences in the Qav registers between the chip families (eg. the unit used for the rate and number of bits in the registers). mv88e6xxx_qav_info is introduced to configure this per chip. Eg. setting up 20mbps credit based shaper on a 1GBit link: tc qdisc add dev p8 parent root handle 100: mqprio \ num_tc 8 \ map 0 0 6 7 0 5 0 0 0 0 0 0 0 0 0 0 \ queues 1@0 1@1 1@2 1@3 1@4 1@5 1@6 1@7 \ hw 0 tc qdisc replace dev p8 parent 100:8 cbs locredit -1470 hicredit 30 \ sendslope -980000 idleslope 20000 offload 1 Note: only idleslope and hicredit can be programmed in the switch registers, other parameters won't affect settings. Signed-off-by: Cedric Jehasse --- drivers/net/dsa/mv88e6xxx/chip.c | 123 ++++++++++++++++++++++++++++= ++++ drivers/net/dsa/mv88e6xxx/chip.h | 21 ++++++ drivers/net/dsa/mv88e6xxx/global2_avb.c | 21 ++++++ drivers/net/dsa/mv88e6xxx/port.c | 38 ++++++++++ drivers/net/dsa/mv88e6xxx/port.h | 16 +++++ 5 files changed, 219 insertions(+) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/c= hip.c index 277efe24edf4..63e2f13a4900 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -32,6 +32,7 @@ #include #include #include +#include =20 #include "chip.h" #include "devlink.h" @@ -5015,6 +5016,7 @@ static const struct mv88e6xxx_ops mv88e6240_ops =3D { .port_set_ether_type =3D mv88e6351_port_set_ether_type, .port_set_jumbo_size =3D mv88e6165_port_set_jumbo_size, .port_egress_rate_limiting =3D mv88e6097_port_egress_rate_limiting, + .port_set_scheduling_mode =3D mv88e6352_port_set_scheduling_mode, .port_pause_limit =3D mv88e6097_port_pause_limit, .port_disable_learn_limit =3D mv88e6xxx_port_disable_learn_limit, .port_disable_pri_override =3D mv88e6xxx_port_disable_pri_override, @@ -5446,6 +5448,7 @@ static const struct mv88e6xxx_ops mv88e6352_ops =3D { .port_set_ether_type =3D mv88e6351_port_set_ether_type, .port_set_jumbo_size =3D mv88e6165_port_set_jumbo_size, .port_egress_rate_limiting =3D mv88e6097_port_egress_rate_limiting, + .port_set_scheduling_mode =3D mv88e6352_port_set_scheduling_mode, .port_pause_limit =3D mv88e6097_port_pause_limit, .port_disable_learn_limit =3D mv88e6xxx_port_disable_learn_limit, .port_disable_pri_override =3D mv88e6xxx_port_disable_pri_override, @@ -5515,6 +5518,7 @@ static const struct mv88e6xxx_ops mv88e6390_ops =3D { .port_get_cmode =3D mv88e6352_port_get_cmode, .port_set_cmode =3D mv88e6390_port_set_cmode, .port_setup_message_port =3D mv88e6xxx_setup_message_port, + .port_set_scheduling_mode =3D mv88e6390_port_set_scheduling_mode, .stats_snapshot =3D mv88e6390_g1_stats_snapshot, .stats_set_histogram =3D mv88e6390_g1_stats_set_histogram, .stats_get_sset_count =3D mv88e6320_stats_get_sset_count, @@ -5580,6 +5584,7 @@ static const struct mv88e6xxx_ops mv88e6390x_ops =3D { .port_get_cmode =3D mv88e6352_port_get_cmode, .port_set_cmode =3D mv88e6390x_port_set_cmode, .port_setup_message_port =3D mv88e6xxx_setup_message_port, + .port_set_scheduling_mode =3D mv88e6390_port_set_scheduling_mode, .stats_snapshot =3D mv88e6390_g1_stats_snapshot, .stats_set_histogram =3D mv88e6390_g1_stats_set_histogram, .stats_get_sset_count =3D mv88e6320_stats_get_sset_count, @@ -5637,6 +5642,7 @@ static const struct mv88e6xxx_ops mv88e6393x_ops =3D { .port_set_ether_type =3D mv88e6393x_port_set_ether_type, .port_set_jumbo_size =3D mv88e6165_port_set_jumbo_size, .port_egress_rate_limiting =3D mv88e6097_port_egress_rate_limiting, + .port_set_scheduling_mode =3D mv88e6390_port_set_scheduling_mode, .port_pause_limit =3D mv88e6390_port_pause_limit, .port_disable_learn_limit =3D mv88e6xxx_port_disable_learn_limit, .port_disable_pri_override =3D mv88e6xxx_port_disable_pri_override, @@ -5679,6 +5685,22 @@ static const struct mv88e6xxx_ops mv88e6393x_ops =3D= { .tcam_ops =3D &mv88e6393_tcam_ops, }; =20 +static const struct mv88e6xxx_qav_info mv88e6352_qav_info =3D { + .max_rate =3D 1000000, + .rate_unit =3D 32, + .rate_mask =3D GENMASK(14, 0), + .hi_limit_mask =3D GENMASK(14, 0), + .queue_mask =3D GENMASK(3, 0), +}; + +static const struct mv88e6xxx_qav_info mv88e6390_qav_info =3D { + .max_rate =3D 4000000, + .rate_unit =3D 64, + .rate_mask =3D GENMASK(15, 0), + .hi_limit_mask =3D GENMASK(13, 0), + .queue_mask =3D GENMASK(7, 0), +}; + static const struct mv88e6xxx_info mv88e6xxx_table[] =3D { [MV88E6020] =3D { .prod_num =3D MV88E6XXX_PORT_SWITCH_ID_PROD_6020, @@ -6227,6 +6249,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .multi_chip =3D true, .edsa_support =3D MV88E6XXX_EDSA_SUPPORTED, .ptp_support =3D true, + .qav =3D &mv88e6352_qav_info, .ops =3D &mv88e6240_ops, }, =20 @@ -6440,6 +6463,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .multi_chip =3D true, .edsa_support =3D MV88E6XXX_EDSA_SUPPORTED, .ptp_support =3D true, + .qav =3D &mv88e6352_qav_info, .ops =3D &mv88e6352_ops, }, [MV88E6361] =3D { @@ -6496,6 +6520,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .multi_chip =3D true, .edsa_support =3D MV88E6XXX_EDSA_UNDOCUMENTED, .ptp_support =3D true, + .qav =3D &mv88e6390_qav_info, .ops =3D &mv88e6390_ops, }, [MV88E6390X] =3D { @@ -6523,6 +6548,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .multi_chip =3D true, .edsa_support =3D MV88E6XXX_EDSA_UNDOCUMENTED, .ptp_support =3D true, + .qav =3D &mv88e6390_qav_info, .ops =3D &mv88e6390x_ops, }, =20 @@ -6551,6 +6577,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .pvt =3D true, .multi_chip =3D true, .ptp_support =3D true, + .qav =3D &mv88e6390_qav_info, .ops =3D &mv88e6393x_ops, }, }; @@ -7172,6 +7199,101 @@ static int mv88e6xxx_crosschip_lag_leave(struct dsa= _switch *ds, int sw_index, return err_sync ? : err_pvt; } =20 +static int mv88e6xxx_setup_tc_cbs(struct dsa_switch *ds, int port, + struct tc_cbs_qopt_offload *cbs) +{ + struct mv88e6xxx_chip *chip =3D ds->priv; + const struct mv88e6xxx_ops *ops =3D chip->info->ops; + const struct mv88e6xxx_avb_ops *avb_ops; + const struct mv88e6xxx_qav_info *qav; + int rate_reg; + int hilimit_reg; + u8 queue_bit; + u16 rate =3D 0; + u16 hi_limit; + int err; + + avb_ops =3D ops->avb_ops; + qav =3D chip->info->qav; + if (!qav || !avb_ops || !avb_ops->port_qav_write || + !ops->port_set_scheduling_mode) + return -EOPNOTSUPP; + + if (!dsa_is_user_port(ds, port)) + return -EOPNOTSUPP; + + if (cbs->queue < 0 || cbs->queue >=3D chip->info->num_tx_queues) + return -EINVAL; + + if (!(qav->queue_mask & BIT(cbs->queue))) + return -EOPNOTSUPP; + + queue_bit =3D BIT(cbs->queue); + rate_reg =3D cbs->queue * 2; + hilimit_reg =3D rate_reg + 1; + + if (cbs->enable) { + if (cbs->idleslope <=3D 0 || + cbs->idleslope > qav->max_rate || + cbs->sendslope >=3D 0 || cbs->hicredit <=3D 0 || + cbs->hicredit > qav->hi_limit_mask) + return -ERANGE; + + rate =3D DIV_ROUND_UP(cbs->idleslope, qav->rate_unit); + if (rate > qav->rate_mask) + return -ERANGE; + } + + mv88e6xxx_reg_lock(chip); + + if (!cbs->enable) { + err =3D avb_ops->port_qav_write(chip, port, rate_reg, 0); + if (err) + goto unlock; + + if (!(chip->ports[port].cbs_active_queues & ~queue_bit)) { + err =3D ops->port_set_scheduling_mode(chip, port, 0); + if (err) + goto unlock; + } + chip->ports[port].cbs_active_queues &=3D ~queue_bit; + goto unlock; + } + + hi_limit =3D cbs->hicredit & qav->hi_limit_mask; + err =3D avb_ops->port_qav_write(chip, port, hilimit_reg, hi_limit); + if (err) + goto unlock; + + err =3D avb_ops->port_qav_write(chip, port, rate_reg, rate); + if (err) + goto unlock; + + err =3D ops->port_set_scheduling_mode(chip, port, + chip->info->num_tx_queues - 1); + if (err) { + avb_ops->port_qav_write(chip, port, rate_reg, 0); + goto unlock; + } + chip->ports[port].cbs_active_queues |=3D queue_bit; + +unlock: + mv88e6xxx_reg_unlock(chip); + + return err; +} + +static int mv88e6xxx_port_setup_tc(struct dsa_switch *ds, int port, + enum tc_setup_type type, void *type_data) +{ + switch (type) { + case TC_SETUP_QDISC_CBS: + return mv88e6xxx_setup_tc_cbs(ds, port, type_data); + default: + return -EOPNOTSUPP; + } +} + static const struct phylink_mac_ops mv88e6xxx_phylink_mac_ops =3D { .mac_select_pcs =3D mv88e6xxx_mac_select_pcs, .mac_prepare =3D mv88e6xxx_mac_prepare, @@ -7231,6 +7353,7 @@ static const struct dsa_switch_ops mv88e6xxx_switch_o= ps =3D { .port_hwtstamp_get =3D mv88e6xxx_port_hwtstamp_get, .port_txtstamp =3D mv88e6xxx_port_txtstamp, .port_rxtstamp =3D mv88e6xxx_port_rxtstamp, + .port_setup_tc =3D mv88e6xxx_port_setup_tc, .cls_flower_add =3D mv88e6xxx_cls_flower_add, .cls_flower_del =3D mv88e6xxx_cls_flower_del, .get_ts_info =3D mv88e6xxx_get_ts_info, diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/c= hip.h index 19d8eda19b78..81c9fb2f0e92 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.h +++ b/drivers/net/dsa/mv88e6xxx/chip.h @@ -125,6 +125,7 @@ enum mv88e6xxx_edsa_support { }; =20 struct mv88e6xxx_ops; +struct mv88e6xxx_qav_info; =20 struct mv88e6xxx_info { enum mv88e6xxx_family family; @@ -177,6 +178,9 @@ struct mv88e6xxx_info { /* Supports PTP */ bool ptp_support; =20 + /* 802.1Qav credit based shaping */ + const struct mv88e6xxx_qav_info *qav; + /* Internal PHY start index. 0 means that internal PHYs range starts at * port 0, 1 means internal PHYs range starts at port 1, etc */ @@ -304,6 +308,9 @@ struct mv88e6xxx_port { =20 /* MacAuth Bypass control flag */ bool mab; + + /* Queues with CBS currently enabled. */ + u8 cbs_active_queues; }; =20 enum mv88e6xxx_region_id { @@ -607,6 +614,8 @@ struct mv88e6xxx_ops { size_t size); =20 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); + int (*port_set_scheduling_mode)(struct mv88e6xxx_chip *chip, int port, + u8 mode); int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, u8 out); int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); @@ -764,6 +773,10 @@ struct mv88e6xxx_avb_ops { int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, int len); int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); + + /* Access port-scoped 802.1Qav registers */ + int (*port_qav_write)(struct mv88e6xxx_chip *chip, int port, int addr, + u16 data); }; =20 struct mv88e6xxx_ptp_ops { @@ -799,6 +812,14 @@ struct mv88e6xxx_tcam_ops { int (*flush_tcam)(struct mv88e6xxx_chip *chip); }; =20 +struct mv88e6xxx_qav_info { + u32 max_rate; /* in kbps */ + u16 rate_unit; /* in kbps */ + u16 rate_mask; /* QPri Rate valid bits mask */ + u16 hi_limit_mask; /* Qpri Hi Limit bits mask*/ + u8 queue_mask; /* supported queues bitmask */ +}; + static inline bool mv88e6xxx_has_stu(struct mv88e6xxx_chip *chip) { return chip->info->max_sid > 0 && diff --git a/drivers/net/dsa/mv88e6xxx/global2_avb.c b/drivers/net/dsa/mv88= e6xxx/global2_avb.c index 657783e043ff..6b54e275d21a 100644 --- a/drivers/net/dsa/mv88e6xxx/global2_avb.c +++ b/drivers/net/dsa/mv88e6xxx/global2_avb.c @@ -110,6 +110,15 @@ static int mv88e6352_g2_avb_port_ptp_write(struct mv88= e6xxx_chip *chip, return mv88e6xxx_g2_avb_write(chip, writeop, data); } =20 +static int mv88e6352_g2_avb_port_qav_write(struct mv88e6xxx_chip *chip, + int port, int addr, u16 data) +{ + u16 writeop =3D MV88E6352_G2_AVB_CMD_OP_WRITE | (port << 8) | + (MV88E6352_G2_AVB_CMD_BLOCK_QAV << 5) | addr; + + return mv88e6xxx_g2_avb_write(chip, writeop, data); +} + static int mv88e6352_g2_avb_ptp_read(struct mv88e6xxx_chip *chip, int addr, u16 *data, int len) { @@ -149,6 +158,7 @@ const struct mv88e6xxx_avb_ops mv88e6352_avb_ops =3D { .ptp_write =3D mv88e6352_g2_avb_ptp_write, .tai_read =3D mv88e6352_g2_avb_tai_read, .tai_write =3D mv88e6352_g2_avb_tai_write, + .port_qav_write =3D mv88e6352_g2_avb_port_qav_write, }; =20 static int mv88e6165_g2_avb_tai_read(struct mv88e6xxx_chip *chip, int addr, @@ -174,6 +184,7 @@ const struct mv88e6xxx_avb_ops mv88e6165_avb_ops =3D { .ptp_write =3D mv88e6352_g2_avb_ptp_write, .tai_read =3D mv88e6165_g2_avb_tai_read, .tai_write =3D mv88e6165_g2_avb_tai_write, + .port_qav_write =3D mv88e6352_g2_avb_port_qav_write, }; =20 static int mv88e6390_g2_avb_port_ptp_read(struct mv88e6xxx_chip *chip, @@ -197,6 +208,15 @@ static int mv88e6390_g2_avb_port_ptp_write(struct mv88= e6xxx_chip *chip, return mv88e6xxx_g2_avb_write(chip, writeop, data); } =20 +static int mv88e6390_g2_avb_port_qav_write(struct mv88e6xxx_chip *chip, + int port, int addr, u16 data) +{ + u16 writeop =3D MV88E6390_G2_AVB_CMD_OP_WRITE | (port << 8) | + (MV88E6352_G2_AVB_CMD_BLOCK_QAV << 5) | addr; + + return mv88e6xxx_g2_avb_write(chip, writeop, data); +} + static int mv88e6390_g2_avb_ptp_read(struct mv88e6xxx_chip *chip, int addr, u16 *data, int len) { @@ -236,4 +256,5 @@ const struct mv88e6xxx_avb_ops mv88e6390_avb_ops =3D { .ptp_write =3D mv88e6390_g2_avb_ptp_write, .tai_read =3D mv88e6390_g2_avb_tai_read, .tai_write =3D mv88e6390_g2_avb_tai_write, + .port_qav_write =3D mv88e6390_g2_avb_port_qav_write, }; diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/p= ort.c index c90117d2dd83..79422b8b01c8 100644 --- a/drivers/net/dsa/mv88e6xxx/port.c +++ b/drivers/net/dsa/mv88e6xxx/port.c @@ -1348,6 +1348,44 @@ int mv88e6097_port_egress_rate_limiting(struct mv88e= 6xxx_chip *chip, int port) 0x0001); } =20 +int mv88e6352_port_set_scheduling_mode(struct mv88e6xxx_chip *chip, int po= rt, + u8 mode) +{ + u16 reg; + int err; + + if (mode > 3) + return -EINVAL; + + err =3D mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, + ®); + if (err) + return err; + + reg &=3D ~MV88E6XXX_PORT_EGRESS_RATE_CTL2_SCHEDULE_MASK; + reg |=3D mode << MV88E6XXX_PORT_EGRESS_RATE_CTL2_SCHEDULE_SHIFT; + + return mv88e6xxx_port_write(chip, port, + MV88E6XXX_PORT_EGRESS_RATE_CTL2, reg); +} + +int mv88e6390_port_set_scheduling_mode(struct mv88e6xxx_chip *chip, int po= rt, + u8 mode) +{ + u16 reg; + + if (mode > MV88E6390_PORT_QUEUE_CTL_SCHEDULE_MASK) + return -EINVAL; + + reg =3D MV88E6390_PORT_QUEUE_CTL_UPDATE | + (MV88E6390_PORT_QUEUE_CTL_SCHEDULE << + MV88E6390_PORT_QUEUE_CTL_PTR_SHIFT) | + (mode & MV88E6390_PORT_QUEUE_CTL_SCHEDULE_MASK); + + return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_QUEUE_CTL, + reg); +} + /* Offset 0x0B: Port Association Vector */ =20 int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/p= ort.h index f6041f91215e..c4b0ec1990b3 100644 --- a/drivers/net/dsa/mv88e6xxx/port.h +++ b/drivers/net/dsa/mv88e6xxx/port.h @@ -241,6 +241,18 @@ =20 /* Offset 0x0A: Egress Rate Control 2 */ #define MV88E6XXX_PORT_EGRESS_RATE_CTL2 0x0a +#define MV88E6XXX_PORT_EGRESS_RATE_CTL2_SCHEDULE_MASK 0x3000 +#define MV88E6XXX_PORT_EGRESS_RATE_CTL2_SCHEDULE_SHIFT 12 + +/* Offset 0x1C: Port Queue Control */ +#define MV88E6390_PORT_QUEUE_CTL 0x1c +#define MV88E6390_PORT_QUEUE_CTL_UPDATE 0x8000 +#define MV88E6390_PORT_QUEUE_CTL_PTR_MASK 0x7f00 +#define MV88E6390_PORT_QUEUE_CTL_PTR_SHIFT 8 +#define MV88E6390_PORT_QUEUE_CTL_DATA_MASK 0x00ff +#define MV88E6390_PORT_QUEUE_CTL_SCHEDULE 0x00 +#define MV88E6390_PORT_QUEUE_CTL_SCHEDULE_MASK 0x07 + =20 /* Offset 0x0B: Port Association Vector */ #define MV88E6XXX_PORT_ASSOC_VECTOR 0x0b @@ -569,6 +581,10 @@ int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chi= p *chip, int port, size_t size); int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int p= ort); int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int p= ort); +int mv88e6352_port_set_scheduling_mode(struct mv88e6xxx_chip *chip, int po= rt, + u8 mode); +int mv88e6390_port_set_scheduling_mode(struct mv88e6xxx_chip *chip, int po= rt, + u8 mode); int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, u16 pav); int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 i= n, --=20 2.43.0