This patchset brings the support of the Other Logic Blocks (OLB)
found in the first Mobileye SoC based on the RISC-V architecture, the
EyeQ7H. Despite the change from MIPS to RISC-V, the Other Logic Blocks
provide similar clock and reset functions to the controllers of the
chip. This series introduces the device tree bindings of the SoC and
the necessary changes to the clock and reset eyeq drivers.
Since this series affects drivers used on Mobileye MIPS SoCs, mainly
clk-eyeq, I tested that it does not introduce regressions on EyeQ5,
EyeQ6H, and EyeQ6Lplus evaluation boards.
In detail, the first patch adds the dt-bindings yaml and headers for
the EyeQ7H OLB.
Patch 2 adds the compatible entries to the reset-eyeq driver, and the
necessary changes for the reset domains found in the EyeQ7H OLB.
Patches 3 and 4 rework the handling of parent clocks in
__clk_hw_register_fixed_factor() to make it identical to other clock types
like divider or gate. This allows simplifying the registration functions
built on top of the now exported __clk_hw_register_fixed_factor(). A
new clk_hw_register_fixed_factor_pdata() is added that will be used in
clk-eyeq later in the series.
Patch 5 renames the defines and functions related to the PLL with the
PLL type fracg, to make room for the other types of PLL found the in
EyeQ7H OLB.
Patch 6 introduces a new generic type of clock structure that can
represents all clocks found in OLB. Then patch 7 and 8 converts all
clocks defined in the driver to the new struct eqc_clock and remove all
the previous separate clocks structures.
Patch 9 adds the list of clocks as match data for the 14 OLB present
in the EyeQ7H SoC, and the functions needed to probe the two PLL types
found in the chip.
This series is based on v7.1-rc3 as all the prerequisites have been
merged. It also applies cleanly on the clk-next branch.
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
Changes in v7:
- Fixed DDR OLB reset controller type (the comment and sashiko were right)
and the comment for the reset offsets for west OLB in reset-eyeq.
- Made sure the parent clock is valid before accessing it
in clk_factor_determine_rate().
- Fixed error paths mistakenly returning IS_ERR(ret) instead of PTR_ERR(ret)
in clk-eyeq.
- Declared the DDR OLB dividers as read-only.
- Ensured that the mult and div computed in eqc_pll_parse_fracg() fit in 32 bits.
- Link to v6: https://patch.msgid.link/20260512-clk-eyeq7-v6-0-0540cce18fb2@bootlin.com
Changes in v6:
- Rebased on v7.1-rc3.
- Dropped the MAINTAINER update for now, this will go with the SoC series.
- Link to v5: https://lore.kernel.org/r/20260317-clk-eyeq7-v5-0-6f6daa2c2367@bootlin.com
Changes in v5:
- Rebased in v7.0-rc1 + version 4 of eyeq6plus series.
- Remove an superfluous whitespace and tidy up macros in clk-provider.h.
- Link to v4: https://lore.kernel.org/r/20260304-clk-eyeq7-v4-0-9d6bd9d24bec@bootlin.com
Changes in v4:
- Rebased on v7.0-rc1 + version 3 of eyeq6plus series.
- Link to v3: https://lore.kernel.org/r/20260114-clk-eyeq7-v3-0-8ebdba7b0133@bootlin.com
Changes in v3:
- Fix eyeq7h-olb DT bindings following Krzysztof review.
- Link to v2: https://lore.kernel.org/r/20251224-clk-eyeq7-v2-0-81744d1025d9@bootlin.com
Changes in v2:
- Move the dt-bindings to their own files and sort the compatibles.
- Reorder the changes in reset-eyeq and make the register access more
readable.
- Drop the validity check on even divider. Unnecessary since it is
always called from a clock .set_rate().
- Drop the parameters check on divider registration. Will be posted
separately.
- Switch to a new generic struct for describing the clocks.
- Add an entry to MAINTAINERS.
- Link to v1: https://lore.kernel.org/r/20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com
To: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
To: Benoît Monin <benoit.monin@bootlin.com>
To: Gregory CLEMENT <gregory.clement@bootlin.com>
To: Théo Lebrun <theo.lebrun@bootlin.com>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>
To: Stephen Boyd <sboyd@kernel.org>
To: Brian Masney <bmasney@redhat.com>
To: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-clk@vger.kernel.org
---
Benoît Monin (9):
dt-bindings: soc: mobileye: Add EyeQ7H OLB
reset: eyeq: Add EyeQ7H compatibles
clk: fixed-factor: Rework initialization with parent clocks
clk: fixed-factor: Export __clk_hw_register_fixed_factor()
clk: eyeq: Prefix the PLL registers with the PLL type
clk: eyeq: Introduce a generic clock type
clk: eyeq: Convert clocks declaration to eqc_clock
clk: eyeq: Drop PLL, dividers, and fixed factors structs
clk: eyeq: Add EyeQ7H compatibles
.../bindings/soc/mobileye/mobileye,eyeq7h-olb.yaml | 192 +++
drivers/clk/clk-eyeq.c | 1262 +++++++++++++-------
drivers/clk/clk-fixed-factor.c | 78 +-
drivers/reset/reset-eyeq.c | 268 ++++-
include/dt-bindings/clock/mobileye,eyeq7h-clk.h | 119 ++
include/linux/clk-provider.h | 56 +-
6 files changed, 1480 insertions(+), 495 deletions(-)
---
base-commit: bb1459368dd795c43380057523f571d5eb0ddded
change-id: 20250807-clk-eyeq7-f9c6ea43d138
Best regards,
--
Benoît Monin, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com