From nobody Sun May 24 19:34:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 601493672BE; Fri, 22 May 2026 17:59:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779472745; cv=none; b=oPib3BADDECHz5R5G5He5cBocV+/kqLaMI/a6/PLodpIGsalpmNJRxDlv8XZRaC18EeA3do9DwIdOSEal8VKyYZUbO03JoNmrj+m8UTXpoHhH5zX6PNMpmtpGAYIQb7qXHK2fz8GOl4knJgYWEa9cJ8JGQQ+ENUiIKWkMW+Z+zM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779472745; c=relaxed/simple; bh=9GYV0ftpEJl4lFndesuOAU5IJOWKdhaJW8q3YmPKl70=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pdWq6Y4IBzT+PNxKFVSSYCILaYVzDJA6Iow62TjpgDab13k/1oSiM/7i7GA+jMDLDmdr9s/nCWPReM6j2vASfFYhGU/jaXjY5AyFM9ewMilZoryIMRCxQxmfeCLG21oFTYnmoQMdpik1ux7tdiTt/CSX3Gc7PJO/Q3v+diC15Qg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=denzt7Bo; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="denzt7Bo" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1EC0B1F000E9; Fri, 22 May 2026 17:59:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779472744; bh=QMgm0LxQlLuFc2zsZd1wTo2E41aWk+l7bTvyq+/nFPA=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=denzt7BoSfQRu8XdwAMCOdNhqRqx4TWNzOl0plLWhiTNR0lhztyBd/kiKfq7SOBb5 6Ao5OLLN+mBV051JffpmVWN/WbgBNGXYcq5URvmpvBm63f0/Y2DBRUX6qnEm04wSU3 navtF/wmY0Fdp15CAp/5bsla5KQ6RIF2jSt1ea7tec2k1aXkEd86z85iIWmwPPz3l+ 30HHkASFGdoHYVbTE6CFRfWW0fxX1l6+tlXeSyQhpoDoEDCbEg5R2YUdoKG/0k1ofE a3OBpJONW4W5KTPRIgZ+PVGsJXN52WiMN6rdezah9aYkB1BpRlsf+10Dbavt9JlEgG HM/mxfBdI4Ttw== From: Mark Brown Date: Fri, 22 May 2026 18:58:37 +0100 Subject: [PATCH 1/3] arm64: Don't number registers in cpu-feature-registers.rst Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260522-arm64-cpu-ftr-regs-v1-1-19775b40faf0@kernel.org> References: <20260522-arm64-cpu-ftr-regs-v1-0-19775b40faf0@kernel.org> In-Reply-To: <20260522-arm64-cpu-ftr-regs-v1-0-19775b40faf0@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Shuah Khan Cc: Peter Maydell , Joey Gouly , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=5720; i=broonie@kernel.org; h=from:subject:message-id; bh=9GYV0ftpEJl4lFndesuOAU5IJOWKdhaJW8q3YmPKl70=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqEJlhSFvKG+iAsC8RAugbV6Xj1bdCp792yxuO/ 6ooN37/DKOJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCahCZYQAKCRAk1otyXVSH 0H5HB/9uJv9FcfkBjloICAd1ZVk7Qlw/i7sJEL2GfiZ6c+3FG+K4nypM6qg5H6lAVugikDDw86e 5cK8h2VBA9Tb8pNO1zt7nvcZYZdQQP3E7ve+VtHoig66EBSQf3jNHRGKKVzgyLhyqW0ZDlIWuOI j4qENg+AMIPPdzbDS0hHUaOf1ovO949zuQUHPPLP4mG9TgzjCoASrBCM4qsPS7gMGXQC30HI/2z tqh8C6r3NK/C9feAwqlWL8E8KeDgNAMjvyetF9rRwaX4hhBiuFWJ2C0x4K7bMLbl1xHUxQ+gIHq cvZkhU3mABAeOF+sCRiDz2d+fluUflAYkzKIA5Uv8Sk6NK6H X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB cpu-feature-regsters.rst documents the set of userspace visible ID registers. At present the section for each register is numbered, this has lead to the registers being documented in a haphazard order as new ones have been added to the end of the list to avoid renumbering. Remove the numbers so we can avoid this problem in future. Signed-off-by: Mark Brown --- Documentation/arch/arm64/cpu-feature-registers.rst | 26 +++++++++++-------= ---- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documenta= tion/arch/arm64/cpu-feature-registers.rst index add66afc7b03..c6e5bc053c09 100644 --- a/Documentation/arch/arm64/cpu-feature-registers.rst +++ b/Documentation/arch/arm64/cpu-feature-registers.rst @@ -113,7 +113,7 @@ infrastructure: 4. List of registers with visible features ------------------------------------------- =20 - 1) ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0 + ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0 =20 +------------------------------+---------+---------+ | Name | bits | visible | @@ -146,7 +146,7 @@ infrastructure: +------------------------------+---------+---------+ =20 =20 - 2) ID_AA64PFR0_EL1 - Processor Feature Register 0 + ID_AA64PFR0_EL1 - Processor Feature Register 0 =20 +------------------------------+---------+---------+ | Name | bits | visible | @@ -173,7 +173,7 @@ infrastructure: +------------------------------+---------+---------+ =20 =20 - 3) ID_AA64PFR1_EL1 - Processor Feature Register 1 + ID_AA64PFR1_EL1 - Processor Feature Register 1 =20 +------------------------------+---------+---------+ | Name | bits | visible | @@ -188,7 +188,7 @@ infrastructure: +------------------------------+---------+---------+ =20 =20 - 4) MIDR_EL1 - Main ID Register + MIDR_EL1 - Main ID Register =20 +------------------------------+---------+---------+ | Name | bits | visible | @@ -208,7 +208,7 @@ infrastructure: as available on the CPU where it is fetched and is not a system wide safe value. =20 - 5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 + ID_AA64ISAR1_EL1 - Instruction set attribute register 1 =20 +------------------------------+---------+---------+ | Name | bits | visible | @@ -240,7 +240,7 @@ infrastructure: | DPB | [3-0] | y | +------------------------------+---------+---------+ =20 - 6) ID_AA64MMFR0_EL1 - Memory model feature register 0 + ID_AA64MMFR0_EL1 - Memory model feature register 0 =20 +------------------------------+---------+---------+ | Name | bits | visible | @@ -248,7 +248,7 @@ infrastructure: | ECV | [63-60] | y | +------------------------------+---------+---------+ =20 - 7) ID_AA64MMFR2_EL1 - Memory model feature register 2 + ID_AA64MMFR2_EL1 - Memory model feature register 2 =20 +------------------------------+---------+---------+ | Name | bits | visible | @@ -256,7 +256,7 @@ infrastructure: | AT | [35-32] | y | +------------------------------+---------+---------+ =20 - 8) ID_AA64ZFR0_EL1 - SVE feature ID register 0 + ID_AA64ZFR0_EL1 - SVE feature ID register 0 =20 +------------------------------+---------+---------+ | Name | bits | visible | @@ -282,7 +282,7 @@ infrastructure: | SVEVer | [3-0] | y | +------------------------------+---------+---------+ =20 - 8) ID_AA64MMFR1_EL1 - Memory model feature register 1 + ID_AA64MMFR1_EL1 - Memory model feature register 1 =20 +------------------------------+---------+---------+ | Name | bits | visible | @@ -290,7 +290,7 @@ infrastructure: | AFP | [47-44] | y | +------------------------------+---------+---------+ =20 - 9) ID_AA64ISAR2_EL1 - Instruction set attribute register 2 + ID_AA64ISAR2_EL1 - Instruction set attribute register 2 =20 +------------------------------+---------+---------+ | Name | bits | visible | @@ -312,7 +312,7 @@ infrastructure: | WFXT | [3-0] | y | +------------------------------+---------+---------+ =20 - 10) MVFR0_EL1 - AArch32 Media and VFP Feature Register 0 + MVFR0_EL1 - AArch32 Media and VFP Feature Register 0 =20 +------------------------------+---------+---------+ | Name | bits | visible | @@ -320,7 +320,7 @@ infrastructure: | FPDP | [11-8] | y | +------------------------------+---------+---------+ =20 - 11) MVFR1_EL1 - AArch32 Media and VFP Feature Register 1 + MVFR1_EL1 - AArch32 Media and VFP Feature Register 1 =20 +------------------------------+---------+---------+ | Name | bits | visible | @@ -334,7 +334,7 @@ infrastructure: | SIMDLS | [11-8] | y | +------------------------------+---------+---------+ =20 - 12) ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5 + ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5 =20 +------------------------------+---------+---------+ | Name | bits | visible | --=20 2.47.3 From nobody Sun May 24 19:34:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5B5E368D73; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KB1dBY/v" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 624031F00A3D; Fri, 22 May 2026 17:59:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779472746; bh=5M741NhNb3pK/+PV++HDDdDV2VM5+HppfDnOzOibUys=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=KB1dBY/vNFe2qtuVGTGxA2lFH58eex0F4XUK9J2EUthFwgBI835a79MjPx1CkJJBx rpFB9IVCIKf1e8WjzS7aK2t1SCBCx1MeZAhnoY9t9jmX60i6B7Dq02Y/VcqWam8irJ sPJq50Ti37/d6tiDjaWwsrkTFt6xwKrkCaqc7ENHwqQKrBptTXuKthC14Bs+x25T0y VSBZfzoYpqzf9hmB3VhExQ1SBpY+TiCY4/vljjMFq/8itJkq6heXJoYZ3VGawdB8l7 X6syOHOGSWPFta2Df/79k5P8elCYgVVNyUpQ7kbjewkiaEtWFOMG58cCgvPjZmL3YP HJspGKSGg+LOQ== From: Mark Brown Date: Fri, 22 May 2026 18:58:38 +0100 Subject: [PATCH 2/3] arm64: Document missing bitfields in cpu-feature-registers.rst Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260522-arm64-cpu-ftr-regs-v1-2-19775b40faf0@kernel.org> References: <20260522-arm64-cpu-ftr-regs-v1-0-19775b40faf0@kernel.org> In-Reply-To: <20260522-arm64-cpu-ftr-regs-v1-0-19775b40faf0@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Shuah Khan Cc: Peter Maydell , Joey Gouly , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=12367; i=broonie@kernel.org; h=from:subject:message-id; bh=BeJCPrI87ngYnWhvrn7H07d98eQ7tMnKHmjO+Ju1V94=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqEJlhvMVvV3+VDHFtpPiprlLe/+9DJjp1kjFdU kHdNABUlcOJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCahCZYQAKCRAk1otyXVSH 0Lm3B/9QNQ+fTXkMmHyyu6DWfHOd8PXwpZgOPTzE7tXfAsePSwDZVDPI/DQ27Ft3/FSDn4NiDOm tnoc4pBezKBDLCncwC7yMv5J42M4rnkCJnFacYD2OYflDXEXadSgOqW9Rz1KEEe7hNFRlOyWgFt KAx2wIrvH4T6Y2mXOM6NJnis0z57PQl8pC887rwoOikCn8VznllP6qROY9YQrM8qWA60Gdh+x5R i+I5PCC6piiEftEMJnB+oamHX0RlYrRX0TlbHD30Gt84hU7w7jVcyJdMGdHrByficuRlo0O3CnK ICWztfFqsGPOKJNvat5la0yXqHRbBEkIFrCrYfaqyrkEvAiF X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB We have been rather lax in updating the list of visible bitfields in the ID registers in cpu-feature-registers.rst, it is currently missing several of the registers and quite a few bitfields in existing registers. Bring it into sync with current -next. Signed-off-by: Mark Brown --- Documentation/arch/arm64/cpu-feature-registers.rst | 146 +++++++++++++++++= ++++ 1 file changed, 146 insertions(+) diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documenta= tion/arch/arm64/cpu-feature-registers.rst index c6e5bc053c09..02815db0c780 100644 --- a/Documentation/arch/arm64/cpu-feature-registers.rst +++ b/Documentation/arch/arm64/cpu-feature-registers.rst @@ -113,6 +113,30 @@ infrastructure: 4. List of registers with visible features ------------------------------------------- =20 + ID_AA6FPFR0_EL1 - Floating Point feature ID register 0 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | F8CVT | [31] | y | + +------------------------------+---------+---------+ + | F8FMA | [30] | y | + +------------------------------+---------+---------+ + | F8DP4 | [29] | y | + +------------------------------+---------+---------+ + | F8DP2 | [28] | y | + +------------------------------+---------+---------+ + | F8MM8 | [27] | y | + +------------------------------+---------+---------+ + | F8MM4 | [26] | y | + +------------------------------+---------+---------+ + | F16MM2 | [15] | y | + +------------------------------+---------+---------+ + | F8E4M3 | [1] | y | + +------------------------------+---------+---------+ + | F8E5M2 | [0] | y | + +------------------------------+---------+---------+ + ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0 =20 +------------------------------+---------+---------+ @@ -178,6 +202,8 @@ infrastructure: +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ + | GCS | [47-44] | y | + +------------------------------+---------+---------+ | SME | [27-24] | y | +------------------------------+---------+---------+ | MTE | [11-8] | y | @@ -187,6 +213,17 @@ infrastructure: | BT | [3-0] | y | +------------------------------+---------+---------+ =20 + ID_AA64PFR2_EL1 - Processor Feature Register 2 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | FPMR | [35-32] | y | + +------------------------------+---------+---------+ + | MTEFAR | [11-8] | y | + +------------------------------+---------+---------+ + | MTESTOREONLY | [7-4] | y | + +------------------------------+---------+---------+ =20 MIDR_EL1 - Main ID Register =20 @@ -213,6 +250,8 @@ infrastructure: +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ + | LS64 | [63-60] | y | + +------------------------------+---------+---------+ | I8MM | [55-52] | y | +------------------------------+---------+---------+ | DGH | [51-48] | y | @@ -256,6 +295,68 @@ infrastructure: | AT | [35-32] | y | +------------------------------+---------+---------+ =20 + ID_AA64MMFR3_EL1 - Memory model feature register 3 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | S1POE | [19-16] | y | + +------------------------------+---------+---------+ + + ID_AA6SMFR0_EL1 - SME feature ID register 0 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | FA64 | [63] | y | + +------------------------------+---------+---------+ + | LUT6 | [61] | y | + +------------------------------+---------+---------+ + | LUTv2 | [60] | y | + +------------------------------+---------+---------+ + | SMEver | [59-56] | y | + +------------------------------+---------+---------+ + | I16I64 | [55-52] | y | + +------------------------------+---------+---------+ + | F64F64 | [48] | y | + +------------------------------+---------+---------+ + | I16I32 | [47-44] | y | + +------------------------------+---------+---------+ + | B16B16 | [43] | y | + +------------------------------+---------+---------+ + | F16F16 | [42] | y | + +------------------------------+---------+---------+ + | F8F16 | [41] | y | + +------------------------------+---------+---------+ + | F8F32 | [40] | y | + +------------------------------+---------+---------+ + | I8I32 | [39-36] | y | + +------------------------------+---------+---------+ + | F16F32 | [35] | y | + +------------------------------+---------+---------+ + | B16F32 | [34] | y | + +------------------------------+---------+---------+ + | BI32I32 | [33] | y | + +------------------------------+---------+---------+ + | F32F32 | [32] | y | + +------------------------------+---------+---------+ + | SF8FMA | [30] | y | + +------------------------------+---------+---------+ + | SF8DP4 | [29] | y | + +------------------------------+---------+---------+ + | SF8DP2 | [28] | y | + +------------------------------+---------+---------+ + | SBitPerm | [25] | y | + +------------------------------+---------+---------+ + | AES | [24] | y | + +------------------------------+---------+---------+ + | SFEXPA | [23] | y | + +------------------------------+---------+---------+ + | STMOP | [16] | y | + +------------------------------+---------+---------+ + | SMOP4 | [0] | y | + +------------------------------+---------+---------+ + ID_AA64ZFR0_EL1 - SVE feature ID register 0 =20 +------------------------------+---------+---------+ @@ -265,6 +366,8 @@ infrastructure: +------------------------------+---------+---------+ | F32MM | [55-52] | y | +------------------------------+---------+---------+ + | F16MM | [51-48] | y | + +------------------------------+---------+---------+ | I8MM | [47-44] | y | +------------------------------+---------+---------+ | SM4 | [43-40] | y | @@ -277,6 +380,8 @@ infrastructure: +------------------------------+---------+---------+ | BitPerm | [19-16] | y | +------------------------------+---------+---------+ + | EltPerm | [15-12] | y | + +------------------------------+---------+---------+ | AES | [7-4] | y | +------------------------------+---------+---------+ | SVEVer | [3-0] | y | @@ -295,6 +400,8 @@ infrastructure: +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ + | LUT | [59-56] | y | + +------------------------------+---------+---------+ | CSSC | [55-52] | y | +------------------------------+---------+---------+ | RPRFM | [51-48] | y | @@ -312,6 +419,18 @@ infrastructure: | WFXT | [3-0] | y | +------------------------------+---------+---------+ =20 + ID_AA64ISAR3_EL1 - Instruction set attribute register 3 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | FPRCVT | [31-28] | y | + +------------------------------+---------+---------+ + | LSFE | [19-16] | y | + +------------------------------+---------+---------+ + | FAMINMAX | [7-4] | y | + +------------------------------+---------+---------+ + MVFR0_EL1 - AArch32 Media and VFP Feature Register 0 =20 +------------------------------+---------+---------+ @@ -327,6 +446,10 @@ infrastructure: +------------------------------+---------+---------+ | SIMDFMAC | [31-28] | y | +------------------------------+---------+---------+ + | FPHP | [27-24] | y | + +------------------------------+---------+---------+ + | SIMDHP | [23-20] | y | + +------------------------------+---------+---------+ | SIMDSP | [19-16] | y | +------------------------------+---------+---------+ | SIMDInt | [15-12] | y | @@ -348,6 +471,29 @@ infrastructure: | AES | [7-4] | y | +------------------------------+---------+---------+ =20 + ID_ISAR6_EL1 - AArch32 Instruction Set Attribute Register 6 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | I8MM | [27-24] | y | + +------------------------------+---------+---------+ + | BF16 | [23-20] | y | + +------------------------------+---------+---------+ + | SB | [15-12] | y | + +------------------------------+---------+---------+ + | FHM | [11-8] | y | + +------------------------------+---------+---------+ + | DP | [7-4] | y | + +------------------------------+---------+---------+ + + ID_PFR2_EL1 - AArch32 Processor Feature Register 2 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | SSBS | [7-4] | y | + +------------------------------+---------+---------+ =20 Appendix I: Example ------------------- --=20 2.47.3 From nobody Sun May 24 19:34:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F206A36DA00; Fri, 22 May 2026 17:59:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779472750; cv=none; b=l86tsGQo9Ktq7TQ7LZdsb/izkBttqM8LdP46m3gOcuKpI7DOVKqpIyntGnIXmDIwANJigFK1D7t6VIk0aM0VidFtZAxVXEL2FJ/Kz8qojiRrjTbrVlS65hEIc79E1jb6kjXj75/+bzLelUEpie668SXACDR64mCdpLptuaXlxC8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779472750; c=relaxed/simple; bh=cx+KF/6nrqSAu4vLW0c/WsDbTzGJ4mLnp/FbDrX0pEg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Vzv0FYV6qoHeYPNwjGkI8QA3QTF/4aa7waiN706K2iJyjdbmpXbpslu/Aw1p0AdjiO2erZryNRnYoB6edFCDIS8e5ataGuTci+eMuwxBy9x6J/VQaiQmFTH7nECMBDQFRNcY2kTSaWvkbgVjw3+tHeT175fefPPHgXHgzhzxxDA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Q3h9Sapv; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Q3h9Sapv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A7FDF1F00A3E; Fri, 22 May 2026 17:59:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779472748; bh=AAcnzs7CI4odaI29OdW5gRVKD8KnKU5khRHBWADis3c=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=Q3h9SapvwuYmx6+PRTRCX85IWJxf72YhczM7KUol+ItHt/ajLIy8Iqz7b9Yk/gx5i iknnxjJf88BACO+fWQKNfHDTH/xBj1PgFP9046zrz5Y03jsy3puHzX5MXZvVr5ZVwo D0HC9CS+VzMvj1SDNik72sRx1+DiqBZXQOfHzXRZLduwm6LFIoMkWbBZwoJldOym6Y lmEoNjbWQFFz/b1zfBbsyEfPEIE4INi+Tug+iYp+HfD/aBlssylX7t1w0T41jlxiKB IafDsO9RkVCjoQZD9uhGBP9zxrzmFH4t+HnoFSKClms87FBPagusuWICG8Kdurcdtm XuifOxzzNJ42w== From: Mark Brown Date: Fri, 22 May 2026 18:58:39 +0100 Subject: [PATCH 3/3] arm64: Sort registers in cpu-feature-registers.rst Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260522-arm64-cpu-ftr-regs-v1-3-19775b40faf0@kernel.org> References: <20260522-arm64-cpu-ftr-regs-v1-0-19775b40faf0@kernel.org> In-Reply-To: <20260522-arm64-cpu-ftr-regs-v1-0-19775b40faf0@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Shuah Khan Cc: Peter Maydell , Joey Gouly , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=18454; i=broonie@kernel.org; h=from:subject:message-id; bh=cx+KF/6nrqSAu4vLW0c/WsDbTzGJ4mLnp/FbDrX0pEg=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqEJliUL54VF4fiT/FStBUaptC+buEsFiUXBnMg Wpo552EeQeJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCahCZYgAKCRAk1otyXVSH 0IouB/wLNnbin9WAFQnGwNUvyb6ps58Yldlu10vRqOq5Bos0/QIIRuNeRSSj6GVKUE9A3Zk+urV agy8PrbCTv0gEEkzrrHPDJGhHjBlYUZPFtTu2hzduapoRnibc1NKpxJVS+q3mirupgy6Wb0Of/S 4VoNMUYTOvM1VSq9/vfCabcPR5fA8ClkbTLoV4z9F1TsoIiM5p28LAWnVqvnmmF6clZLqbYmvYS Q9cpbD1fuoeBHPCuR/cHYaWU6SijxnNKKOJn8Mj0nyqcfsE7kjPWmOM/FUI1VC9aqY9xqg8vroC s00c/JL9BcnMTiJVFSBixKr0vmvb0d+TGZdpLuTYwUN8nu/7 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB In order to make it a bit easier to work with sort the list of registers in cpu-feature-registers.rst lexically. There should be no content changes resulting from this patch. Signed-off-by: Mark Brown --- Documentation/arch/arm64/cpu-feature-registers.rst | 223 +++++++++++------= ---- 1 file changed, 112 insertions(+), 111 deletions(-) diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documenta= tion/arch/arm64/cpu-feature-registers.rst index 02815db0c780..0ea294c56984 100644 --- a/Documentation/arch/arm64/cpu-feature-registers.rst +++ b/Documentation/arch/arm64/cpu-feature-registers.rst @@ -170,137 +170,161 @@ infrastructure: +------------------------------+---------+---------+ =20 =20 - ID_AA64PFR0_EL1 - Processor Feature Register 0 + ID_AA64ISAR1_EL1 - Instruction set attribute register 1 =20 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ - | DIT | [51-48] | y | + | LS64 | [63-60] | y | +------------------------------+---------+---------+ - | MPAM | [43-40] | n | + | I8MM | [55-52] | y | +------------------------------+---------+---------+ - | SVE | [35-32] | y | + | DGH | [51-48] | y | +------------------------------+---------+---------+ - | GIC | [27-24] | n | + | BF16 | [47-44] | y | +------------------------------+---------+---------+ - | AdvSIMD | [23-20] | y | + | SB | [39-36] | y | +------------------------------+---------+---------+ - | FP | [19-16] | y | + | FRINTTS | [35-32] | y | +------------------------------+---------+---------+ - | EL3 | [15-12] | n | + | GPI | [31-28] | y | +------------------------------+---------+---------+ - | EL2 | [11-8] | n | + | GPA | [27-24] | y | +------------------------------+---------+---------+ - | EL1 | [7-4] | n | + | LRCPC | [23-20] | y | +------------------------------+---------+---------+ - | EL0 | [3-0] | n | + | FCMA | [19-16] | y | + +------------------------------+---------+---------+ + | JSCVT | [15-12] | y | + +------------------------------+---------+---------+ + | API | [11-8] | y | + +------------------------------+---------+---------+ + | APA | [7-4] | y | + +------------------------------+---------+---------+ + | DPB | [3-0] | y | +------------------------------+---------+---------+ =20 - - ID_AA64PFR1_EL1 - Processor Feature Register 1 + ID_AA64ISAR2_EL1 - Instruction set attribute register 2 =20 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ - | GCS | [47-44] | y | + | LUT | [59-56] | y | +------------------------------+---------+---------+ - | SME | [27-24] | y | + | CSSC | [55-52] | y | +------------------------------+---------+---------+ - | MTE | [11-8] | y | + | RPRFM | [51-48] | y | +------------------------------+---------+---------+ - | SSBS | [7-4] | y | + | BC | [23-20] | y | +------------------------------+---------+---------+ - | BT | [3-0] | y | + | MOPS | [19-16] | y | + +------------------------------+---------+---------+ + | APA3 | [15-12] | y | + +------------------------------+---------+---------+ + | GPA3 | [11-8] | y | + +------------------------------+---------+---------+ + | RPRES | [7-4] | y | + +------------------------------+---------+---------+ + | WFXT | [3-0] | y | +------------------------------+---------+---------+ =20 - ID_AA64PFR2_EL1 - Processor Feature Register 2 + ID_AA64ISAR3_EL1 - Instruction set attribute register 3 =20 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ - | FPMR | [35-32] | y | + | FPRCVT | [31-28] | y | +------------------------------+---------+---------+ - | MTEFAR | [11-8] | y | + | LSFE | [19-16] | y | +------------------------------+---------+---------+ - | MTESTOREONLY | [7-4] | y | + | FAMINMAX | [7-4] | y | +------------------------------+---------+---------+ =20 - MIDR_EL1 - Main ID Register + ID_AA64MMFR0_EL1 - Memory model feature register 0 =20 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ - | Implementer | [31-24] | y | - +------------------------------+---------+---------+ - | Variant | [23-20] | y | + | ECV | [63-60] | y | +------------------------------+---------+---------+ - | Architecture | [19-16] | y | + + ID_AA64MMFR1_EL1 - Memory model feature register 1 + +------------------------------+---------+---------+ - | PartNum | [15-4] | y | + | Name | bits | visible | +------------------------------+---------+---------+ - | Revision | [3-0] | y | + | AFP | [47-44] | y | +------------------------------+---------+---------+ =20 - NOTE: The 'visible' fields of MIDR_EL1 will contain the value - as available on the CPU where it is fetched and is not a system - wide safe value. - - ID_AA64ISAR1_EL1 - Instruction set attribute register 1 + ID_AA64MMFR2_EL1 - Memory model feature register 2 =20 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ - | LS64 | [63-60] | y | + | AT | [35-32] | y | +------------------------------+---------+---------+ - | I8MM | [55-52] | y | + + ID_AA64MMFR3_EL1 - Memory model feature register 3 + +------------------------------+---------+---------+ - | DGH | [51-48] | y | + | Name | bits | visible | +------------------------------+---------+---------+ - | BF16 | [47-44] | y | + | S1POE | [19-16] | y | +------------------------------+---------+---------+ - | SB | [39-36] | y | + + ID_AA64PFR0_EL1 - Processor Feature Register 0 + +------------------------------+---------+---------+ - | FRINTTS | [35-32] | y | + | Name | bits | visible | +------------------------------+---------+---------+ - | GPI | [31-28] | y | + | DIT | [51-48] | y | +------------------------------+---------+---------+ - | GPA | [27-24] | y | + | MPAM | [43-40] | n | +------------------------------+---------+---------+ - | LRCPC | [23-20] | y | + | SVE | [35-32] | y | +------------------------------+---------+---------+ - | FCMA | [19-16] | y | + | GIC | [27-24] | n | +------------------------------+---------+---------+ - | JSCVT | [15-12] | y | + | AdvSIMD | [23-20] | y | +------------------------------+---------+---------+ - | API | [11-8] | y | + | FP | [19-16] | y | +------------------------------+---------+---------+ - | APA | [7-4] | y | + | EL3 | [15-12] | n | +------------------------------+---------+---------+ - | DPB | [3-0] | y | + | EL2 | [11-8] | n | + +------------------------------+---------+---------+ + | EL1 | [7-4] | n | + +------------------------------+---------+---------+ + | EL0 | [3-0] | n | +------------------------------+---------+---------+ =20 - ID_AA64MMFR0_EL1 - Memory model feature register 0 + + ID_AA64PFR1_EL1 - Processor Feature Register 1 =20 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ - | ECV | [63-60] | y | + | GCS | [47-44] | y | +------------------------------+---------+---------+ - - ID_AA64MMFR2_EL1 - Memory model feature register 2 - + | SME | [27-24] | y | +------------------------------+---------+---------+ - | Name | bits | visible | + | MTE | [11-8] | y | +------------------------------+---------+---------+ - | AT | [35-32] | y | + | SSBS | [7-4] | y | + +------------------------------+---------+---------+ + | BT | [3-0] | y | +------------------------------+---------+---------+ =20 - ID_AA64MMFR3_EL1 - Memory model feature register 3 + ID_AA64PFR2_EL1 - Processor Feature Register 2 =20 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ - | S1POE | [19-16] | y | + | FPMR | [35-32] | y | + +------------------------------+---------+---------+ + | MTEFAR | [11-8] | y | + +------------------------------+---------+---------+ + | MTESTOREONLY | [7-4] | y | +------------------------------+---------+---------+ =20 ID_AA6SMFR0_EL1 - SME feature ID register 0 @@ -387,50 +411,64 @@ infrastructure: | SVEVer | [3-0] | y | +------------------------------+---------+---------+ =20 - ID_AA64MMFR1_EL1 - Memory model feature register 1 + ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5 =20 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ - | AFP | [47-44] | y | + | CRC32 | [19-16] | y | + +------------------------------+---------+---------+ + | SHA2 | [15-12] | y | + +------------------------------+---------+---------+ + | SHA1 | [11-8] | y | + +------------------------------+---------+---------+ + | AES | [7-4] | y | +------------------------------+---------+---------+ =20 - ID_AA64ISAR2_EL1 - Instruction set attribute register 2 + ID_ISAR6_EL1 - AArch32 Instruction Set Attribute Register 6 =20 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ - | LUT | [59-56] | y | - +------------------------------+---------+---------+ - | CSSC | [55-52] | y | + | I8MM | [27-24] | y | +------------------------------+---------+---------+ - | RPRFM | [51-48] | y | + | BF16 | [23-20] | y | +------------------------------+---------+---------+ - | BC | [23-20] | y | + | SB | [15-12] | y | +------------------------------+---------+---------+ - | MOPS | [19-16] | y | + | FHM | [11-8] | y | +------------------------------+---------+---------+ - | APA3 | [15-12] | y | + | DP | [7-4] | y | +------------------------------+---------+---------+ - | GPA3 | [11-8] | y | + + ID_PFR2_EL1 - AArch32 Processor Feature Register 2 + +------------------------------+---------+---------+ - | RPRES | [7-4] | y | + | Name | bits | visible | +------------------------------+---------+---------+ - | WFXT | [3-0] | y | + | SSBS | [7-4] | y | +------------------------------+---------+---------+ =20 - ID_AA64ISAR3_EL1 - Instruction set attribute register 3 + MIDR_EL1 - Main ID Register =20 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ - | FPRCVT | [31-28] | y | + | Implementer | [31-24] | y | +------------------------------+---------+---------+ - | LSFE | [19-16] | y | + | Variant | [23-20] | y | +------------------------------+---------+---------+ - | FAMINMAX | [7-4] | y | + | Architecture | [19-16] | y | + +------------------------------+---------+---------+ + | PartNum | [15-4] | y | + +------------------------------+---------+---------+ + | Revision | [3-0] | y | +------------------------------+---------+---------+ =20 + NOTE: The 'visible' fields of MIDR_EL1 will contain the value + as available on the CPU where it is fetched and is not a system + wide safe value. + MVFR0_EL1 - AArch32 Media and VFP Feature Register 0 =20 +------------------------------+---------+---------+ @@ -457,43 +495,6 @@ infrastructure: | SIMDLS | [11-8] | y | +------------------------------+---------+---------+ =20 - ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5 - - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | CRC32 | [19-16] | y | - +------------------------------+---------+---------+ - | SHA2 | [15-12] | y | - +------------------------------+---------+---------+ - | SHA1 | [11-8] | y | - +------------------------------+---------+---------+ - | AES | [7-4] | y | - +------------------------------+---------+---------+ - - ID_ISAR6_EL1 - AArch32 Instruction Set Attribute Register 6 - - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | I8MM | [27-24] | y | - +------------------------------+---------+---------+ - | BF16 | [23-20] | y | - +------------------------------+---------+---------+ - | SB | [15-12] | y | - +------------------------------+---------+---------+ - | FHM | [11-8] | y | - +------------------------------+---------+---------+ - | DP | [7-4] | y | - +------------------------------+---------+---------+ - - ID_PFR2_EL1 - AArch32 Processor Feature Register 2 - - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | SSBS | [7-4] | y | - +------------------------------+---------+---------+ =20 Appendix I: Example ------------------- --=20 2.47.3