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([120.60.66.36]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bea990105fsm19011775ad.55.2026.05.21.10.46.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 10:46:25 -0700 (PDT) From: Manivannan Sadhasivam X-Google-Original-From: Manivannan Sadhasivam To: ryder.lee@mediatek.com, jianjun.wang@mediatek.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org Cc: robh@kernel.org, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam , stable@vger.kernel.org, Caleb James DeLisle Subject: [PATCH v2] PCI: mediatek: Fix IRQ domain leak when port fails to enable Date: Thu, 21 May 2026 23:16:17 +0530 Message-ID: <20260521174617.17692-1-mani@kernel.org> X-Mailer: git-send-email 2.48.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: q-MifEEBs5PS9pw0VeB7L3c6QX6SqCC9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIxMDE3OSBTYWx0ZWRfX/+vSKmEKrJaz jSQLklN/k1xGy/Y8p4PDsUf0asNWzzpgokuYUQWGt5pi+Q41iGEcB6IU7yucVr+csMN42sPUzJ5 /Tb0uCEWK0IHr/p1kS0fUY17QKzvpGgroVTrvxHa05wFTx9/46o0l3cC7PSIyyQRK4OBzjjVISL yqc7cax0RvFdKE+CQ9OZgpXWNB/gr/e/YrzEouI5Yb+dfLTyjf0HINj9eufYMWjcpZZ8FUPRjpm 83PTH2v6xai7n6onAfgGzYSMNATIU/luN+IveC62yD8fkbQJz82vknRShy/q/lj0RH6GtxuN66F 9Vx3+8FOr42/+ZCq9z65xeFRmmiXINT54rYN9NavbFUhwcOgnjM/FBBoUA3HzaY94ckQYNgi5/E WsYT21pX6TC7K3RmEJZXTkYMpUDnK5zvNf2rg6O4RqHWPbJEoFyEvpffwCDGgnsarTPV2UMemMe eIT3fofXnQTtZYyodyQ== X-Authority-Analysis: v=2.4 cv=YfyNIQRf c=1 sm=1 tr=0 ts=6a0f44f3 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=F8mVszBSU3svo1NvbJWAvw==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=qMEm_45GddOWhgBJpCIA:9 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: q-MifEEBs5PS9pw0VeB7L3c6QX6SqCC9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-21_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 suspectscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605210179 Content-Type: text/plain; charset="utf-8" From: Manivannan Sadhasivam When mtk_pcie_enable_port() fails, mtk_pcie_port_free() removes the port from pcie->ports and frees the port structure. However, the IRQ domains set up earlier by mtk_pcie_init_irq_domain() are never freed. Fix this by refactoring mtk_pcie_irq_teardown() into a per-port helper, mtk_pcie_irq_teardown_port(), and calling it from mtk_pcie_setup() when mtk_pcie_enable_port() fails. Since the IRQ teardown must only happen in the probe error path (during resume, child devices may have active MSI mappings and the NOIRQ context prohibits sleeping locks), mtk_pcie_enable_port() is changed to return an error code so callers can distinguish the two paths and act accordingly. This issue was reported by Sashiko while reviewing the EcoNet EN7528 SoC support series. Cc: stable@vger.kernel.org # 5.10 Cc: Caleb James DeLisle Fixes: b099631df160 ("PCI: mediatek: Add controller support for MT2712 and = MT7622") Signed-off-by: Manivannan Sadhasivam --- Changes in v2: * Used a different approach by refactoring mtk_pcie_irq_teardown() and call= ing mtk_pcie_irq_teardown_port() from mtk_pcie_setup(), as Sashiko flagged so= me potential issues with v1. drivers/pci/controller/pcie-mediatek.c | 63 ++++++++++++++++---------- 1 file changed, 40 insertions(+), 23 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controlle= r/pcie-mediatek.c index 75722524fe74..907ae4285ecb 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -529,23 +529,27 @@ static void mtk_pcie_enable_msi(struct mtk_pcie_port = *port) writel(val, port->base + PCIE_INT_MASK); } =20 -static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie) +static void mtk_pcie_irq_teardown_port(struct mtk_pcie_port *port) { - struct mtk_pcie_port *port, *tmp; + irq_set_chained_handler_and_data(port->irq, NULL, NULL); =20 - list_for_each_entry_safe(port, tmp, &pcie->ports, list) { - irq_set_chained_handler_and_data(port->irq, NULL, NULL); + if (port->irq_domain) + irq_domain_remove(port->irq_domain); =20 - if (port->irq_domain) - irq_domain_remove(port->irq_domain); + if (IS_ENABLED(CONFIG_PCI_MSI)) { + if (port->inner_domain) + irq_domain_remove(port->inner_domain); + } =20 - if (IS_ENABLED(CONFIG_PCI_MSI)) { - if (port->inner_domain) - irq_domain_remove(port->inner_domain); - } + irq_dispose_mapping(port->irq); +} =20 - irq_dispose_mapping(port->irq); - } +static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie) +{ + struct mtk_pcie_port *port, *tmp; + + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + mtk_pcie_irq_teardown_port(port); } =20 static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq, @@ -865,7 +869,7 @@ static int mtk_pcie_startup_port_an7583(struct mtk_pcie= _port *port) return mtk_pcie_startup_port_v2(port); } =20 -static void mtk_pcie_enable_port(struct mtk_pcie_port *port) +static int mtk_pcie_enable_port(struct mtk_pcie_port *port) { struct mtk_pcie *pcie =3D port->pcie; struct device *dev =3D pcie->dev; @@ -874,7 +878,7 @@ static void mtk_pcie_enable_port(struct mtk_pcie_port *= port) err =3D clk_prepare_enable(port->sys_ck); if (err) { dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot); - goto err_sys_clk; + return err; } =20 err =3D clk_prepare_enable(port->ahb_ck); @@ -922,11 +926,15 @@ static void mtk_pcie_enable_port(struct mtk_pcie_port= *port) goto err_phy_on; } =20 - if (!pcie->soc->startup(port)) - return; + err =3D pcie->soc->startup(port); + if (err) { + dev_info(dev, "Port%d link down\n", port->slot); + goto err_soc_startup; + } =20 - dev_info(dev, "Port%d link down\n", port->slot); + return 0; =20 +err_soc_startup: phy_power_off(port->phy); err_phy_on: phy_exit(port->phy); @@ -942,8 +950,8 @@ static void mtk_pcie_enable_port(struct mtk_pcie_port *= port) clk_disable_unprepare(port->ahb_ck); err_ahb_clk: clk_disable_unprepare(port->sys_ck); -err_sys_clk: - mtk_pcie_port_free(port); + + return err; } =20 static int mtk_pcie_parse_port(struct mtk_pcie *pcie, @@ -1109,8 +1117,13 @@ static int mtk_pcie_setup(struct mtk_pcie *pcie) return err; =20 /* enable each port, and then check link status */ - list_for_each_entry_safe(port, tmp, &pcie->ports, list) - mtk_pcie_enable_port(port); + list_for_each_entry_safe(port, tmp, &pcie->ports, list) { + err =3D mtk_pcie_enable_port(port); + if (err) { + mtk_pcie_irq_teardown_port(port); + mtk_pcie_port_free(port); + } + } =20 /* power down PCIe subsys if slots are all empty (link down) */ if (list_empty(&pcie->ports)) @@ -1209,14 +1222,18 @@ static int mtk_pcie_resume_noirq(struct device *dev) { struct mtk_pcie *pcie =3D dev_get_drvdata(dev); struct mtk_pcie_port *port, *tmp; + int err; =20 if (list_empty(&pcie->ports)) return 0; =20 clk_prepare_enable(pcie->free_ck); =20 - list_for_each_entry_safe(port, tmp, &pcie->ports, list) - mtk_pcie_enable_port(port); + list_for_each_entry_safe(port, tmp, &pcie->ports, list) { + err =3D mtk_pcie_enable_port(port); + if (err) + mtk_pcie_port_free(port); + } =20 /* In case of EP was removed while system suspend. */ if (list_empty(&pcie->ports)) --=20 2.48.1