From nobody Sun May 24 20:34:45 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11C113C2B9C for ; Thu, 21 May 2026 13:05:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779368742; cv=none; b=KHJicuj2zV28Vb1CYf8uZtIG4JwThuqJpmIrn8vzD/XHkJaVrxhQRaD/vO47G8jCUI90G4NGarR/SeLQyfL4VxDaCEgQnRSyfsnagduQ0y6EsSyqj24rjU67Vw+RksOL8+IDhMLPnd8NGZvQRy8fijuhoew3MSS863msOb30iZ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779368742; c=relaxed/simple; bh=MXVb6shOF8kc6JfjsBKEO28b2NFGXqTGXPSyJyP4mmc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HVgcdOEf0VfYogL5J8LaPiLgm5rlr+gQnc13+GEy4nG679OfOVIvlcD9eKQPRJx9qtMIchybhPffItVFTJ3vL7Qb8QrrAVUgCiorAg/AK+wtbhc2Jm9fSCsmD4oJ+lLlfNMoGs5VWmtgPdf2IP8mcemB3FaoAURzSpGGZprhacE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=hDmDeDl2; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="hDmDeDl2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1779368740; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=n2Xg61qDILSmucUjgxrF173mJJSUSxq30iR0zCuIF2A=; b=hDmDeDl271iPperecCqGJc1kcgOFXSj4mFFedfB1mHaMie+J4MDUvTcRn2cEMXEQ2ICf3/ KS8OyryCxqJSUnXB97gRlPIvQ52m/Z7fWzK2T8wkr2Y/JGaqPd97i4Y37zJxRDHY1IGNxh DJQ1+xEeduCXQ3k13KCGXo0eOa6DN+U= Received: from mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-176-idGagvD2MYigfF1OGExscA-1; Thu, 21 May 2026 09:05:37 -0400 X-MC-Unique: idGagvD2MYigfF1OGExscA-1 X-Mimecast-MFC-AGG-ID: idGagvD2MYigfF1OGExscA_1779368736 Received: from mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.111]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 7D9511800657; Thu, 21 May 2026 13:05:36 +0000 (UTC) Received: from fedora.redhat.com (unknown [10.44.48.82]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 7419A1800352; Thu, 21 May 2026 13:05:34 +0000 (UTC) From: Jose Ignacio Tornos Martinez To: bhelgaas@google.com, alex@shazbot.org Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Jose Ignacio Tornos Martinez Subject: [PATCH v5 1/3] PCI: Add d3cold as general reset method Date: Thu, 21 May 2026 15:05:10 +0200 Message-ID: <20260521130512.515125-2-jtornosm@redhat.com> In-Reply-To: <20260521130512.515125-1-jtornosm@redhat.com> References: <20260521130512.515125-1-jtornosm@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Content-Type: text/plain; charset="utf-8" Add D3cold power cycle as a general PCI reset method for single-function devices on platforms with ACPI _PR3 power resources. This provides true power cycle reset capability when the platform can physically cut power to the device. The implementation strictly requires _PR3 to be present - the platform must be able to control device power. This ensures d3cold only attempts true power cycling, not falling back to D3hot transitions. D3cold reset is placed at the end of the reset hierarchy since it requires specific platform support and should be tried after standard methods. Reset hierarchy with this change: 1. device_specific 2. acpi 3. flr 4. af_flr 5. pm (D3hot via config space, checks NoSoftRst) 6. bus (SBR) 7. cxl_bus 8. d3cold (NEW - true power cycle, requires _PR3) This benefits: - Platforms with _PR3 support - Single-function devices needing true power cycle - VFIO passthrough scenarios where FLR/PM unavailable Signed-off-by: Jose Ignacio Tornos Martinez --- v5: Address the suggestion of AI review (sashiko.dev), add IOMMU handling (pci_dev_reset_iommu_prepare/done) to prevent IOMMU faults during power state transitions v4: https://lore.kernel.org/all/20260518124836.460805-2-jtornosm@redhat.com/ drivers/pci/pci.c | 50 +++++++++++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 2 +- 2 files changed, 51 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 8f7cfcc00090..096868f80cd4 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4491,6 +4491,55 @@ static int pci_pm_reset(struct pci_dev *dev, bool pr= obe) return ret; } =20 +/** + * pci_d3cold_reset - Put device into D3cold and back to D0 for reset + * @dev: PCI device to reset + * @probe: if true, check if D3cold reset is supported; if false, perform = reset + * + * Reset the device by transitioning through D3cold (actual power removal = via + * platform power control) and back to D0. This requires ACPI _PR3 power + * resources to be present - the platform must be able to physically cut p= ower + * to the device. + * + * Only available for single-function devices to avoid affecting other + * functions in multi-function devices. + * + * Returns 0 if device can be/was reset this way, -ENOTTY if not supported, + * or other negative error code on failure. + */ +static int pci_d3cold_reset(struct pci_dev *dev, bool probe) +{ + int ret; + + if (dev->multifunction) + return -ENOTTY; + + if (!pci_pr3_present(dev)) + return -ENOTTY; + + if (probe) + return 0; + + if (dev->current_state !=3D PCI_D0) + return -EINVAL; + + ret =3D pci_dev_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", ret); + return ret; + } + + ret =3D pci_set_power_state(dev, PCI_D3cold); + if (ret) + goto done; + + ret =3D pci_set_power_state(dev, PCI_D0); + +done: + pci_dev_reset_iommu_done(dev); + return ret; +} + /** * pcie_wait_for_link_status - Wait for link status change * @pdev: Device whose link to wait for. @@ -5065,6 +5114,7 @@ const struct pci_reset_fn_method pci_reset_fn_methods= [] =3D { { pci_pm_reset, .name =3D "pm" }, { pci_reset_bus_function, .name =3D "bus" }, { cxl_reset_bus_function, .name =3D "cxl_bus" }, + { pci_d3cold_reset, .name =3D "d3cold" }, }; =20 /** diff --git a/include/linux/pci.h b/include/linux/pci.h index 2c4454583c11..1ca7b880ead7 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -51,7 +51,7 @@ PCI_STATUS_PARITY) =20 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */ -#define PCI_NUM_RESET_METHODS 8 +#define PCI_NUM_RESET_METHODS 9 =20 #define PCI_RESET_PROBE true #define PCI_RESET_DO_RESET false --=20 2.54.0 From nobody Sun May 24 20:34:45 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 501B23E2ACD for ; Thu, 21 May 2026 13:06:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779368761; cv=none; b=JsYL4Wu4ULBdOx/nQi1UylJUPag1HrjDfiUo8Ks5lZArpiIiTYZtmnVH8JV554u0r+Wl9qC/S47YydrVma7IvVNwFJX9hSt68KjeeTmwbazH4NIEbum9ltUCTtmFFYxMDlm2qFQV+RmqgNaxuy0N53tEZGdV9Ujo+bRs/dieu3U= ARC-Message-Signature: i=1; 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Thu, 21 May 2026 13:05:51 +0000 (UTC) Received: from fedora.redhat.com (unknown [10.44.48.82]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id C1AE31800465; Thu, 21 May 2026 13:05:49 +0000 (UTC) From: Jose Ignacio Tornos Martinez To: bhelgaas@google.com, alex@shazbot.org Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Jose Ignacio Tornos Martinez Subject: [PATCH v5 2/3] PCI: Add device-specific reset for Qualcomm devices Date: Thu, 21 May 2026 15:05:11 +0200 Message-ID: <20260521130512.515125-3-jtornosm@redhat.com> In-Reply-To: <20260521130512.515125-1-jtornosm@redhat.com> References: <20260521130512.515125-1-jtornosm@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Content-Type: text/plain; charset="utf-8" Some Qualcomm PCIe devices (ath11k WiFi, ath12k WiFi, SDX62/SDX65 modems) lack working reset methods for VFIO passthrough scenarios. These devices have no FLR capability, advertise NoSoftRst+ (blocking PM reset), and have broken bus reset. The problem manifests in VFIO passthrough scenarios: - ath11k WiFi (17cb:1103): Normal VM operation works fine, including clean shutdown/reboot. However, when the VM terminates uncleanly (crash, force-off), VFIO attempts to reset the device before it can be assigned to another VM. Without a working reset method, the device remains in an undefined state, preventing reuse. - ath12k WiFi (17cb:1107): Same behavior as ath11k. - SDX62/SDX65 5G modems (17cb:0308): Never successfully initialize even on first VM assignment without proper reset capability. Add device-specific reset entries for these Qualcomm devices using D3cold power cycling with automatic D3hot fallback. The implementation uses pci_set_power_state(D3cold) which automatically falls back to D3hot on platforms without ACPI _PR3 power resources. Extract a shared pci_dev_d3cold_d0_cycle() helper function to avoid code duplication between pci_d3cold_reset() (strict _PR3 requirement) and the new reset_d3cold_d3hot() device-specific reset (automaticfallback). The helper handles IOMMU preparation, performs the power cycle via pci_set_power_state(), and cleans up IOMMU state. Device-specific reset is position #1 in the reset hierarchy, so these Qualcomm devices will use power cycling as their primary reset method, with the general d3cold method (position #8) available as a fallback on _PR3-capable platforms if users override via sysfs. Signed-off-by: Jose Ignacio Tornos Martinez --- v5: Follow the advice from Alex Williamson, replace v4's general "soft" reset method (patch 2/3) as too broad by a device-specific reset using pci_dev_reset_methods[] v4: https://lore.kernel.org/all/20260518124836.460805-3-jtornosm@redhat.com/ drivers/pci/pci.c | 55 ++++++++++++++++++++++++++++---------------- drivers/pci/pci.h | 1 + drivers/pci/quirks.c | 19 +++++++++++++++ 3 files changed, 55 insertions(+), 20 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 096868f80cd4..3677aaf8d160 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4491,6 +4491,40 @@ static int pci_pm_reset(struct pci_dev *dev, bool pr= obe) return ret; } =20 +/** + * pci_dev_d3cold_d0_cycle - Perform D3cold->D0 power cycle + * @dev: Device to power cycle + * + * Common helper to perform D3cold->D0 power cycle for reset methods. + * Attempts D3cold transition with automatic fallback to D3hot on platforms + * without ACPI _PR3 power resources. Handles IOMMU preparation and cleanu= p. + * + * Returns 0 on success, negative error code on failure. + */ +int pci_dev_d3cold_d0_cycle(struct pci_dev *dev) +{ + int ret; + + if (dev->current_state !=3D PCI_D0) + return -EINVAL; + + ret =3D pci_dev_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", ret); + return ret; + } + + ret =3D pci_set_power_state(dev, PCI_D3cold); + if (ret) + goto done; + + ret =3D pci_set_power_state(dev, PCI_D0); + +done: + pci_dev_reset_iommu_done(dev); + return ret; +} + /** * pci_d3cold_reset - Put device into D3cold and back to D0 for reset * @dev: PCI device to reset @@ -4509,8 +4543,6 @@ static int pci_pm_reset(struct pci_dev *dev, bool pro= be) */ static int pci_d3cold_reset(struct pci_dev *dev, bool probe) { - int ret; - if (dev->multifunction) return -ENOTTY; =20 @@ -4520,24 +4552,7 @@ static int pci_d3cold_reset(struct pci_dev *dev, boo= l probe) if (probe) return 0; =20 - if (dev->current_state !=3D PCI_D0) - return -EINVAL; - - ret =3D pci_dev_reset_iommu_prepare(dev); - if (ret) { - pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", ret); - return ret; - } - - ret =3D pci_set_power_state(dev, PCI_D3cold); - if (ret) - goto done; - - ret =3D pci_set_power_state(dev, PCI_D0); - -done: - pci_dev_reset_iommu_done(dev); - return ret; + return pci_dev_d3cold_d0_cycle(dev); } =20 /** diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 4a14f88e543a..a9942787de9e 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -234,6 +234,7 @@ void pci_init_reset_methods(struct pci_dev *dev); int pci_bridge_secondary_bus_reset(struct pci_dev *dev); int pci_bus_error_reset(struct pci_dev *dev); int pci_try_reset_bridge(struct pci_dev *bridge); +int pci_dev_d3cold_d0_cycle(struct pci_dev *dev); =20 struct pci_cap_saved_data { u16 cap_nr; diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index e49136ac5dbf..70f3b0f26799 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4237,6 +4237,22 @@ static int reset_hinic_vf_dev(struct pci_dev *pdev, = bool probe) return 0; } =20 +/* + * Device-specific reset method via D3cold/D3hot power cycle. + * + * Some devices lack working FLR, advertise NoSoftRst+ (blocking PM reset), + * and have broken bus reset. This function provides device-specific reset= via + * power cycling, attempting D3cold with automatic fallback to D3hot on pl= atforms + * without ACPI _PR3 power resources. + */ +static int reset_d3cold_d3hot(struct pci_dev *dev, bool probe) +{ + if (probe) + return 0; + + return pci_dev_d3cold_d0_cycle(dev); +} + static const struct pci_dev_reset_methods pci_dev_reset_methods[] =3D { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, reset_intel_82599_sfp_virtfn }, @@ -4252,6 +4268,9 @@ static const struct pci_dev_reset_methods pci_dev_res= et_methods[] =3D { reset_chelsio_generic_dev }, { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF, reset_hinic_vf_dev }, + { PCI_VENDOR_ID_QCOM, 0x1103, reset_d3cold_d3hot }, /* ath11k */ + { PCI_VENDOR_ID_QCOM, 0x1107, reset_d3cold_d3hot }, /* ath12k */ + { PCI_VENDOR_ID_QCOM, 0x0308, reset_d3cold_d3hot }, /* SDX62/SDX65 */ { 0 } }; =20 --=20 2.54.0 From nobody Sun May 24 20:34:45 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E21DE3CE0A8 for ; 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Thu, 21 May 2026 09:05:58 -0400 X-MC-Unique: 9iXTnHttM2uiINIyJgiBbQ-1 X-Mimecast-MFC-AGG-ID: 9iXTnHttM2uiINIyJgiBbQ_1779368757 Received: from mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.111]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id F25DF19560B7; Thu, 21 May 2026 13:05:56 +0000 (UTC) Received: from fedora.redhat.com (unknown [10.44.48.82]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 08B621800591; Thu, 21 May 2026 13:05:54 +0000 (UTC) From: Jose Ignacio Tornos Martinez To: bhelgaas@google.com, alex@shazbot.org Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Jose Ignacio Tornos Martinez Subject: [PATCH v5 3/3] PCI: Disable broken bus reset on Qualcomm devices Date: Thu, 21 May 2026 15:05:12 +0200 Message-ID: <20260521130512.515125-4-jtornosm@redhat.com> In-Reply-To: <20260521130512.515125-1-jtornosm@redhat.com> References: <20260521130512.515125-1-jtornosm@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Content-Type: text/plain; charset="utf-8" Some Qualcomm PCIe devices (ath11k WiFi, ath12k WiFi, SDX62/SDX65 modems) do not properly support Secondary Bus Reset (SBR). Testing confirms this is device-specific, not deployment-specific: MediaTek MT7925e successfully uses bus reset through the same passive M.2-to-PCIe adapters where Qualcomm devices fail, proving PERST# is properly wired through the adapters. This quirk acts as a safety net, preventing the broken bus reset from being attempted if users override reset methods (device_specific or d3cold when available) via sysfs. Signed-off-by: Jose Ignacio Tornos Martinez --- v5: Quirk code unchanged from v4 v4: https://lore.kernel.org/all/20260518124836.460805-4-jtornosm@redhat.com/ drivers/pci/quirks.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 000000000000..111111111111 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3789,6 +3789,9 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003= 0, quirk_no_bus_reset); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset= ); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset= ); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset= ); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset= ); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset= ); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_QCOM, 0x1103, quirk_no_bus_reset); = /* ath11k */ +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_QCOM, 0x1107, quirk_no_bus_reset); = /* ath12k */ +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_QCOM, 0x0308, quirk_no_bus_reset); = /* SDX62/SDX65 */ /* * Root port on some Cavium CN8xxx chips do not successfully complete a bus -- 2.53.0