From nobody Sun May 24 20:36:24 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E34C3F9267; Thu, 21 May 2026 12:44:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779367487; cv=none; b=pU2UclBGoIkDRaFkPif9KU1ON0o4Yq48R1Ysf9KzuG+eoZRt4Xj3QEoPLYUKsAsmHT52hSy8/fNYfKG7td+vTyztdylvl3hJAcNNn0OWKJRss0UY8nJEMeRHGpPbQ2a0NpUvI8PmMjpfF7mqCa8zPsgVGj4J3KjAYaPQ1YuiqbA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779367487; c=relaxed/simple; bh=vl0PT/MORTjvkVXEPloURKq/4N2xHH2AuBE1J8ygcS4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rAk2HBVBIb4CGpYT8HupBw9ReX7C9jJRvvLf52/kqDU0N7etIkgSTSNe6In3qUOMzbTqnLDnYLu32jsvnFmJ7gb7PQezVP71N3jeI8wm3BG8uGkh3AduHpHi4t5aYnTY7nB7joBQmD4ezPfvX0oOwsvuU5o4fIcoTgcaV9fB9EM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=E5FYaA39; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="E5FYaA39" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779367483; x=1810903483; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vl0PT/MORTjvkVXEPloURKq/4N2xHH2AuBE1J8ygcS4=; b=E5FYaA393RQvnQpQ9kKQLoh515GblIwzkhkjlG2rQtB62s5AsZlMF4tb cKHzWhkDcm6dZIX4oHqG99QjNAftsQshZFO8DlikQ8/niIQauieZ2RIii Mvkz2JiZHStgCnzwNjqHcHc7b9Rr0RuKdMfWRSYJplISBDRa55oGyeq1t dHSNA7KH8k/2xB7or9WEKkME6QMqEffOAaEzpbc+tZ6A12y8Riye36esB B/PofXjayeyz64f2BDjXK/dfPCMlLuhpSGCqtGD78DiTs9Nb4d+rw6ORJ IIrRvdwTBhVZ835v6YNM9OgaMUd8CBt+aV6dIatKE1AdNEhAiGnGjkKL8 g==; X-CSE-ConnectionGUID: hSUiJMwPQ/emCetqfkPw1Q== X-CSE-MsgGUID: TTgiaLoLTOedI4R2Ci+dSA== X-IronPort-AV: E=McAfee;i="6800,10657,11792"; a="80265197" X-IronPort-AV: E=Sophos;i="6.23,246,1770624000"; d="scan'208";a="80265197" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 05:44:42 -0700 X-CSE-ConnectionGUID: FZ38KbHwT7GvCp1U7fGjZQ== X-CSE-MsgGUID: 1qZdHEYaQ2WlVbcD9ob2Og== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,246,1770624000"; d="scan'208";a="236265146" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 05:44:40 -0700 From: Qiuxu Zhuo To: Tony Luck , Borislav Petkov Cc: Qiuxu Zhuo , Jie Wang , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] EDAC/igen6: Make registers for detecting IBECC configurable Date: Thu, 21 May 2026 20:38:11 +0800 Message-ID: <20260521123812.3961038-2-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260521123812.3961038-1-qiuxu.zhuo@intel.com> References: <20260521123812.3961038-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some Intel CPUs with IBECC (In-Band ECC) capability use different registers to indicate IBECC presence. Make IBECC detection registers CPU-model specific and configure them properly for scalable IBECC detection. No functional changes intended. Tested-by: Jie Wang Signed-off-by: Qiuxu Zhuo --- drivers/edac/igen6_edac.c | 55 +++++++++++++++++++-------------------- 1 file changed, 27 insertions(+), 28 deletions(-) diff --git a/drivers/edac/igen6_edac.c b/drivers/edac/igen6_edac.c index f3e53d63eb54..a761d683eae3 100644 --- a/drivers/edac/igen6_edac.c +++ b/drivers/edac/igen6_edac.c @@ -151,6 +151,8 @@ static struct res_config { /* MEMSS_PMA_CR registers. */ u32 reg_mem_config_offset; u32 reg_mem_config_ddr_type_mask; + u32 reg_capabilities_misc_offset; + u32 reg_capabilities_misc_ibecc_dis; /* Memory controller registers. */ u32 reg_mad_inter_size_mask[NUM_CHANNELS]; u64 reg_mad_inter_size_granularity; @@ -405,27 +407,22 @@ static bool mtl_p_ibecc_available(struct pci_dev *pde= v) return !(CAPID_E_IBECC_BIT18 & v); } =20 -static bool mtl_ps_ibecc_available(struct pci_dev *pdev) +static bool generic_ibecc_available(struct pci_dev *pdev) { -#define MCHBAR_MEMSS_IBECCDIS 0x13c00 - void __iomem *window; - u64 mchbar; + void __iomem *base =3D igen6_pvt->memss_pma_cr; + bool present; u32 val; =20 - if (get_mchbar(pdev, &mchbar)) - return false; - - window =3D ioremap(mchbar, MCHBAR_SIZE * 2); - if (!window) { - igen6_printk(KERN_ERR, "Failed to ioremap 0x%llx\n", mchbar); - return false; + if (res_cfg->reg_capabilities_misc_offset) { + val =3D readl(base + res_cfg->reg_capabilities_misc_offset); + present =3D !(val & res_cfg->reg_capabilities_misc_ibecc_dis); + edac_dbg(2, "capabilities misc reg 0x%x\n", val); + } else { + igen6_printk(KERN_ERR, "No register for detecting IBECC presence.\n"); + present =3D false; } =20 - val =3D readl(window + MCHBAR_MEMSS_IBECCDIS); - iounmap(window); - - /* Bit6: 1 - IBECC is disabled, 0 - IBECC isn't disabled */ - return !GET_BITFIELD(val, 6, 6); + return present; } =20 static u64 mem_addr_to_sys_addr(u64 maddr) @@ -725,18 +722,20 @@ static struct res_config rpl_p_cfg =3D { }; =20 static struct res_config mtl_ps_cfg =3D { - .machine_check =3D true, - .num_imc =3D 2, - .reg_mchbar_mask =3D GENMASK_ULL(41, 17), - .reg_tom_mask =3D GENMASK_ULL(41, 20), - .reg_touud_mask =3D GENMASK_ULL(41, 20), - .reg_eccerrlog_addr_mask =3D GENMASK_ULL(38, 5), - .imc_base =3D 0xd800, - .ibecc_base =3D 0xd400, - .ibecc_error_log_offset =3D 0x170, - .ibecc_available =3D mtl_ps_ibecc_available, - .err_addr_to_sys_addr =3D adl_err_addr_to_sys_addr, - .err_addr_to_imc_addr =3D adl_err_addr_to_imc_addr, + .machine_check =3D true, + .num_imc =3D 2, + .reg_mchbar_mask =3D GENMASK_ULL(41, 17), + .reg_tom_mask =3D GENMASK_ULL(41, 20), + .reg_touud_mask =3D GENMASK_ULL(41, 20), + .reg_eccerrlog_addr_mask =3D GENMASK_ULL(38, 5), + .reg_capabilities_misc_offset =3D 0x13c00, + .reg_capabilities_misc_ibecc_dis =3D BIT(6), + .imc_base =3D 0xd800, + .ibecc_base =3D 0xd400, + .ibecc_error_log_offset =3D 0x170, + .ibecc_available =3D generic_ibecc_available, + .err_addr_to_sys_addr =3D adl_err_addr_to_sys_addr, + .err_addr_to_imc_addr =3D adl_err_addr_to_imc_addr, }; =20 static struct res_config mtl_p_cfg =3D { --=20 2.43.0 From nobody Sun May 24 20:36:24 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD2FC3FC5D7; Thu, 21 May 2026 12:44:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779367497; cv=none; b=bRju0vQQ4nQolyS/11SULdlPmLnxp4cKhXSZ4LTOHYrRbH5ogEjA0X2F6sodp7Ml+hqp+StpjyNpchYJLb13x/29IjPhgGu0DcBfIp73H7nrtrL5UgoF2Ag0dGtn6Vv1FKqG9JRCWyjZwt2qYaVH2Hzs5lvhjl4PGNAM/Ov6u0g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779367497; c=relaxed/simple; bh=vkpTdE49LW3ePrA6mNyoeYRGMf3DT/A0A8Svp1xxlVA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TGHnhCwuXopvRwDDoTWec/zzL+718ONQWajNcWq6WRKU7yfeoipwV0hX4tzlLcJVMSYN2pF6dX2RyDoz+Z3ej+S5mkZvW+BvhllJ3W6bgNNOQK4LFu1E3vTXqKtJSWvtb44Gink+72mFQJUcSBVx/zmAfTa3B9fW0mCZVKYvVpU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MB/9nc3C; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MB/9nc3C" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779367490; x=1810903490; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vkpTdE49LW3ePrA6mNyoeYRGMf3DT/A0A8Svp1xxlVA=; b=MB/9nc3C7/vHcnPUV8uESiaESuR7kIL59+brGTm49wTBywEs8XA+GuB1 tYL8Unnk9K20cOZwG++hzAJWwz/UY7zfBRBnWbEVq1FPs97v1Ml8jo4nj 5Kxjvfo/ltpgA/t/sXPvpGrCCPZkkOKVD3SZqHfVzlIaODed//7iDf4Jc fHJAUgsgK23y6uzuOY0vb/F7I4GYpXe394JSjOfZCY88YQVnnJPAHhKYZ BlElziiyMp80LQQjNHaU13SKsAXsnWEQW3LArxNg60MU4/32Jya1KBp87 9E+OHBdz9xeCJ+zI5cbzPSwEfAQhoP9JIZTPVVMXSg1foAita552sjqhV Q==; X-CSE-ConnectionGUID: hF49MM+SQMq2yM+C1rwOKA== X-CSE-MsgGUID: jGauXXbHTvWQpD6iWjo+YQ== X-IronPort-AV: E=McAfee;i="6800,10657,11792"; a="80265207" X-IronPort-AV: E=Sophos;i="6.23,246,1770624000"; d="scan'208";a="80265207" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 05:44:49 -0700 X-CSE-ConnectionGUID: 421uKTlsSpacgZwzxqpNQA== X-CSE-MsgGUID: bXnvk7OpSWGmgEpNQT+tbg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,246,1770624000"; d="scan'208";a="236265157" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2026 05:44:47 -0700 From: Qiuxu Zhuo To: Tony Luck , Borislav Petkov Cc: Qiuxu Zhuo , Jie Wang , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] EDAC/igen6: Add Intel Nova Lake-H SoC support Date: Thu, 21 May 2026 20:38:12 +0800 Message-ID: <20260521123812.3961038-3-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260521123812.3961038-1-qiuxu.zhuo@intel.com> References: <20260521123812.3961038-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Nova Lake-H SoCs share similar memory controller registers and IBECC (In-Band ECC) registers with Panther Lake-H SoCs but use a new memory subsystem register for IBECC presence detection. Add Nova Lake-H SoC compute die IDs and create a new configuration structure for Nova Lake-H SoCs to enable EDAC support. Tested-by: Jie Wang Signed-off-by: Qiuxu Zhuo --- drivers/edac/igen6_edac.c | 46 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/edac/igen6_edac.c b/drivers/edac/igen6_edac.c index a761d683eae3..9af15ac6ff84 100644 --- a/drivers/edac/igen6_edac.c +++ b/drivers/edac/igen6_edac.c @@ -151,6 +151,7 @@ static struct res_config { /* MEMSS_PMA_CR registers. */ u32 reg_mem_config_offset; u32 reg_mem_config_ddr_type_mask; + u32 reg_mem_config_ibecc_en_mask; u32 reg_capabilities_misc_offset; u32 reg_capabilities_misc_ibecc_dis; /* Memory controller registers. */ @@ -316,6 +317,12 @@ static struct work_struct ecclog_work; /* Compute die IDs for Wildcat Lake with IBECC */ #define DID_WCL_SKU1 0xfd00 =20 +/* Compute die IDs for Nova Lake-H/HX with IBECC */ +#define DID_NVL_H_SKU1 0xd701 +#define DID_NVL_H_SKU2 0xd702 +#define DID_NVL_H_SKU3 0xd704 +#define DID_NVL_H_SKU4 0xd705 + static int get_mchbar(struct pci_dev *pdev, u64 *mchbar) { union { @@ -417,6 +424,10 @@ static bool generic_ibecc_available(struct pci_dev *pd= ev) val =3D readl(base + res_cfg->reg_capabilities_misc_offset); present =3D !(val & res_cfg->reg_capabilities_misc_ibecc_dis); edac_dbg(2, "capabilities misc reg 0x%x\n", val); + } else if (res_cfg->reg_mem_config_offset) { + val =3D readl(base + res_cfg->reg_mem_config_offset); + present =3D !!(val & res_cfg->reg_mem_config_ibecc_en_mask); + edac_dbg(2, "mem config reg 0x%x\n", val); } else { igen6_printk(KERN_ERR, "No register for detecting IBECC presence.\n"); present =3D false; @@ -798,6 +809,37 @@ static struct res_config wcl_cfg =3D { .err_addr_to_imc_addr =3D adl_err_addr_to_imc_addr, }; =20 +static struct res_config nvl_h_cfg =3D { + .machine_check =3D true, + .num_imc =3D 2, + .reg_mchbar_mask =3D GENMASK_ULL(41, 17), + .reg_tom_mask =3D GENMASK_ULL(41, 20), + .reg_touud_mask =3D GENMASK_ULL(41, 20), + .reg_eccerrlog_addr_mask =3D GENMASK_ULL(38, 5), + .reg_mem_config_offset =3D 0x12904, + .reg_mem_config_ddr_type_mask =3D GENMASK(8, 6), + .reg_mem_config_ibecc_en_mask =3D GENMASK(3, 2), + .reg_mad_inter_size_mask[0] =3D GENMASK(15, 8), + .reg_mad_inter_size_mask[1] =3D GENMASK(23, 16), + .reg_mad_inter_size_granularity =3D BIT_ULL(29), + .reg_mad_intra_rank_mask[0] =3D BIT(7), + .reg_mad_intra_rank_mask[1] =3D BIT(15), + .reg_mad_intra_width_mask[0] =3D BIT(6), + .reg_mad_intra_width_mask[1] =3D BIT(14), + .reg_mad_intra_density_mask[0] =3D GENMASK(3, 0), + .reg_mad_intra_density_mask[1] =3D GENMASK(11, 8), + .imc_base =3D 0xd800, + .ibecc_base =3D 0xd400, + .ibecc_error_log_offset =3D 0x170, + .get_mem_type =3D ptl_h_get_mem_type, + .get_dev_type =3D ptl_h_get_dev_type, + .set_chan_params =3D ptl_h_set_chan_params, + .set_dimm_params =3D ptl_h_set_dimm_params, + .ibecc_available =3D generic_ibecc_available, + .err_addr_to_sys_addr =3D adl_err_addr_to_sys_addr, + .err_addr_to_imc_addr =3D adl_err_addr_to_imc_addr, +}; + static struct pci_device_id igen6_pci_tbl[] =3D { { PCI_VDEVICE(INTEL, DID_EHL_SKU5), (kernel_ulong_t)&ehl_cfg }, { PCI_VDEVICE(INTEL, DID_EHL_SKU6), (kernel_ulong_t)&ehl_cfg }, @@ -865,6 +907,10 @@ static struct pci_device_id igen6_pci_tbl[] =3D { { PCI_VDEVICE(INTEL, DID_PTL_H_SKU13), (kernel_ulong_t)&ptl_h_cfg }, { PCI_VDEVICE(INTEL, DID_PTL_H_SKU14), (kernel_ulong_t)&ptl_h_cfg }, { PCI_VDEVICE(INTEL, DID_WCL_SKU1), (kernel_ulong_t)&wcl_cfg }, + { PCI_VDEVICE(INTEL, DID_NVL_H_SKU1), (kernel_ulong_t)&nvl_h_cfg }, + { PCI_VDEVICE(INTEL, DID_NVL_H_SKU2), (kernel_ulong_t)&nvl_h_cfg }, + { PCI_VDEVICE(INTEL, DID_NVL_H_SKU3), (kernel_ulong_t)&nvl_h_cfg }, + { PCI_VDEVICE(INTEL, DID_NVL_H_SKU4), (kernel_ulong_t)&nvl_h_cfg }, { }, }; MODULE_DEVICE_TABLE(pci, igen6_pci_tbl); --=20 2.43.0