From nobody Sun May 24 20:34:45 2026 Received: from mail-m3290.qiye.163.com (mail-m3290.qiye.163.com [220.197.32.90]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D59626ED25; Thu, 21 May 2026 14:08:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.90 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779372494; cv=none; b=Hc+v1SUBvTMOeMNgFrQymZlP/ymMj+eCf//QzBKUVLnW5+blNL8r4L1tCC1xZR62jVhL0GDaf20SaXTIAI5zVPalD6RJhtmiD3u/ZaB/mxdJPlmQUn3kFr0wbOwOWn7B//GeQ+fUlN7WF/srUCkXG52p7Vqbyfzqs8hf3npkoQc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779372494; c=relaxed/simple; bh=PzCfdeMgxHZUAy6GyRAEU851bWonkK4ZMObu0m3qBQE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TMot0GFubomhXyZYoh5JKK7h7iPZA5Ow0y8uoclm5xu3cZR/kMW77nQvQjYxBCK2M1cosLknms1kLx9V1bcRkaattesncm9HJxVmDVEvLMuWPE72JwFIj/0KeqXgR0Gs/D/asbH8s3gbkJOLgW2yApb6DKTLBdWJlQWMuo2cCsY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=hqdjcljG; arc=none smtp.client-ip=220.197.32.90 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="hqdjcljG" Received: from zyb-HP-ProDesk-680-G2-MT.. (unknown [61.154.14.86]) by smtp.qiye.163.com (Hmail) with ESMTP id 3f5009432; Thu, 21 May 2026 19:45:13 +0800 (GMT+08:00) From: Damon Ding To: hjc@rock-chips.com, heiko@sntech.de, andy.yan@rock-chips.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org Cc: Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, nicolas.frattaroli@collabora.com, cristian.ciocaltea@collabora.com, sebastian.reichel@collabora.com, dmitry.baryshkov@oss.qualcomm.com, luca.ceresoli@bootlin.com, dianders@chromium.org, m.szyprowski@samsung.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Damon Ding Subject: [PATCH v2 1/3] dt-bindings: display: bridge: analogix-dp: Add data-lanes support for endpoint Date: Thu, 21 May 2026 19:44:57 +0800 Message-Id: <20260521114459.1394264-2-damon.ding@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260521114459.1394264-1-damon.ding@rock-chips.com> References: <20260521114459.1394264-1-damon.ding@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a9e4a5a9f7303a3kunmad9184e677768 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWRgWCB1ZQUpXWS1ZQUlXWQ8JGhUIEh9ZQVkaGkJLVk1DSEkeGB4YTE1IS1YVFA kWGhdVEwETFhoSFyQUDg9ZV1kYEgtZQVlNSlVKTk9VSk9VQ01ZV1kWGg8SFR0UWUFZT0tIVUpLSE pKQk1VSktLVUpCWQY+ DKIM-Signature: a=rsa-sha256; b=hqdjcljGsxyTmfX06y3C3Se7JNYUa+1+U/AnCJYEDwzLTCpDOT65czKGEl1ajeT5UUJVHGeGEaCZOT8rG6eXZGp4wldTEtvfJpmFZiJWLK5rpYSJjz3ceQxw1sNTIjH3lYKxznkaWp+TX4cBZxcT70HqGZOwHTE7k97Tu7CU8O8=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=Xu79CGy7oXgHkId0a/dytBXCz0cn2ptJALLOPB88Bf8=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add data-lanes property support to the port@1 endpoint for physical lane mapping configuration. Lane mapping is mainly used for below scenarios: 1. Correct PCB lane swap and differential line routing crossover without hardware changes; 2. Adapt mismatched lane pin definitions between SoC and eDP panel; 3. Support multiple panel hardware variants on the same board by configuring data-lanes in device tree only. Signed-off-by: Damon Ding --- Changes in v2: - Add lane mapping application scenarios in commit message. - Remove redundant deprecated property 'data-lanes' for eDP node. - Update port@1 $ref to /schemas/graph.yaml#/$defs/port-base. --- .../bindings/display/bridge/analogix,dp.yaml | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/display/bridge/analogix,dp.y= aml b/Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml index 62f0521b0924..e34fdb21adb4 100644 --- a/Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml +++ b/Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml @@ -42,13 +42,20 @@ properties: properties: port@0: $ref: /schemas/graph.yaml#/properties/port - description: - Input node to receive pixel data. + description: Input node to receive pixel data. =20 port@1: - $ref: /schemas/graph.yaml#/properties/port - description: - Port node with one endpoint connected to a dp-connector node. + $ref: /schemas/graph.yaml#/$defs/port-base + description: Port node with one endpoint connected to sink device = node. + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + properties: + data-lanes: + minItems: 1 + maxItems: 4 + items: + enum: [ 0, 1, 2, 3 ] =20 required: - port@0 --=20 2.34.1 From nobody Sun May 24 20:34:45 2026 Received: from mail-m32118.qiye.163.com (mail-m32118.qiye.163.com [220.197.32.118]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26E783CF02E; Thu, 21 May 2026 12:20:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.118 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779366055; cv=none; b=GPYKAk41CXHTaMeNo/a6zu7Iktob2jOrvykz4Fh3BRur9DUfHX28LAlkDnJtspduzw4yJJmxbHUlEBGPeNqCBSA+Ujel53G5wAkxTdedA0VAvzDjZWfdkdT9JG1bExU9qyw4gZNqi/CklUkgBDjXwcuS3DI1fmJLGnG5FMdCuPs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779366055; c=relaxed/simple; bh=4BWCPZnCEYs5vgRGHHEtO//oZUNtWemwT86caw3lyn4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=H/PErf5s6kd5z6J8APBv2qp3GtOETwD89zFYegvw6h/742Ibylwum81WYugVrny+Q65QCvV/pw9mS38CcfhCtmNjZkFln58iJ/5G9jnvi8rfRCKbu31lI7w5Ht/qmewHTahBqCSYu7sLZ/BUdJEzkxw0WEbv1oBdEolinbKbUg8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=EXC1F9yu; arc=none smtp.client-ip=220.197.32.118 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="EXC1F9yu" Received: from zyb-HP-ProDesk-680-G2-MT.. (unknown [61.154.14.86]) by smtp.qiye.163.com (Hmail) with ESMTP id 3f5009434; Thu, 21 May 2026 19:45:14 +0800 (GMT+08:00) From: Damon Ding To: hjc@rock-chips.com, heiko@sntech.de, andy.yan@rock-chips.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org Cc: Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, nicolas.frattaroli@collabora.com, cristian.ciocaltea@collabora.com, sebastian.reichel@collabora.com, dmitry.baryshkov@oss.qualcomm.com, luca.ceresoli@bootlin.com, dianders@chromium.org, m.szyprowski@samsung.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Damon Ding Subject: [PATCH v2 2/3] dt-bindings: rockchip: analogix-dp: Add data-lanes example Date: Thu, 21 May 2026 19:44:58 +0800 Message-Id: <20260521114459.1394264-3-damon.ding@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260521114459.1394264-1-damon.ding@rock-chips.com> References: <20260521114459.1394264-1-damon.ding@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a9e4a5aa4a203a3kunmad9184e67776c X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWRgWCB1ZQUpXWS1ZQUlXWQ8JGhUIEh9ZQVkaTRhCVkpPGB1NSB0dGB4eT1YVFA kWGhdVEwETFhoSFyQUDg9ZV1kYEgtZQVlNSlVKTk9VSk9VQ01ZV1kWGg8SFR0UWUFZT0tIVUpLSE pKQk1VSktLVUpCWQY+ DKIM-Signature: a=rsa-sha256; b=EXC1F9yuTc+tl5/F+N4awUmmaKrZe9mRfjiMId9aWVSauh2NxtXP9orD84HZrTLA7f8DGJkCLMhAlGy5/HB5EPvlVTl9hen/oXiLd3Q9DEB66SvpTsDZ8OFBa7NugzdDBuO4IcCFv1NNZcmQcmjmPVR2XsxYF4mVBgHn7IEhfvw=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=KlebGy4vmLFS3sABadJGKLU3IR8mYj+LJC5u2ExLQAI=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add data-lanes setting in endpoint example to show actual lane mapping usage. Signed-off-by: Damon Ding --- .../bindings/display/rockchip/rockchip,analogix-dp.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,an= alogix-dp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchi= p,analogix-dp.yaml index bb75d898a5c5..cf75c926318b 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-= dp.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-= dp.yaml @@ -151,6 +151,7 @@ examples: reg =3D <1>; =20 edp_out_panel: endpoint { + data-lanes =3D <0 1>; remote-endpoint =3D <&panel_in_edp>; }; }; --=20 2.34.1 From nobody Sun May 24 20:34:45 2026 Received: from mail-m1973181.qiye.163.com (mail-m1973181.qiye.163.com [220.197.31.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 012F8360EDA; Thu, 21 May 2026 12:00:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779364850; cv=none; b=ZGUSYQt9RddXgbHiPR3jyjfsfAIbmpicpvlu8DGVgPcRHuMwc1gKS/LTGm9MF+Zsbkgcq6UOTHEPNiRMIDk6ucNilJCT2qnVpw5FLiDBy/GL3faat82ofdNVDD1U0Vwy9fApYuMObxf7FwQG2KwRUqHgVhMqMsuNqfrczuXnl7I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779364850; c=relaxed/simple; bh=CHlDNE9z0WKPa1PJfaedo1znuIIyJoJBerFc5sSc06M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SvZZR/bo0h7wgGjFwFmEFex76o1qgLGf1ZQ9OjK6rMQvkpt4Su/Mlh7Y0hZhU/VcqeK3t3PEfIRpDeZTe3OnXtu12JmaR32Ub//yV5M0xlPXVAmpv1FWVW07x+8JpcEryVsZ7hu+FN9R5UQVfbNFimEi8Sr6syzaNn714NHb13Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=RUFo+Pjg; arc=none smtp.client-ip=220.197.31.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="RUFo+Pjg" Received: from zyb-HP-ProDesk-680-G2-MT.. (unknown [61.154.14.86]) by smtp.qiye.163.com (Hmail) with ESMTP id 3f5009439; Thu, 21 May 2026 19:45:16 +0800 (GMT+08:00) From: Damon Ding To: hjc@rock-chips.com, heiko@sntech.de, andy.yan@rock-chips.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org Cc: Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, nicolas.frattaroli@collabora.com, cristian.ciocaltea@collabora.com, sebastian.reichel@collabora.com, dmitry.baryshkov@oss.qualcomm.com, luca.ceresoli@bootlin.com, dianders@chromium.org, m.szyprowski@samsung.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Damon Ding Subject: [PATCH v2 3/3] drm/bridge: analogix_dp: Add support for optional data-lanes mapping Date: Thu, 21 May 2026 19:44:59 +0800 Message-Id: <20260521114459.1394264-4-damon.ding@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260521114459.1394264-1-damon.ding@rock-chips.com> References: <20260521114459.1394264-1-damon.ding@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a9e4a5aaae503a3kunmad9184e677777 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWRgWCB1ZQUpXWS1ZQUlXWQ8JGhUIEh9ZQVkZGhhJVkxCSEsdHk0YQ0xPSVYVFA kWGhdVEwETFhoSFyQUDg9ZV1kYEgtZQVlNSlVKTk9VSk9VQ01ZV1kWGg8SFR0UWUFZT0tIVUpLSE pKQk1VSktLVUpCWQY+ DKIM-Signature: a=rsa-sha256; b=RUFo+PjgbR1zAlAiaOXr46eNbQpXSpl5SoOmFGDefG36kcsPc1VPXG4HC0x1nXfPl0B5AvvznvKh0pepSZGZoukN0tkUDvTiHOc+lvarp4RsJOCdZDzrAZdC/nVyV7QcTwQYoxEOtdEg2dGBDK4ddWycO2pw7gec/sKcW7LTkd4=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=MGZJIkp+bxuC8sN+1d1VBd1BwHThYFGRrqxTQBMfj8w=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Parse the optional 'data-lanes' device tree property to support custom physical lane mapping configuration. If no valid configuration is found, fall back to the default lane map (0, 1, 2, 3) automatically and keep the driver running. Lane mapping is mainly used for below scenarios: 1. Correct PCB lane swap and differential line routing crossover without hardware changes; 2. Adapt mismatched lane pin definitions between SoC and eDP panel; 3. Support multiple panel hardware variants on the same board by configuring data-lanes in device tree only. Signed-off-by: Damon Ding --- Changes in v2: - Add lane mapping application scenarios in commit message. --- .../drm/bridge/analogix/analogix_dp_core.c | 56 +++++++++++++++++++ .../drm/bridge/analogix/analogix_dp_core.h | 4 +- .../gpu/drm/bridge/analogix/analogix_dp_reg.c | 15 +++-- .../gpu/drm/bridge/analogix/analogix_dp_reg.h | 4 ++ 4 files changed, 70 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/g= pu/drm/bridge/analogix/analogix_dp_core.c index 5dc07ff84cd3..d1c6365118de 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -1234,6 +1234,59 @@ static const struct drm_bridge_funcs analogix_dp_bri= dge_funcs =3D { .detect =3D analogix_dp_bridge_detect, }; =20 +static int analogix_dp_dt_parse_lanes_map(struct analogix_dp_device *dp) +{ + struct video_info *video_info =3D &dp->video_info; + struct device_node *endpoint; + u32 tmp[LANE_COUNT4]; + u32 map[LANE_COUNT4] =3D {0, 1, 2, 3}; + bool used[LANE_COUNT4] =3D {false}; + int num_lanes; + int ret, i; + + memcpy(video_info->lane_map, map, sizeof(map)); + + num_lanes =3D drm_of_get_data_lanes_count_ep(dp->dev->of_node, 1, 0, 1, + video_info->max_lane_count); + if (num_lanes < 0) + return -EINVAL; + + endpoint =3D of_graph_get_endpoint_by_regs(dp->dev->of_node, 1, -1); + if (!endpoint) + return -EINVAL; + + ret =3D of_property_read_u32_array(endpoint, "data-lanes", tmp, num_lanes= ); + of_node_put(endpoint); + if (ret) + return -EINVAL; + + for (i =3D 0; i < num_lanes; i++) { + if (tmp[i] >=3D LANE_COUNT4) { + dev_dbg(dp->dev, "data-lanes[%d] =3D %u is out of range\n", i, tmp[i]); + return -EINVAL; + } + + if (used[tmp[i]]) { + dev_dbg(dp->dev, "data-lanes[%d] =3D %u is duplicate\n", i, tmp[i]); + return -EINVAL; + } + + used[tmp[i]] =3D true; + map[i] =3D tmp[i]; + } + + for (i =3D 0; i < LANE_COUNT4 && num_lanes < LANE_COUNT4; i++) { + if (!used[i]) + map[num_lanes++] =3D i; + } + + dev_dbg(dp->dev, "Using parsed lane map: <%u %u %u %u>\n", map[0], map[1]= , map[2], map[3]); + + memcpy(video_info->lane_map, map, sizeof(map)); + + return 0; +} + static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp) { struct device_node *dp_node =3D dp->dev->of_node; @@ -1266,6 +1319,9 @@ static int analogix_dp_dt_parse_pdata(struct analogix= _dp_device *dp) break; } =20 + if (analogix_dp_dt_parse_lanes_map(dp)) + dev_dbg(dp->dev, "No valid data-lanes found, using default lane map\n"); + return 0; } =20 diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/g= pu/drm/bridge/analogix/analogix_dp_core.h index 94348c4e3623..a75d0fb8f980 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h @@ -137,6 +137,8 @@ struct video_info { =20 int max_link_rate; enum link_lane_count_type max_lane_count; + + u32 lane_map[LANE_COUNT4]; }; =20 struct link_train { @@ -175,7 +177,7 @@ struct analogix_dp_device { /* analogix_dp_reg.c */ void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool ena= ble); void analogix_dp_stop_video(struct analogix_dp_device *dp); -void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable); +void analogix_dp_lane_mapping(struct analogix_dp_device *dp); void analogix_dp_init_analog_param(struct analogix_dp_device *dp); void analogix_dp_init_interrupt(struct analogix_dp_device *dp); void analogix_dp_reset(struct analogix_dp_device *dp); diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gp= u/drm/bridge/analogix/analogix_dp_reg.c index ea8401293a23..c1344a3f013a 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c @@ -48,16 +48,15 @@ void analogix_dp_stop_video(struct analogix_dp_device *= dp) writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); } =20 -void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable) +void analogix_dp_lane_mapping(struct analogix_dp_device *dp) { + u32 *lane_map =3D dp->video_info.lane_map; u32 reg; =20 - if (enable) - reg =3D LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 | - LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3; - else - reg =3D LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | - LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0; + reg =3D lane_map[0] << LANE0_MAP_SHIFT; + reg |=3D lane_map[1] << LANE1_MAP_SHIFT; + reg |=3D lane_map[2] << LANE2_MAP_SHIFT; + reg |=3D lane_map[3] << LANE3_MAP_SHIFT; =20 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP); } @@ -140,7 +139,7 @@ void analogix_dp_reset(struct analogix_dp_device *dp) =20 usleep_range(20, 30); =20 - analogix_dp_lane_swap(dp, 0); + analogix_dp_lane_mapping(dp); =20 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gp= u/drm/bridge/analogix/analogix_dp_reg.h index 12735139046c..ac914e37089b 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h @@ -209,6 +209,10 @@ #define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0) #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) +#define LANE3_MAP_SHIFT (6) +#define LANE2_MAP_SHIFT (4) +#define LANE1_MAP_SHIFT (2) +#define LANE0_MAP_SHIFT (0) =20 /* ANALOGIX_DP_ANALOG_CTL_1 */ #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) --=20 2.34.1