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Thu, 21 May 2026 04:11:17 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Simon Horman" , Adithya Jayachandran , Jiri Pirko , Moshe Shemesh , Or Har-Toov , Shay Drori , Parav Pandit , Daniel Jurgens , Kees Cook , Cosmin Ratiu , Carolina Jubran , , , , Gal Pressman Subject: [PATCH net-next 01/12] net/mlx5: Add satellite PF vport support Date: Thu, 21 May 2026 14:08:32 +0300 Message-ID: <20260521110843.367329-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260521110843.367329-1-tariqt@nvidia.com> References: <20260521110843.367329-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00022572:EE_|DS0PR12MB7584:EE_ X-MS-Office365-Filtering-Correlation-Id: aae04c9b-9123-47a2-24a9-08deb729bba1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|36860700016|1800799024|3023799007|56012099003|18002099003|22082099003|11063799006|6133799003; X-Microsoft-Antispam-Message-Info: b/e4aC5E0k6ZZxpNooZlY8mxJTl9Z4JhgyzTU5RNFwdgJMktrSc8QRqBQMyxD2s/wD/s1sylvQDqwIe2xnLFAdAKocgSgIxdQ+uM13fAUUCI9UX1Au+P+CGFDKls2iy4+OD0OCjvcP2IngBDk+wxXOB2eBR3vA481Xyk8VHXPGWWkB4JS3TSTTUDeXkYN0MLWA04fXsDKkU2+gdOzzqt4dfcFw5b/WTuuRT55UR474pqa1MzNMxcjkK4LiOhnP98x7hhAclnXXXpuBZiZ/zR/G4gTLpb07TIwnJ1tlDxiLZ5LLPf4gTXOSfoYR1eRLRNstdb+AYxW4lV2gDxiuPFllnJBdM0qVXLcvNipPZ4vJ0CPyT2ETOkbl12ZAgcqBE7wkSsB/KvqIDfLNfjqDOHzTTuVzRvnjEgCb/szIv+lEZAY9Y/W7UQs6QX+2H1DTU8Xtm7bt1XsMj0nxvxkjKwJQy08X2EbCotIy1H4PHyjxwPQVGj3/dE0ILqa4e77/NB/EpCRPBWwTHKPzDbsMfnoTpLZGVIxw5Hct65Hkjg573EVCx+m/wk9DgfLP4S5NsyqjV0kFa1VyCI0YeDK9kfo/IuSfE+zO6AAQuN7+bFkhkVY8SBPY1wvAXZULZ1q0zMxvhNwcjQku/nyiN2Vy7pqDGkvXR+zLsr8XIGe1rQIMk2MUQeQMHi8xnCblqHXVQmUdHXbhYgLPOXxZsiXljM2E2CTSH9blx8rjLTRR33n3A= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(7416014)(36860700016)(1800799024)(3023799007)(56012099003)(18002099003)(22082099003)(11063799006)(6133799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +Zgip+mCkB/hqil3PaQJEhsgPqK4m/AnvQbxq6ohx3K3xJC7F5eQnu9FS5aCgdHK9FgwKmNxFmrLHI5TcuXop/qU+txsc89S5/n1Jc8uqYOLDE5UML8rcbOvI3/rgLe/17044RJ05eEaYfw0sebVUUwJKDPfaw450d01N5TceC7ygARZTFlovSX7TkCq0MRiisS3hoe2/F3OvanZR1UOlPvJcEvi8UYGX7TRAs+Hf4W/Mpl7nx7A0Wd9HganMZ7xYDJIHqepstr2szFv4hnX1YsmWT1lMEEJruWXwicp2frUJcQzFgGOywWOrgSnGMCDAejevNt+KXM+g5HeXk7Fw5XFq9dtvp2O32JCxvAVKX0G1TVZ/igu6Q3P1BIu1EMejgU8xuTS9KGtXIx44EgaMqdWkRssDUakm7rJwlGff9I7V01CofJ/LYur0IO4ohO1 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2026 11:11:40.0375 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aae04c9b-9123-47a2-24a9-08deb729bba1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022572.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7584 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Discover satellite PFs from query_esw_functions output and allocate eswitch vports for them. For each satellite PF, create a vport via the CREATE_ESW_VPORT command using its vhca_id and allocate it in the eswitch vport table. When enabling switchdev mode, the ECPF acting as the eswitch manager activates each satellite PF with enable_hca, loads its vport and adds a representor. Since satellite PF devlink ports are registered in a later patch, guard mlx5_esw_offloads_devlink_port() against vports with no devlink port to avoid NULL dereference during representor attach. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/esw/adj_vport.c | 6 +- .../mellanox/mlx5/core/esw/devlink_port.c | 7 +- .../net/ethernet/mellanox/mlx5/core/eswitch.c | 159 +++++++++++++++++- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 10 ++ 4 files changed, 171 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/adj_vport.c b/driv= ers/net/ethernet/mellanox/mlx5/core/esw/adj_vport.c index 250af09b5af2..ca249b50f830 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/adj_vport.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/adj_vport.c @@ -23,7 +23,7 @@ int mlx5_esw_adj_vport_modify(struct mlx5_core_dev *dev, = u16 vport, return mlx5_cmd_exec_in(dev, modify_vport_state, in); } =20 -static void mlx5_esw_destroy_esw_vport(struct mlx5_core_dev *dev, u16 vpor= t) +void mlx5_esw_destroy_esw_vport(struct mlx5_core_dev *dev, u16 vport) { u32 in[MLX5_ST_SZ_DW(destroy_esw_vport_in)] =3D {}; =20 @@ -34,8 +34,8 @@ static void mlx5_esw_destroy_esw_vport(struct mlx5_core_d= ev *dev, u16 vport) mlx5_cmd_exec_in(dev, destroy_esw_vport, in); } =20 -static int mlx5_esw_create_esw_vport(struct mlx5_core_dev *dev, u16 vhca_i= d, - u16 *vport_num) +int mlx5_esw_create_esw_vport(struct mlx5_core_dev *dev, u16 vhca_id, + u16 *vport_num) { u32 out[MLX5_ST_SZ_DW(create_esw_vport_out)] =3D {}; u32 in[MLX5_ST_SZ_DW(create_esw_vport_in)] =3D {}; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c b/d= rivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c index 8a79764345e7..0730f0c883fe 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c @@ -253,5 +253,10 @@ struct devlink_port *mlx5_esw_offloads_devlink_port(st= ruct mlx5_eswitch *esw, u1 struct mlx5_vport *vport; =20 vport =3D mlx5_eswitch_get_vport(esw, vport_num); - return IS_ERR(vport) ? ERR_CAST(vport) : &vport->dl_port->dl_port; + if (IS_ERR(vport)) + return ERR_CAST(vport); + if (!vport->dl_port) + return ERR_PTR(-ENODEV); + + return &vport->dl_port->dl_port; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index 206911817a04..e75925a99852 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -1517,8 +1517,11 @@ int mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch *esw, enum mlx5_eswitch_vport_event enabled_events) { + struct mlx5_esw_functions *esw_funcs =3D &esw->esw_funcs; bool pf_needed; + u16 vport_num; int ret; + int i; =20 pf_needed =3D mlx5_core_is_ecpf_esw_manager(esw->dev) || esw->mode =3D=3D MLX5_ESWITCH_LEGACY; @@ -1548,14 +1551,14 @@ mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitc= h *esw, /* Enable ECVF vports */ if (mlx5_core_ec_sriov_enabled(esw->dev)) { ret =3D mlx5_eswitch_load_ec_vf_vports(esw, - esw->esw_funcs.num_ec_vfs, + esw_funcs->num_ec_vfs, enabled_events); if (ret) goto ec_vf_err; } =20 /* Enable VF vports */ - ret =3D mlx5_eswitch_load_vf_vports(esw, esw->esw_funcs.num_vfs, + ret =3D mlx5_eswitch_load_vf_vports(esw, esw_funcs->num_vfs, enabled_events); if (ret) goto vf_err; @@ -1565,13 +1568,36 @@ mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitc= h *esw, if (ret) goto unload_vf_vports; =20 + /* Enable satellite PF vports */ + for (i =3D 0; i < esw_funcs->num_spfs; i++) { + vport_num =3D esw_funcs->spfs[i].vport_num; + + ret =3D mlx5_eswitch_load_pf_vf_vport(esw, vport_num, + enabled_events); + if (ret) + goto spf_err; + + ret =3D mlx5_esw_pf_enable_hca(esw->dev, vport_num); + if (ret) { + mlx5_eswitch_unload_pf_vf_vport(esw, vport_num); + goto spf_err; + } + } + return 0; =20 +spf_err: + while (i-- > 0) { + vport_num =3D esw_funcs->spfs[i].vport_num; + mlx5_esw_pf_disable_hca(esw->dev, vport_num); + mlx5_eswitch_unload_pf_vf_vport(esw, vport_num); + } + mlx5_eswitch_unload_adj_vf_vports(esw); unload_vf_vports: - mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs); + mlx5_eswitch_unload_vf_vports(esw, esw_funcs->num_vfs); vf_err: if (mlx5_core_ec_sriov_enabled(esw->dev)) - mlx5_eswitch_unload_ec_vf_vports(esw, esw->esw_funcs.num_ec_vfs); + mlx5_eswitch_unload_ec_vf_vports(esw, esw_funcs->num_ec_vfs); ec_vf_err: if (mlx5_ecpf_vport_exists(esw->dev)) mlx5_eswitch_unload_pf_vf_vport(esw, MLX5_VPORT_ECPF); @@ -1589,13 +1615,22 @@ mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitc= h *esw, */ void mlx5_eswitch_disable_pf_vf_vports(struct mlx5_eswitch *esw) { + struct mlx5_esw_functions *esw_funcs =3D &esw->esw_funcs; + u16 vport_num; + int i; + + for (i =3D 0; i < esw_funcs->num_spfs; i++) { + vport_num =3D esw_funcs->spfs[i].vport_num; + mlx5_esw_pf_disable_hca(esw->dev, vport_num); + mlx5_eswitch_unload_pf_vf_vport(esw, vport_num); + } + mlx5_eswitch_unload_adj_vf_vports(esw); =20 - mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs); + mlx5_eswitch_unload_vf_vports(esw, esw_funcs->num_vfs); =20 if (mlx5_core_ec_sriov_enabled(esw->dev)) - mlx5_eswitch_unload_ec_vf_vports(esw, - esw->esw_funcs.num_ec_vfs); + mlx5_eswitch_unload_ec_vf_vports(esw, esw_funcs->num_ec_vfs); =20 if (mlx5_ecpf_vport_exists(esw->dev)) { mlx5_eswitch_unload_pf_vf_vport(esw, MLX5_VPORT_ECPF); @@ -2065,11 +2100,105 @@ void mlx5_esw_vport_free(struct mlx5_eswitch *esw,= struct mlx5_vport *vport) kfree(vport); } =20 +static void mlx5_esw_spfs_cleanup(struct mlx5_eswitch *esw) +{ + struct mlx5_esw_functions *esw_funcs =3D &esw->esw_funcs; + int i; + + for (i =3D 0; i < esw_funcs->num_spfs; i++) + mlx5_esw_destroy_esw_vport(esw->dev, + esw_funcs->spfs[i].vport_num); + + kfree(esw_funcs->spfs); + esw_funcs->spfs =3D NULL; + esw_funcs->num_spfs =3D 0; +} + +static int mlx5_esw_spfs_init(struct mlx5_eswitch *esw) +{ + struct mlx5_esw_functions *esw_funcs =3D &esw->esw_funcs; + struct mlx5_core_dev *dev =3D esw->dev; + int num_entries; + const u8 *entry; + const u32 *out; + int err =3D 0; + int pf_type; + u16 vhca_id; + int i; + + if (!MLX5_CAP_GEN(dev, query_host_net_function_v1)) + return 0; + + out =3D mlx5_esw_query_functions(dev); + if (IS_ERR(out)) + return PTR_ERR(out); + + num_entries =3D MLX5_GET(query_esw_functions_out, out, net_function_num); + if (!num_entries) + goto out_free; + + esw_funcs->spfs =3D kcalloc(num_entries, sizeof(*esw_funcs->spfs), + GFP_KERNEL); + if (!esw_funcs->spfs) { + err =3D -ENOMEM; + goto out_free; + } + + entry =3D MLX5_ADDR_OF(query_esw_functions_out, out, net_function_params); + + for (i =3D 0; i < num_entries; i++) { + u16 vport_num; + + pf_type =3D MLX5_GET(network_function_params, entry, pci_pf_type); + if (pf_type !=3D MLX5_PCI_PF_TYPE_SATELLITE_PF) { + entry +=3D MLX5_UN_SZ_BYTES(net_function_params); + continue; + } + + if (!MLX5_GET(network_function_params, entry, + esw_vport_manual)) { + esw_warn(dev, "Satellite PF without esw_vport_manual is not supported\n= "); + entry +=3D MLX5_UN_SZ_BYTES(net_function_params); + continue; + } + + vhca_id =3D MLX5_GET(network_function_params, entry, vhca_id); + + err =3D mlx5_esw_create_esw_vport(dev, vhca_id, &vport_num); + if (err) { + esw_warn(dev, "Failed to create satellite PF vport for vhca_id 0x%x, er= r %d\n", + vhca_id, err); + goto spfs_cleanup; + } + + esw_funcs->spfs[esw_funcs->num_spfs].vport_num =3D vport_num; + esw_funcs->spfs[esw_funcs->num_spfs].vhca_id =3D vhca_id; + esw_funcs->num_spfs++; + + entry +=3D MLX5_UN_SZ_BYTES(net_function_params); + } + + if (!esw_funcs->num_spfs) { + kfree(esw_funcs->spfs); + esw_funcs->spfs =3D NULL; + } + + kvfree(out); + return 0; + +spfs_cleanup: + mlx5_esw_spfs_cleanup(esw); +out_free: + kvfree(out); + return err; +} + static void mlx5_esw_vports_cleanup(struct mlx5_eswitch *esw) { struct mlx5_vport *vport; unsigned long i; =20 + mlx5_esw_spfs_cleanup(esw); mlx5_esw_for_each_vport(esw, i, vport) mlx5_esw_vport_free(esw, vport); xa_destroy(&esw->vports); @@ -2123,6 +2252,22 @@ static int mlx5_esw_vports_init(struct mlx5_eswitch = *esw) idx++; } =20 + err =3D mlx5_esw_spfs_init(esw); + if (err) + goto err; + + for (i =3D 0; i < esw->esw_funcs.num_spfs; i++) { + struct mlx5_vport *vport; + u16 vport_num; + + vport_num =3D esw->esw_funcs.spfs[i].vport_num; + err =3D mlx5_esw_vport_alloc(esw, idx++, vport_num); + if (err) + goto err; + vport =3D mlx5_eswitch_get_vport(esw, vport_num); + vport->vhca_id =3D esw->esw_funcs.spfs[i].vhca_id; + } + if (mlx5_core_ec_sriov_enabled(esw->dev)) { int ec_vf_base_num =3D mlx5_core_ec_vf_vport_base(dev); =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index a5f832ed2251..19419799a26d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -349,11 +349,18 @@ struct mlx5_host_work { void (*func)(struct mlx5_eswitch *esw); }; =20 +struct mlx5_esw_spf { + u16 vport_num; + u16 vhca_id; +}; + struct mlx5_esw_functions { struct mlx5_nb nb; bool host_funcs_disabled; u16 num_vfs; u16 num_ec_vfs; + struct mlx5_esw_spf *spfs; + int num_spfs; }; =20 enum { @@ -666,6 +673,9 @@ void mlx5_esw_adjacent_vhcas_setup(struct mlx5_eswitch = *esw); void mlx5_esw_adjacent_vhcas_cleanup(struct mlx5_eswitch *esw); int mlx5_esw_adj_vport_modify(struct mlx5_core_dev *dev, u16 vport, bool connect); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Simon Horman" , Adithya Jayachandran , Jiri Pirko , Moshe Shemesh , Or Har-Toov , Shay Drori , Parav Pandit , Daniel Jurgens , Kees Cook , Cosmin Ratiu , Carolina Jubran , , , , Gal Pressman Subject: [PATCH net-next 02/12] net/mlx5: Introduce generic helper for PF SFs info Date: Thu, 21 May 2026 14:08:33 +0300 Message-ID: <20260521110843.367329-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260521110843.367329-1-tariqt@nvidia.com> References: <20260521110843.367329-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD78:EE_|IA0PR12MB8745:EE_ X-MS-Office365-Filtering-Correlation-Id: 3b3403fc-9d11-4d11-0b52-08deb729bec2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|7416014|376014|22082099003|18002099003|56012099003|11063799006|6133799003; X-Microsoft-Antispam-Message-Info: wQpVNgmpUAI4KopYMzL8ABtHOXmal5lOOb2tkn70i9/QaaQTSGGz0KId1pn1J2YJ6u3qajGr25FL5UXysQAjpk1LNiyP1WMNcAWV43JZygCQRGYm8jGy8HoHmj2CxH9OFDeq+gC/3THqe+G5lpei223OyQYZrXTHotgIA+tqcqMNBaUON4LrFbvqt8knBu6BH66952K3E3kbEuCrDVnkt4aQTxS2KbqxaVpdM+j1R7iU7QBqJ74yPxx43BHypv9Zz/IEicuO2ZqZyzch5c9MhNST3vt8L9lx4ddWaJ2lOklMgiIOLaZbiuszhMw4C6mZ5sj6notSJkwAtruEooMYcuZtnz/AqibUQzqmy5tVj8EQ/rG6Xi+9tF/rTRNiNIk1cMJeKZYskDm9q8vIY5g4yTKKM7xllPt0XB2rz/TOnv5y2an3lE2GNj+r3fvDr5YJpi3wMXcRTfZYzUZkqC0Gkn497ZJU5n6VKaYM65RvNhT72E9AdwSM9D2/RB/7Gh9ICu02ediigmsFDi6i/SHDT5k1tn08jivY4uagCLHtS2g6W2Nk9DjDw9db8NmCk/aGOyht4I2Q1OEig55hYjqkaPeBQImP/4ogikKgXhExrJ466xs79bfJMIPynqzPQZK+UmIQsppf5xJ6iUsmYjIKY/Hx4SNzPl8r8qAPCcKtbKZtCnMCUfQ4/vfbo087Y/s09d+abto9pE5EgkuCZYhhRyO0ymP8lfr9WfWY6Yf7hKc= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(7416014)(376014)(22082099003)(18002099003)(56012099003)(11063799006)(6133799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: s26AMDPCKX6SDILXkq+Va+sRmvvHq25FQUH7DVJRNrFjPUbhJZPGrTgl18yqw4siEih/RrR3BK2xNDVPgx+QKKhfyJpnJz3WHtqkOVWs2gkGk4bc7qSXwHkbF0cqGjchdwdDXZjnAOLXtfDWKPy+og7wvRCx74UsYs1XdNXaI+n/FBIEIoSJA0a6kSb03gUZqmyP2VOcXrH73GxaU4/YGEpikzNMDA0zdIZL5pVJWgSBB9D7vJn3OH3QUfFLdA89Mzo+WKq18GAJuzm7/O6MYdqtcAXzJzf5RZURrLXWTms6zvHkSJvGftuOvpPUdJUKMHuENfdYwqyIVGH+aESFxdim3GW91urAF+h6w4LSDdQHfc+0i5ADVVWKSW3lbBLOw8U22LBI2RT7kKLIIN5Lu+u7AYigazCJ6cbh3d7ZZ80ND5soDy0Vd2GP4Ey4MLnc X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2026 11:11:45.3505 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3b3403fc-9d11-4d11-0b52-08deb729bec2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD78.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8745 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Introduce mlx5_esw_sf_max_pf_functions() that queries a PF's max_num_sf and sf_base_id using mlx5_vport_get_other_func_general_cap(), which supports both function_id and vhca_id based addressing. Refactor mlx5_esw_sf_max_hpf_functions() into a thin wrapper that adds the host PF precondition checks and calls the new generic helper. Remove mlx5_query_hca_cap_host_pf() as it is not used anymore. This prepares for querying SFs info of Satellite PFs. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/eswitch.c | 38 +++++++++---------- 1 file changed, 17 insertions(+), 21 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index e75925a99852..815538ba754f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -2023,37 +2023,20 @@ void mlx5_eswitch_disable(struct mlx5_eswitch *esw) mlx5_lag_enable_change(esw->dev); } =20 -static int mlx5_query_hca_cap_host_pf(struct mlx5_core_dev *dev, void *out) -{ - u16 opmod =3D (MLX5_CAP_GENERAL << 1) | (HCA_CAP_OPMOD_GET_MAX & 0x01); - u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)] =3D {}; - - MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); - MLX5_SET(query_hca_cap_in, in, op_mod, opmod); - MLX5_SET(query_hca_cap_in, in, function_id, MLX5_VPORT_HOST_PF); - MLX5_SET(query_hca_cap_in, in, other_function, true); - return mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); -} - -int mlx5_esw_sf_max_hpf_functions(struct mlx5_core_dev *dev, u16 *max_sfs,= u16 *sf_base_id) - +static int mlx5_esw_sf_max_pf_functions(struct mlx5_core_dev *dev, + u16 vport_num, u16 *max_sfs, + u16 *sf_base_id) { int query_out_sz =3D MLX5_ST_SZ_BYTES(query_hca_cap_out); void *query_ctx; void *hca_caps; int err; =20 - if (!mlx5_core_is_ecpf(dev) || - !mlx5_esw_host_functions_enabled(dev)) { - *max_sfs =3D 0; - return 0; - } - query_ctx =3D kzalloc(query_out_sz, GFP_KERNEL); if (!query_ctx) return -ENOMEM; =20 - err =3D mlx5_query_hca_cap_host_pf(dev, query_ctx); + err =3D mlx5_vport_get_other_func_general_cap(dev, vport_num, query_ctx); if (err) goto out_free; =20 @@ -2066,6 +2049,19 @@ int mlx5_esw_sf_max_hpf_functions(struct mlx5_core_d= ev *dev, u16 *max_sfs, u16 * return err; } =20 +int mlx5_esw_sf_max_hpf_functions(struct mlx5_core_dev *dev, u16 *max_sfs, + u16 *sf_base_id) +{ + if (!mlx5_core_is_ecpf(dev) || + !mlx5_esw_host_functions_enabled(dev)) { + *max_sfs =3D 0; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Simon Horman" , Adithya Jayachandran , Jiri Pirko , Moshe Shemesh , Or Har-Toov , Shay Drori , Parav Pandit , Daniel Jurgens , Kees Cook , Cosmin Ratiu , Carolina Jubran , , , , Gal Pressman Subject: [PATCH net-next 03/12] net/mlx5: Initialize host PF host number earlier Date: Thu, 21 May 2026 14:08:34 +0300 Message-ID: <20260521110843.367329-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260521110843.367329-1-tariqt@nvidia.com> References: <20260521110843.367329-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD74:EE_|LV8PR12MB9111:EE_ X-MS-Office365-Filtering-Correlation-Id: 70368ab4-96d1-4e71-bb64-08deb729c39b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|7416014|36860700016|56012099003|22082099003|18002099003|11063799006|6133799003; X-Microsoft-Antispam-Message-Info: oHYENmYdtJw7W6jHjVa8dP4Jl7g8StYZBmPvQ1qXX2CWInsmiXR0CRns3OCrmrQ4wVLyd0i58LOZYVOF/bunJYvqCt7DIslfDFsUb5yYXSUzIBHzMBs9AZMntQzxhiLmKHx9p3TxOPZJyC/uEQ6rhdwhmvsJHHEw1yS8uTibiz2yWoLjZHrg0Yi6LbjzSmWXqIMIanuqjzdTJr1tl8bzHIkS0ybTGwfYjcvcPC0yidVaa7D6lEtJdG2H4dNtAkkXvMwjWGqwHBjRsKbswNYxAdnFtyL6nUmwwRditAThkk1SRIxE785SQQGzd5aJ7ujeiFYM8o6I9fMJ99/JIEx7evZ/mwMoq06PMI6WcHmQjHaQR5ap1a3E7HXXBRNsGbA0nOn2WlyKtYiL2kw2aJNNyqPDnzM/Sf6Nv3y/4dHdJ4xwJqjapsG8mRdGLLaMXkMQLECPQ8EkowMPoAL1bmLW+4r1AVWo7fG+/wB6K6jr5y7HKm7mPRw3PK7Jn+o5zrTEhTVoOqYF5pq0hieV/fkrjbhVmuvHuQAMjmkhRInGpz4ZA0S8soa95yoCKVJ10UPem+59Zt2UUh68yp0QAP6ff53oqhREcZyrhp0SvTtkh9ysaNdbRp8wF5ee9kx/CMc4ahwH4HpcWsITP1R0N2I2UIbaVkoGi/Ci7yu/Naa3vuaj1Gy5V+sUR8YUwugX+p4PMxCsXNhIzv6ZbJzTDyn0QyXCr3J6VHUizRa5bLEmaTI= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(7416014)(36860700016)(56012099003)(22082099003)(18002099003)(11063799006)(6133799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: EMwaFTP4ylj4ktp6ExvTH0Xm10Fdiq+zIgIr6UaIUQdPvJJyK1Nb4dQABVHADE+FtbrU1Hrd27ZXWF5asl52hYa8814VIx6leUd1HVRZJeiaBNCVLZPkZ8wxEFsMyPn3c2H+NhvlLj8kp0kYBBELtMbjyEjH1oy6u06jyRxLMHsOmuUzYmkB367azn5IXwHGFGYVKRLHLoFjyhHFvzhcR8h1FCzcYlwTXUgX9/HgEbRQ78FvOxe4i1+O7hFrtMcdwhnGEv/U/YpKjlRXvL/NVFRA7M6f7NOJoqEEfvXDlvgorl0hHloWC1OArofBTTwvoaQipSdm5FL6N4iXoch2fIfqToMRH+GX/9/MuDMOf/bDFRRXFXT6AvO6O5GcjJLV1BrVEgHqI1oCtuALiOoT9ncMcFUeOj1BCtVQznLPEC/586qZwBo4LKuOqvHbrVJA X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2026 11:11:53.4809 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 70368ab4-96d1-4e71-bb64-08deb729c39b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD74.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9111 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Move host_number from esw->offloads to esw->esw_funcs as hpf_host_number and initialize it during vports_init instead of offloads_enable. This makes the host PF host number available earlier in the initialization sequence, which is required for upcoming SF hardware table support for satellite PFs. Add a mlx5_esw_get_hpf_host_number() accessor to retrieve the stored host number. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/esw/devlink_port.c | 2 +- .../net/ethernet/mellanox/mlx5/core/eswitch.c | 33 +++++++++++++++++++ .../net/ethernet/mellanox/mlx5/core/eswitch.h | 4 ++- .../mellanox/mlx5/core/eswitch_offloads.c | 25 +------------- 4 files changed, 38 insertions(+), 26 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c b/d= rivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c index 0730f0c883fe..e723f05cd4d3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c @@ -34,7 +34,7 @@ static void mlx5_esw_offloads_pf_vf_devlink_port_attrs_se= t(struct mlx5_eswitch * pfnum =3D PCI_FUNC(dev->pdev->devfn); external =3D mlx5_core_is_ecpf_esw_manager(dev); if (external) - controller_num =3D dev->priv.eswitch->offloads.host_number + 1; + controller_num =3D mlx5_esw_get_hpf_host_number(dev) + 1; =20 if (vport_num =3D=3D MLX5_VPORT_HOST_PF) { memcpy(dl_port->attrs.switch_id.id, ppid.id, ppid.id_len); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index 815538ba754f..f9085b8dc20b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -2062,6 +2062,35 @@ int mlx5_esw_sf_max_hpf_functions(struct mlx5_core_d= ev *dev, u16 *max_sfs, sf_base_id); } =20 +u16 mlx5_esw_get_hpf_host_number(struct mlx5_core_dev *dev) +{ + struct mlx5_eswitch *esw =3D dev->priv.eswitch; + + if (!mlx5_esw_allowed(esw)) + return 0; + + return esw->esw_funcs.hpf_host_number; +} + +static int mlx5_esw_hpf_host_number_init(struct mlx5_eswitch *esw) +{ + struct mlx5_esw_pf_info host_pf_info; + const u32 *query_host_out; + + if (!mlx5_core_is_ecpf_esw_manager(esw->dev)) + return 0; + + query_host_out =3D mlx5_esw_query_functions(esw->dev); + if (IS_ERR(query_host_out)) + return PTR_ERR(query_host_out); + + /* Mark non local controller with non zero controller number. */ + host_pf_info =3D mlx5_esw_get_host_pf_info(esw->dev, query_host_out); + esw->esw_funcs.hpf_host_number =3D host_pf_info.host_number; + kvfree(query_host_out); + return 0; +} + int mlx5_esw_vport_alloc(struct mlx5_eswitch *esw, int index, u16 vport_nu= m) { struct mlx5_vport *vport; @@ -2211,6 +2240,10 @@ static int mlx5_esw_vports_init(struct mlx5_eswitch = *esw) =20 xa_init(&esw->vports); =20 + err =3D mlx5_esw_hpf_host_number_init(esw); + if (err) + goto err; + if (mlx5_esw_host_functions_enabled(dev)) { err =3D mlx5_esw_vport_alloc(esw, idx, MLX5_VPORT_HOST_PF); if (err) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index 19419799a26d..abdb4c460b06 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -332,7 +332,6 @@ struct mlx5_esw_offload { u64 num_block_mode; enum devlink_eswitch_encap_mode encap; struct ida vport_metadata_ida; - unsigned int host_number; /* ECPF supports one external host */ }; =20 /* E-Switch MC FDB table hash node */ @@ -359,6 +358,7 @@ struct mlx5_esw_functions { bool host_funcs_disabled; u16 num_vfs; u16 num_ec_vfs; + u16 hpf_host_number; struct mlx5_esw_spf *spfs; int num_spfs; }; @@ -879,6 +879,8 @@ struct devlink_port *mlx5_esw_offloads_devlink_port(str= uct mlx5_eswitch *esw, u1 =20 int mlx5_esw_sf_max_hpf_functions(struct mlx5_core_dev *dev, u16 *max_sfs,= u16 *sf_base_id); =20 +u16 mlx5_esw_get_hpf_host_number(struct mlx5_core_dev *dev); + int mlx5_esw_vport_vhca_id_map(struct mlx5_eswitch *esw, struct mlx5_vport *vport); void mlx5_esw_vport_vhca_id_unmap(struct mlx5_eswitch *esw, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index b06b10d443bd..f17db51abe2d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -3819,25 +3819,6 @@ int mlx5_esw_funcs_changed_handler(struct notifier_b= lock *nb, return NOTIFY_OK; } =20 -static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw) -{ - struct mlx5_esw_pf_info host_pf_info; - const u32 *query_host_out; - - if (!mlx5_core_is_ecpf_esw_manager(esw->dev)) - return 0; - - query_host_out =3D mlx5_esw_query_functions(esw->dev); - if (IS_ERR(query_host_out)) - return PTR_ERR(query_host_out); - - /* Mark non local controller with non zero controller number. */ - host_pf_info =3D mlx5_esw_get_host_pf_info(esw->dev, query_host_out); - esw->offloads.host_number =3D host_pf_info.host_number; - kvfree(query_host_out); - return 0; -} - bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u3= 2 controller) { /* Local controller is always valid */ @@ -3848,7 +3829,7 @@ bool mlx5_esw_offloads_controller_valid(const struct = mlx5_eswitch *esw, u32 cont return false; =20 /* External host number starts with zero in device */ - return (controller =3D=3D esw->offloads.host_number + 1); + return (controller =3D=3D mlx5_esw_get_hpf_host_number(esw->dev) + 1); } =20 int esw_offloads_enable(struct mlx5_eswitch *esw) @@ -3867,10 +3848,6 @@ int esw_offloads_enable(struct mlx5_eswitch *esw) if (err) goto err_roce; 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Thu, 21 May 2026 04:11:36 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Simon Horman" , Adithya Jayachandran , Jiri Pirko , Moshe Shemesh , Or Har-Toov , Shay Drori , Parav Pandit , Daniel Jurgens , Kees Cook , Cosmin Ratiu , Carolina Jubran , , , , Gal Pressman Subject: [PATCH net-next 04/12] net/mlx5: Initialize satellite PF SF vports Date: Thu, 21 May 2026 14:08:35 +0300 Message-ID: <20260521110843.367329-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260521110843.367329-1-tariqt@nvidia.com> References: <20260521110843.367329-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00022573:EE_|MW4PR12MB5643:EE_ X-MS-Office365-Filtering-Correlation-Id: 71ef9c0d-2f12-4c23-ef66-08deb729c83b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|82310400026|376014|7416014|18002099003|56012099003|11063799006|22082099003|6133799003; X-Microsoft-Antispam-Message-Info: LuwahFuhCM72FRd/rWS5omvGNXF0qecDPGuak9FHpuaoTkI9h7pYcabT0LciRMI/HjEM9p4K3GviCmNdiMi92mnB5QyNmDvqfJiNU9xSZNG7rN7pqGzRXMUEyRmxOblPfSEKQAi1PbHoh2QoB9eF81JnhMdcB8RxwYeIVuBKnnGu1dkFeCGPg26boir/QF4I1oIjTc7A2x+L5+mSWTrSLLj0uuVKmx1bE12sHS5IoWbuNZDGN8lgBQhLZGQM7i4/xGUzpuz1vIaPjYmD7UUwc+hZ/KCl7snod/cG16WwanNqha+HJip4NFIna78HOLTESENbHhEd4yXR/kVH3YFpka7k29ZMMVyo35GT9ZLuOZQCkiIVCMStviA5FZKBCb8EnIokr7R5jtAYeEuPqdY0tkcJvz417ujPIqWihWXdII98IZarQibfIre+i3GdxraXOkPaMbTYWKI37/if1AAru/lKqpVRR+TX/JN8NT3t6Ijtn2NYNHeNU9FSMJ11zMouhB+TZAJMhGhflKmndqgxwCf8+uerTrR36+SRqb7y8XCYwe+Xse/Y1uMyVblwQv1RxlA0bh34WVk1p8IPKKZNKiSCikFuzjLZdNCVmnVa2IB6cLyXYxPHPnHgAB92xlVgViUTbHalE954Z50p0Clr6bl7sB3G8xFU3ZMY8gCE1hBp68OyX4RxdLGvuFPm7aowSWY3WhZ8T/xxSmY9O93xqrRZ/BuY0nApzJnb/RqYbA0= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(82310400026)(376014)(7416014)(18002099003)(56012099003)(11063799006)(22082099003)(6133799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: aQoOkk+dVVdW/g4OAoXr1QaHo9x+SzDk0J8FBkApCFMDpD9mFx+uiMj83kGmMX7gGFOQBvTe0CkBipQ2s4UNzrv2W9Yp0Qc8KktL9MpOJKk1BfgAPhWw0sb2+hMKLUEHb92lcBWPnEuvM4y8NaJaV0osXKCLcyYoUx8HlqYCoapeDHeZQgp/ur/PuKiU5wZ0kwHr3HU8s02oh+DbGmleFkmDU/z9zkcCuXnQ1vDQYhjSKyxgvZj3lv6OsIC2j41aJah3RSbO1fZGFanaThuJ5EE+Y5g10oDLOhCeTUcTj4veN0KywTezv1HSVQQ8P9e7Zz0XQtHyqPwaiUMMzM75VbMKwCu7SwN7VepqRW+35SDRTOGPdCyhekAUD6eVb68xpPvVYCykIYbItKIrK1MtIzt7lUFN8IDAdwGhWSdELecYhkrkPkmPxS/9fSrlegjU X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2026 11:12:01.2211 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 71ef9c0d-2f12-4c23-ef66-08deb729c83b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022573.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB5643 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Extend satellite PF (SPF) initialization to allocate SF vports for each SPF. For each discovered SPF, query its SF capabilities, allocate SF vports, and store the host_number for controller identification. Add accessor APIs mlx5_esw_get_num_spfs(), mlx5_esw_spf_get_host_number(), mlx5_esw_sf_max_spf_functions(), and mlx5_esw_has_spf_sfs() for use by the SF hardware table in a subsequent patch. Also extend mlx5_esw_offloads_controller_valid() to accept SPF controllers in addition to the host PF controller. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/eswitch.c | 81 ++++++++++++++++++- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 8 ++ .../mellanox/mlx5/core/eswitch_offloads.c | 13 ++- 3 files changed, 97 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index f9085b8dc20b..42cdb4309258 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -2062,6 +2062,51 @@ int mlx5_esw_sf_max_hpf_functions(struct mlx5_core_d= ev *dev, u16 *max_sfs, sf_base_id); } =20 +int mlx5_esw_sf_max_spf_functions(struct mlx5_core_dev *dev, int spf_idx, + u16 *max_sfs, u16 *sf_base_id) +{ + struct mlx5_eswitch *esw =3D dev->priv.eswitch; + u16 vport_num; + + if (!mlx5_esw_allowed(esw)) { + *max_sfs =3D 0; + return 0; + } + + if (spf_idx >=3D esw->esw_funcs.num_spfs) + return -EINVAL; + + vport_num =3D esw->esw_funcs.spfs[spf_idx].vport_num; + return mlx5_esw_sf_max_pf_functions(dev, vport_num, max_sfs, + sf_base_id); +} + +int mlx5_esw_get_num_spfs(struct mlx5_core_dev *dev) +{ + struct mlx5_eswitch *esw =3D dev->priv.eswitch; + + if (!mlx5_esw_allowed(esw)) + return 0; + + return esw->esw_funcs.num_spfs; +} + +int mlx5_esw_spf_get_host_number(struct mlx5_core_dev *dev, int spf_idx, + u16 *host_number) +{ + struct mlx5_eswitch *esw =3D dev->priv.eswitch; + + if (!mlx5_esw_allowed(esw)) + return -EPERM; + + if (spf_idx >=3D esw->esw_funcs.num_spfs) + return -EINVAL; + + *host_number =3D esw->esw_funcs.spfs[spf_idx].host_number; + + return 0; +} + u16 mlx5_esw_get_hpf_host_number(struct mlx5_core_dev *dev) { struct mlx5_eswitch *esw =3D dev->priv.eswitch; @@ -2072,6 +2117,16 @@ u16 mlx5_esw_get_hpf_host_number(struct mlx5_core_de= v *dev) return esw->esw_funcs.hpf_host_number; } =20 +bool mlx5_esw_has_spf_sfs(struct mlx5_core_dev *dev) +{ + struct mlx5_eswitch *esw =3D dev->priv.eswitch; + + if (!mlx5_esw_allowed(esw)) + return false; + + return esw->esw_funcs.has_spf_sfs; +} + static int mlx5_esw_hpf_host_number_init(struct mlx5_eswitch *esw) { struct mlx5_esw_pf_info host_pf_info; @@ -2198,6 +2253,8 @@ static int mlx5_esw_spfs_init(struct mlx5_eswitch *es= w) =20 esw_funcs->spfs[esw_funcs->num_spfs].vport_num =3D vport_num; esw_funcs->spfs[esw_funcs->num_spfs].vhca_id =3D vhca_id; + esw_funcs->spfs[esw_funcs->num_spfs].host_number =3D + MLX5_GET(network_function_params, entry, host_number); esw_funcs->num_spfs++; =20 entry +=3D MLX5_UN_SZ_BYTES(net_function_params); @@ -2224,6 +2281,7 @@ static void mlx5_esw_vports_cleanup(struct mlx5_eswit= ch *esw) unsigned long i; =20 mlx5_esw_spfs_cleanup(esw); + esw->esw_funcs.has_spf_sfs =3D false; mlx5_esw_for_each_vport(esw, i, vport) mlx5_esw_vport_free(esw, vport); xa_destroy(&esw->vports); @@ -2232,8 +2290,7 @@ static void mlx5_esw_vports_cleanup(struct mlx5_eswit= ch *esw) static int mlx5_esw_vports_init(struct mlx5_eswitch *esw) { struct mlx5_core_dev *dev =3D esw->dev; - u16 max_host_pf_sfs; - u16 base_sf_num; + u16 max_sfs, base_sf_num; int idx =3D 0; int err; int i; @@ -2270,10 +2327,10 @@ static int mlx5_esw_vports_init(struct mlx5_eswitch= *esw) idx++; } =20 - err =3D mlx5_esw_sf_max_hpf_functions(dev, &max_host_pf_sfs, &base_sf_num= ); + err =3D mlx5_esw_sf_max_hpf_functions(dev, &max_sfs, &base_sf_num); if (err) goto err; - for (i =3D 0; i < max_host_pf_sfs; i++) { + for (i =3D 0; i < max_sfs; i++) { err =3D mlx5_esw_vport_alloc(esw, idx, base_sf_num + i); if (err) goto err; @@ -2295,6 +2352,22 @@ static int mlx5_esw_vports_init(struct mlx5_eswitch = *esw) goto err; vport =3D mlx5_eswitch_get_vport(esw, vport_num); vport->vhca_id =3D esw->esw_funcs.spfs[i].vhca_id; + + err =3D mlx5_esw_sf_max_spf_functions(dev, i, + &max_sfs, &base_sf_num); + if (err) + goto err; + if (max_sfs) + esw->esw_funcs.has_spf_sfs =3D true; + for (int j =3D 0; j < max_sfs; j++) { + err =3D mlx5_esw_vport_alloc(esw, idx, + base_sf_num + j); + if (err) + goto err; + xa_set_mark(&esw->vports, base_sf_num + j, + MLX5_ESW_VPT_SF); + idx++; + } } =20 if (mlx5_core_ec_sriov_enabled(esw->dev)) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index abdb4c460b06..88041dd8a39d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -351,6 +351,7 @@ struct mlx5_host_work { struct mlx5_esw_spf { u16 vport_num; u16 vhca_id; + u16 host_number; }; =20 struct mlx5_esw_functions { @@ -359,6 +360,7 @@ struct mlx5_esw_functions { u16 num_vfs; u16 num_ec_vfs; u16 hpf_host_number; + bool has_spf_sfs; struct mlx5_esw_spf *spfs; int num_spfs; }; @@ -878,8 +880,14 @@ void mlx5_esw_offloads_devlink_port_unregister(struct = mlx5_vport *vport); struct devlink_port *mlx5_esw_offloads_devlink_port(struct mlx5_eswitch *e= sw, u16 vport_num); =20 int mlx5_esw_sf_max_hpf_functions(struct mlx5_core_dev *dev, u16 *max_sfs,= u16 *sf_base_id); +int mlx5_esw_sf_max_spf_functions(struct mlx5_core_dev *dev, int spf_idx, + u16 *max_sfs, u16 *sf_base_id); =20 +int mlx5_esw_get_num_spfs(struct mlx5_core_dev *dev); +int mlx5_esw_spf_get_host_number(struct mlx5_core_dev *dev, int spf_idx, + u16 *host_number); u16 mlx5_esw_get_hpf_host_number(struct mlx5_core_dev *dev); +bool mlx5_esw_has_spf_sfs(struct mlx5_core_dev *dev); =20 int mlx5_esw_vport_vhca_id_map(struct mlx5_eswitch *esw, struct mlx5_vport *vport); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index f17db51abe2d..c229a96a111f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -3821,6 +3821,9 @@ int mlx5_esw_funcs_changed_handler(struct notifier_bl= ock *nb, =20 bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u3= 2 controller) { + const struct mlx5_esw_functions *esw_funcs; + int i; + /* Local controller is always valid */ if (controller =3D=3D 0) return true; @@ -3829,7 +3832,15 @@ bool mlx5_esw_offloads_controller_valid(const struct= mlx5_eswitch *esw, u32 cont return false; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Simon Horman" , Adithya Jayachandran , Jiri Pirko , Moshe Shemesh , Or Har-Toov , Shay Drori , Parav Pandit , Daniel Jurgens , Kees Cook , Cosmin Ratiu , Carolina Jubran , , , , Gal Pressman Subject: [PATCH net-next 05/12] net/mlx5: Support SPF SFs in SF hardware table Date: Thu, 21 May 2026 14:08:36 +0300 Message-ID: <20260521110843.367329-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260521110843.367329-1-tariqt@nvidia.com> References: <20260521110843.367329-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00022573:EE_|DS0PR12MB6533:EE_ X-MS-Office365-Filtering-Correlation-Id: 5da1ea2f-9648-47d4-3a28-08deb729cb30 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700016|82310400026|1800799024|22082099003|56012099003|18002099003|11063799006|6133799003; X-Microsoft-Antispam-Message-Info: XplOwkMheiPZIkrpCswLnRM6/qEJnNdEHWx/eRaWvbaKq5+hvjfgrisV2fcn6EbvT0/G8QpJBSGcROTHN2st8DYZa7wHZUsA5IlBpnxE6qsRpCkqtTcSvrsbZOmvVUDdb8qjXA09GfvIruESIxCoNl7SDoqXRQgmvZKVOJKvZyjkLiZRgcjYQ1JnWkYYLbp52h3qnQn8HqUGyaIX2HqLHbRdl84pPDcBy7ZIcG95yRtpILfkgruVNU4d2g3H7U11VkM59YKAoTnirgN09wug5nkQqA7UqZbaT0zt38Id1sFJ432KKRaPE63vER0xCr43VYNVO9sGSKkhLLnkspUnmEw8QNpfMxIRuLElhywgrNTWaWkcoJJKFls5k4Ks370YIIHSWIh2NqW3wV1b9hGs1EahSyob9Ttpprwtl9rls4MaTFEnwc8Zw7wXJSiDWiCM8GjlAZV7DfvyRbsIUS+yYg/RFg91hDvgC/V2isC10CYGpjnDsvuasgjAgWevHRa0gnOFUkk8OCyCJtIYvQ1Cl9Efrm5L8opE5cpF127CLSrwW9/82HUlhebfj/ew/ZIrURTLxvMX84PPbMMlUQiTPYiZPuID3lqPzGjGP6if8qG0LwVm7nOND4S0zwNoYEBWDbF8z4Ntu4GGrT3UM9qjcS4fDLBnZhQQlNGcNP4xTmHmzU9n3cCA+NDucry+p7ywUhImFBcCK9Q3J+fg+/nD/2Lac/ciwQnIsYDYsEJx1Co= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700016)(82310400026)(1800799024)(22082099003)(56012099003)(18002099003)(11063799006)(6133799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: JpmT8fuV8psZT0HPPE2WlDGvkbd3S+wicc+bzZFaAhVq7MY/wEwWydaFfwNifeCpVGkbqzsYZIfkNT94OGsO0WqRuIQcp5dNVcnzXajbC+lo0ElkqWpDh42wpx7WQk6KnJ47r4IJ4Klt6+Bjy98d6QtiYz4JBBGoApxf3JEfQWG4O1zmNRYqNakluQP/4sPx+GrZFEuHhZ6AT3KrObRsvJygZiCbXKGViqkQisJp2JbugGiLXgyI0AfInn04j1Bd1R39xh2M2rj0pvxAM4a3+afB1Ln5QAI/vl0gEp6suvdO/HveO+KLgWofWnU/C6oiiKTlxTcpd/CgC4XDzZBaKLKGY3j4murCAH+oc0+qrGzS+8nS7YAR5vWmRXVmv7MdjKD4M4t4rdD/XjNyV2tlsksgEq2vi4sMOqT46PAPg0Vt+gcNvBtbYOR85nJAzgrh X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2026 11:12:06.1724 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5da1ea2f-9648-47d4-3a28-08deb729cb30 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022573.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6533 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Convert the SF hardware table from a fixed-size hwc array to a dynamically allocated one, supporting satellite PF (SPF) SFs alongside local and external host SFs. Initialize hwc entries for each SPF using its host_number as controller. Rename MLX5_SF_HWC_EXTERNAL to MLX5_SF_HWC_EXT_HOST and add MLX5_SF_HWC_FIRST_SPF for clarity. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/sf/hw_table.c | 89 ++++++++++++++----- 1 file changed, 69 insertions(+), 20 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/hw_table.c b/driver= s/net/ethernet/mellanox/mlx5/core/sf/hw_table.c index 049dfd431618..0bc9146a3598 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/sf/hw_table.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/hw_table.c @@ -21,25 +21,33 @@ struct mlx5_sf_hwc_table { struct mlx5_sf_hw *sfs; int max_fn; u16 start_fn_id; + u32 controller; }; =20 -enum mlx5_sf_hwc_index { +enum { MLX5_SF_HWC_LOCAL, - MLX5_SF_HWC_EXTERNAL, - MLX5_SF_HWC_MAX, + MLX5_SF_HWC_EXT_HOST, + MLX5_SF_HWC_FIRST_SPF, }; =20 struct mlx5_sf_hw_table { struct mutex table_lock; /* Serializes sf deletion and vhca state change = handler. */ - struct mlx5_sf_hwc_table hwc[MLX5_SF_HWC_MAX]; + struct mlx5_sf_hwc_table *hwc; + int num_hwc; }; =20 static struct mlx5_sf_hwc_table * mlx5_sf_controller_to_hwc(struct mlx5_core_dev *dev, u32 controller) { - int idx =3D !!controller; + struct mlx5_sf_hw_table *table =3D dev->priv.sf_hw_table; + int i; + + for (i =3D MLX5_SF_HWC_FIRST_SPF; i < table->num_hwc; i++) { + if (table->hwc[i].controller =3D=3D controller) + return &table->hwc[i]; + } =20 - return &dev->priv.sf_hw_table->hwc[idx]; + return &table->hwc[!!controller]; } =20 u16 mlx5_sf_sw_to_hw_id(struct mlx5_core_dev *dev, u32 controller, u16 sw_= id) @@ -60,7 +68,7 @@ mlx5_sf_table_fn_to_hwc(struct mlx5_sf_hw_table *table, u= 16 fn_id) { int i; =20 - for (i =3D 0; i < ARRAY_SIZE(table->hwc); i++) { + for (i =3D 0; i < table->num_hwc; i++) { if (table->hwc[i].max_fn && fn_id >=3D table->hwc[i].start_fn_id && fn_id < (table->hwc[i].start_fn_id + table->hwc[i].max_fn)) @@ -221,9 +229,10 @@ static void mlx5_sf_hw_table_hwc_dealloc_all(struct ml= x5_core_dev *dev, static void mlx5_sf_hw_table_dealloc_all(struct mlx5_core_dev *dev, struct mlx5_sf_hw_table *table) { - mlx5_sf_hw_table_hwc_dealloc_all(dev, - &table->hwc[MLX5_SF_HWC_EXTERNAL]); - mlx5_sf_hw_table_hwc_dealloc_all(dev, &table->hwc[MLX5_SF_HWC_LOCAL]); + int i; + + for (i =3D 0; i < table->num_hwc; i++) + mlx5_sf_hw_table_hwc_dealloc_all(dev, &table->hwc[i]); } =20 static int mlx5_sf_hw_table_hwc_init(struct mlx5_sf_hwc_table *hwc, u16 ma= x_fn, u16 base_id) @@ -277,11 +286,13 @@ static int mlx5_sf_hw_table_res_register(struct mlx5_= core_dev *dev, u16 max_fn, int mlx5_sf_hw_table_init(struct mlx5_core_dev *dev) { struct mlx5_sf_hw_table *table; + int num_spfs, num_hwc; u16 max_ext_fn =3D 0; u16 ext_base_id =3D 0; u16 base_id; u16 max_fn; int err; + int i; =20 if (!mlx5_vhca_event_supported(dev)) return 0; @@ -295,7 +306,7 @@ int mlx5_sf_hw_table_init(struct mlx5_core_dev *dev) if (mlx5_sf_hw_table_res_register(dev, max_fn, max_ext_fn)) mlx5_core_dbg(dev, "failed to register max SFs resources"); =20 - if (!max_fn && !max_ext_fn) + if (!max_fn && !max_ext_fn && !mlx5_esw_has_spf_sfs(dev)) return 0; =20 table =3D kzalloc_obj(*table); @@ -304,26 +315,62 @@ int mlx5_sf_hw_table_init(struct mlx5_core_dev *dev) goto alloc_err; } =20 + num_spfs =3D mlx5_esw_get_num_spfs(dev); + num_hwc =3D MLX5_SF_HWC_FIRST_SPF + num_spfs; + table->hwc =3D kcalloc(num_hwc, sizeof(*table->hwc), GFP_KERNEL); + if (!table->hwc) { + err =3D -ENOMEM; + goto hwc_alloc_err; + } + table->num_hwc =3D num_hwc; + mutex_init(&table->table_lock); dev->priv.sf_hw_table =3D table; =20 + table->hwc[MLX5_SF_HWC_LOCAL].controller =3D 0; base_id =3D mlx5_sf_start_function_id(dev); err =3D mlx5_sf_hw_table_hwc_init(&table->hwc[MLX5_SF_HWC_LOCAL], max_fn,= base_id); if (err) - goto table_err; + goto hwc_init_err; =20 - err =3D mlx5_sf_hw_table_hwc_init(&table->hwc[MLX5_SF_HWC_EXTERNAL], + table->hwc[MLX5_SF_HWC_EXT_HOST].controller =3D + mlx5_esw_get_hpf_host_number(dev) + 1; + err =3D mlx5_sf_hw_table_hwc_init(&table->hwc[MLX5_SF_HWC_EXT_HOST], max_ext_fn, ext_base_id); if (err) - goto ext_err; + goto hwc_init_err; + + for (i =3D 0; i < num_spfs; i++) { + u16 spf_max_sfs, spf_base_id, host_number; + int hwc_idx =3D MLX5_SF_HWC_FIRST_SPF + i; + + err =3D mlx5_esw_spf_get_host_number(dev, i, &host_number); + if (err) + goto hwc_init_err; + + err =3D mlx5_esw_sf_max_spf_functions(dev, i, &spf_max_sfs, + &spf_base_id); + if (err) + goto hwc_init_err; =20 - mlx5_core_dbg(dev, "SF HW table: max sfs =3D %d, ext sfs =3D %d\n", max_f= n, max_ext_fn); + table->hwc[hwc_idx].controller =3D host_number + 1; + err =3D mlx5_sf_hw_table_hwc_init(&table->hwc[hwc_idx], + spf_max_sfs, spf_base_id); + if (err) + goto hwc_init_err; + } + + mlx5_core_dbg(dev, "SF HW table: max sfs =3D %d, ext sfs =3D %d, num spfs= =3D %d\n", + max_fn, max_ext_fn, num_spfs); return 0; =20 -ext_err: - mlx5_sf_hw_table_hwc_cleanup(&table->hwc[MLX5_SF_HWC_LOCAL]); -table_err: +hwc_init_err: + dev->priv.sf_hw_table =3D NULL; + for (i =3D 0; i < num_hwc; i++) + mlx5_sf_hw_table_hwc_cleanup(&table->hwc[i]); mutex_destroy(&table->table_lock); + kfree(table->hwc); +hwc_alloc_err: kfree(table); alloc_err: mlx5_sf_hw_table_res_unregister(dev); @@ -333,13 +380,15 @@ int mlx5_sf_hw_table_init(struct mlx5_core_dev *dev) void mlx5_sf_hw_table_cleanup(struct mlx5_core_dev *dev) { struct mlx5_sf_hw_table *table =3D dev->priv.sf_hw_table; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Simon Horman" , Adithya Jayachandran , Jiri Pirko , Moshe Shemesh , Or Har-Toov , Shay Drori , Parav Pandit , Daniel Jurgens , Kees Cook , Cosmin Ratiu , Carolina Jubran , , , , Gal Pressman Subject: [PATCH net-next 06/12] net/mlx5: Expose PF number from query_esw_functions Date: Thu, 21 May 2026 14:08:37 +0300 Message-ID: <20260521110843.367329-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260521110843.367329-1-tariqt@nvidia.com> References: <20260521110843.367329-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00022572:EE_|SAWPR12MB999140:EE_ X-MS-Office365-Filtering-Correlation-Id: 54b72a59-3a6f-405c-1f43-08deb729d13d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|82310400026|7416014|376014|22082099003|56012099003|3023799007|11063799006|18002099003|6133799003; X-Microsoft-Antispam-Message-Info: ImPWDt+xhsx4Jt3mcrvgWmQHhVUECdBdGGJGeCVKeYQHEkku6RR6Oir+7rQ/sgizZsfmVE3/bAnxfVCm1ufnidkEa0jDHgD0GdySJOfe6QIMcF128oIx5GWhYSdoDTPZbOVNiuzy6GH+DzD00M5F3RkI4Iqc02L12T+wnSio5pj49HVjLLBpBPdqTSpCVjbC8gF/4X2AIu+k/8qMy9uUId/9yRPrsMzPldPTNVMqvqADT6+Ipqt9VKZEPctZ15ZksJGOanIh57rHxRBWtql9GPRo8cLHCmYo8eKBVS0YhKexo1M2nTbSh1PGbwqgkK+8cYdv/yPP9z8Anbl7U1QfKydsrxGLg153+qsEdCuL6ePzc8+fEYP+ksAchA+REH7MS9qu+/AHMaR9jz04/uJ6sNEiC4w650TvYyL3UZiDN/96kc0RmAgjFfdJs0YX9qGzL4T7HQuBR4CKA+5p433OWgbkrQ5DkLa9OGm+dhvediuFploq2NUxlM4gPs8pzSzu8VO/z6w2kNTHwkHJK8+CQgEU8LrmByhNJq7+ZqJ3ECqqw3h2DeIISsAy5g5Lrz/Aad2Wk+aZx90yAqvip4duoofa9d4id+Vmy7I/o2xH4NZtl04ZhtMrRM+xlY85AaOHUFHLvulS8ZGMpbbiv8VulD2HxWnRipIIGo/haiyqSZqLkEZ+pvyXEXp5zuhZX4XbLp+vDd7tz9AjEUwMC1Mxd/LN6GYH8yFQH+u5dxt1KuE= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(82310400026)(7416014)(376014)(22082099003)(56012099003)(3023799007)(11063799006)(18002099003)(6133799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: zUw3emYwApGoKOVqjmriY6rM2f6gyokgceemjWEtQ42zYVuHt/V+sqsVopcZKShbCwDyOfkkO2UV86yu5THwZ6bYk5cDnddGvWCS0h2/nTMYE5ougJbYqaqdQQPDraTimoCL6O0CQC+Q6jJLgSxsS+7piSW+Zj6Qauj4ap3/MP/23q5CWP2NBrt169ZdIm5MTljCCWypd2A8P3HgRbxpTjjep4mXXJ5uPpZJcgW1BfHwndt2NQ1N7yRGS+AvJuClhSefMNgkIRYUilZv4QiixAzETmj3YciiWX3uJ1ACS8lBsvdu6hwhrxgu3MQE53I7cXs9dS4xPmdvOeDzSNn+KoEI0ALmELGax/knkMARANKiCN2rG6Q8aDBgdN2Fs2wCRW4+qN27fm7y0D6m+5SBJbALrMvml/pdi7K1gmi6GlMfYWOR7YsIfv2qoOolay87 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2026 11:12:16.3310 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 54b72a59-3a6f-405c-1f43-08deb729d13d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022572.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SAWPR12MB999140 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Extract pci_device_function from the query_esw_functions output for both the host PF and satellite PFs, storing it alongside the existing host_number field. Add mlx5_esw_get_hpf_pf_num() helper that returns the host PF's actual PCI device function when the new query format is supported, falling back to PCI_FUNC(dev->pdev->devfn) for older firmware. Use it in devlink port attribute setup so that host PF and VF devlink ports report the correct PF number rather than the ECPF's own PCI function number. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/esw/devlink_port.c | 4 ++++ .../net/ethernet/mellanox/mlx5/core/eswitch.c | 22 ++++++++++++++++--- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 4 ++++ 3 files changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c b/d= rivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c index e723f05cd4d3..d5f0101aa966 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c @@ -37,6 +37,8 @@ static void mlx5_esw_offloads_pf_vf_devlink_port_attrs_se= t(struct mlx5_eswitch * controller_num =3D mlx5_esw_get_hpf_host_number(dev) + 1; =20 if (vport_num =3D=3D MLX5_VPORT_HOST_PF) { + if (external) + pfnum =3D mlx5_esw_get_hpf_pf_num(dev); memcpy(dl_port->attrs.switch_id.id, ppid.id, ppid.id_len); dl_port->attrs.switch_id.id_len =3D ppid.id_len; devlink_port_attrs_pci_pf_set(dl_port, controller_num, pfnum, external); @@ -49,6 +51,8 @@ static void mlx5_esw_offloads_pf_vf_devlink_port_attrs_se= t(struct mlx5_eswitch * if (vport->adjacent) { func_id =3D vport->adj_info.function_id; pfnum =3D vport->adj_info.parent_pci_devfn; + } else if (external) { + pfnum =3D mlx5_esw_get_hpf_pf_num(dev); } =20 devlink_port_attrs_pci_vf_set(dl_port, controller_num, pfnum, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index 42cdb4309258..8e2ac759d1f3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -1157,6 +1157,8 @@ mlx5_esw_host_pf_from_net_func_params(const u8 *entry= , int num_entries) entry, pci_total_vfs), .host_number =3D MLX5_GET(network_function_params, entry, host_number), + .pf_num =3D MLX5_GET(network_function_params, entry, + pci_device_function), }; } =20 @@ -2103,7 +2105,6 @@ int mlx5_esw_spf_get_host_number(struct mlx5_core_dev= *dev, int spf_idx, return -EINVAL; =20 *host_number =3D esw->esw_funcs.spfs[spf_idx].host_number; - return 0; } =20 @@ -2117,6 +2118,17 @@ u16 mlx5_esw_get_hpf_host_number(struct mlx5_core_de= v *dev) return esw->esw_funcs.hpf_host_number; } =20 +u16 mlx5_esw_get_hpf_pf_num(struct mlx5_core_dev *dev) +{ + struct mlx5_eswitch *esw =3D dev->priv.eswitch; + + if (mlx5_core_is_ecpf_esw_manager(dev) && + MLX5_CAP_GEN(dev, query_host_net_function_v1)) + return esw->esw_funcs.hpf_pf_num; + + return PCI_FUNC(dev->pdev->devfn); +} + bool mlx5_esw_has_spf_sfs(struct mlx5_core_dev *dev) { struct mlx5_eswitch *esw =3D dev->priv.eswitch; @@ -2127,7 +2139,7 @@ bool mlx5_esw_has_spf_sfs(struct mlx5_core_dev *dev) return esw->esw_funcs.has_spf_sfs; } =20 -static int mlx5_esw_hpf_host_number_init(struct mlx5_eswitch *esw) +static int mlx5_esw_hpf_info_init(struct mlx5_eswitch *esw) { struct mlx5_esw_pf_info host_pf_info; const u32 *query_host_out; @@ -2142,6 +2154,7 @@ static int mlx5_esw_hpf_host_number_init(struct mlx5_= eswitch *esw) /* Mark non local controller with non zero controller number. */ host_pf_info =3D mlx5_esw_get_host_pf_info(esw->dev, query_host_out); esw->esw_funcs.hpf_host_number =3D host_pf_info.host_number; + esw->esw_funcs.hpf_pf_num =3D host_pf_info.pf_num; kvfree(query_host_out); return 0; } @@ -2255,6 +2268,9 @@ static int mlx5_esw_spfs_init(struct mlx5_eswitch *es= w) esw_funcs->spfs[esw_funcs->num_spfs].vhca_id =3D vhca_id; esw_funcs->spfs[esw_funcs->num_spfs].host_number =3D MLX5_GET(network_function_params, entry, host_number); + esw_funcs->spfs[esw_funcs->num_spfs].pf_num =3D + MLX5_GET(network_function_params, entry, + pci_device_function); esw_funcs->num_spfs++; =20 entry +=3D MLX5_UN_SZ_BYTES(net_function_params); @@ -2297,7 +2313,7 @@ static int mlx5_esw_vports_init(struct mlx5_eswitch *= esw) =20 xa_init(&esw->vports); =20 - err =3D mlx5_esw_hpf_host_number_init(esw); + err =3D mlx5_esw_hpf_info_init(esw); if (err) goto err; =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index 88041dd8a39d..03c7582d7b95 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -77,6 +77,7 @@ struct mlx5_esw_pf_info { u16 num_of_vfs; u16 total_vfs; u16 host_number; + u16 pf_num; }; =20 #ifdef CONFIG_MLX5_ESWITCH @@ -352,6 +353,7 @@ struct mlx5_esw_spf { u16 vport_num; u16 vhca_id; u16 host_number; + u16 pf_num; }; =20 struct mlx5_esw_functions { @@ -360,6 +362,7 @@ struct mlx5_esw_functions { u16 num_vfs; u16 num_ec_vfs; u16 hpf_host_number; + u16 hpf_pf_num; bool has_spf_sfs; struct mlx5_esw_spf *spfs; int num_spfs; @@ -887,6 +890,7 @@ int mlx5_esw_get_num_spfs(struct mlx5_core_dev *dev); int mlx5_esw_spf_get_host_number(struct mlx5_core_dev *dev, int spf_idx, u16 *host_number); u16 mlx5_esw_get_hpf_host_number(struct mlx5_core_dev *dev); +u16 mlx5_esw_get_hpf_pf_num(struct mlx5_core_dev *dev); bool mlx5_esw_has_spf_sfs(struct mlx5_core_dev *dev); =20 int mlx5_esw_vport_vhca_id_map(struct mlx5_eswitch *esw, --=20 2.44.0 From nobody Sun May 24 21:37:40 2026 Received: from SA9PR02CU001.outbound.protection.outlook.com (mail-southcentralusazon11013001.outbound.protection.outlook.com [40.93.196.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96C573BB130; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Simon Horman" , Adithya Jayachandran , Jiri Pirko , Moshe Shemesh , Or Har-Toov , Shay Drori , Parav Pandit , Daniel Jurgens , Kees Cook , Cosmin Ratiu , Carolina Jubran , , , , Gal Pressman Subject: [PATCH net-next 07/12] net/mlx5: Map SF controller to pfnum for satellite PFs Date: Thu, 21 May 2026 14:08:38 +0300 Message-ID: <20260521110843.367329-8-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260521110843.367329-1-tariqt@nvidia.com> References: <20260521110843.367329-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0002256E:EE_|CH3PR12MB9283:EE_ X-MS-Office365-Filtering-Correlation-Id: f80caefc-9f76-47eb-5d1a-08deb729d47e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|36860700016|82310400026|11063799006|18002099003|56012099003|22082099003|6133799003; X-Microsoft-Antispam-Message-Info: 7HTmJfkQsH8CyFArhPRFmXVkefIt2fLlMlR/Wn+skl+6vTs+IUwT2OnDokJsyslBGbA3AWT7VZ7vNy7XhoRp3slja7w3c2JFcvHHNv4mV/fXUyaBRtyuN0dhUcJexTI+nmegtz1XM+gGPfY19thatxHqhH9RDdtZ9GaEoyOvUsppE/zSDVYwNt1Lz4MaNvPR4OpmehiBYHbwGgsNdykVrz+EQj6uvDy9KbFuXMf6aaM2DSrP0uZdNOFxEDpBjRgTWNkpffaLsqUqq3gKigC+m0Jw+N+0W5SMoGmEAHulT51TYW1vsPdGlvPLJhPHUWHNpW4j2/AgMxxNrhVaVlSQSEw4CikdLeTd0ub+yuHaTn4tMysA3JVEz3MGc21eWXG6P3UMsBP0uqFd+YnFTuBUt+2r2nSpFOtPM2f1G1+qgtwYisFA5ndfLq4b+EOTdeyEGoFRnFZ8C8yr5rz/8Wbd3p7rGD5I5mYjCSRgDeQZOoif4HqcVtlapEUgwqmN4WK8PG0hTvrvT9nL98sNuHt2A4dVv9X+lTDoufqSQULLAoOI0Lh6Fd2m6KMOt068AOGsY3lD0pQm582fke8Yfu+hC/hZ/epelqA7gId4jEPLmE4Ij7prlIH9myuogrOXLssiYEDfZ7muoJ5GJyd+Mg7dx3e2NLb5x06jv93wu8VWoas32iBLlreNXIbfCkHDgpybUeDmQgEW8AnnS6t7XDW8k1pVMK3FkH+xWVFU4Z5h2P8= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(36860700016)(82310400026)(11063799006)(18002099003)(56012099003)(22082099003)(6133799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: j2yUNMNOElE4UKTIRkZ7ZSgNY6Gft3FaZWym8NJKGzMaQNsDE8c0ScZhz/9rT9b7QQ2BdG32vI9UEHWOXKwir9ElgxmLwS2DftuUxvyZOWGsRX5Ye8H4CqyuTsL2+SeHQWa1cyzddwcC3JisnvX7LJoNN8ekDXKkIY6w3tWXtDf09PBV/g3aARANvAvusTOA8g7tnwqfUASZjiSusBAp65H+VZD+bbATOAHa5v4CWL43o9jApiyPOP1trwQImV9O4euoy6MvlfRrICVYbYtXn5ie77iSMUoh5LyH7rlSxzf7Ew6g0BNom1zWy1ihBBQvGVd6ZCvfD7ILgEVfROx6wQqTrq0uOgY+NAt9Wa4RuRTVnTcsvO0OYaaKh59f3E4UXBmD0iuFqiSfoy03ccfMO6KgJX7HLbikcr8DNbU/sCRvqouFmuuc0vWOpJSRjPzx X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2026 11:12:21.7885 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f80caefc-9f76-47eb-5d1a-08deb729d47e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0002256E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9283 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh SF devlink port creation and registration used the ECPF's PCI function as pfnum. Extend this to support satellite PF controllers by introducing mlx5_esw_sf_controller_to_pfnum() that maps a controller number to the corresponding PF number, and use it in SF port attribute setup and SF creation validation. Reorder the checks in mlx5_devlink_sf_port_new() so that mlx5_sf_table_supported() runs before attribute validation, since the new helper requires the eswitch to be initialized. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/esw/devlink_port.c | 2 +- .../net/ethernet/mellanox/mlx5/core/eswitch.c | 17 +++++++++++++++++ .../net/ethernet/mellanox/mlx5/core/eswitch.h | 1 + .../ethernet/mellanox/mlx5/core/sf/devlink.c | 14 +++++++++----- 4 files changed, 28 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c b/d= rivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c index d5f0101aa966..fddb108bcbff 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c @@ -125,7 +125,7 @@ static void mlx5_esw_offloads_sf_devlink_port_attrs_set= (struct mlx5_eswitch *esw struct netdev_phys_item_id ppid =3D {}; u16 pfnum; =20 - pfnum =3D PCI_FUNC(dev->pdev->devfn); + pfnum =3D mlx5_esw_sf_controller_to_pfnum(dev, controller); mlx5_esw_get_port_parent_id(dev, &ppid); memcpy(dl_port->attrs.switch_id.id, &ppid.id[0], ppid.id_len); dl_port->attrs.switch_id.id_len =3D ppid.id_len; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index 8e2ac759d1f3..f734f9364b2c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -2129,6 +2129,23 @@ u16 mlx5_esw_get_hpf_pf_num(struct mlx5_core_dev *de= v) return PCI_FUNC(dev->pdev->devfn); } =20 +u16 mlx5_esw_sf_controller_to_pfnum(struct mlx5_core_dev *dev, u32 control= ler) +{ + struct mlx5_eswitch *esw =3D dev->priv.eswitch; + struct mlx5_esw_functions *esw_funcs; + int i; + + if (!controller) + return PCI_FUNC(dev->pdev->devfn); + + esw_funcs =3D &esw->esw_funcs; + for (i =3D 0; i < esw_funcs->num_spfs; i++) + if (controller =3D=3D esw_funcs->spfs[i].host_number + 1) + return esw_funcs->spfs[i].pf_num; + + return mlx5_esw_get_hpf_pf_num(dev); +} + bool mlx5_esw_has_spf_sfs(struct mlx5_core_dev *dev) { struct mlx5_eswitch *esw =3D dev->priv.eswitch; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index 03c7582d7b95..f85be8e39953 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -891,6 +891,7 @@ int mlx5_esw_spf_get_host_number(struct mlx5_core_dev *= dev, int spf_idx, u16 *host_number); u16 mlx5_esw_get_hpf_host_number(struct mlx5_core_dev *dev); u16 mlx5_esw_get_hpf_pf_num(struct mlx5_core_dev *dev); +u16 mlx5_esw_sf_controller_to_pfnum(struct mlx5_core_dev *dev, u32 control= ler); bool mlx5_esw_has_spf_sfs(struct mlx5_core_dev *dev); =20 int mlx5_esw_vport_vhca_id_map(struct mlx5_eswitch *esw, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c b/drivers= /net/ethernet/mellanox/mlx5/core/sf/devlink.c index 2fc69897e35b..b6cecbcc392d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c @@ -265,6 +265,8 @@ static int mlx5_sf_new_check_attr(struct mlx5_core_dev *dev, const struct devlink_por= t_new_attrs *new_attr, struct netlink_ext_ack *extack) { + u32 controller; + if (new_attr->flavour !=3D DEVLINK_PORT_FLAVOUR_PCI_SF) { NL_SET_ERR_MSG_MOD(extack, "Driver supports only SF port addition"); return -EOPNOTSUPP; @@ -284,7 +286,9 @@ mlx5_sf_new_check_attr(struct mlx5_core_dev *dev, const= struct devlink_port_new_ NL_SET_ERR_MSG_MOD(extack, "External controller is unsupported"); return -EOPNOTSUPP; } - if (new_attr->pfnum !=3D PCI_FUNC(dev->pdev->devfn)) { + controller =3D new_attr->controller_valid ? new_attr->controller : 0; + if (new_attr->pfnum !=3D + mlx5_esw_sf_controller_to_pfnum(dev, controller)) { NL_SET_ERR_MSG_MOD(extack, "Invalid pfnum supplied"); return -EOPNOTSUPP; } @@ -306,10 +310,6 @@ int mlx5_devlink_sf_port_new(struct devlink *devlink, struct mlx5_sf_table *table =3D dev->priv.sf_table; int err; =20 - err =3D mlx5_sf_new_check_attr(dev, new_attr, extack); - if (err) - return err; - if (!mlx5_sf_table_supported(dev)) { NL_SET_ERR_MSG_MOD(extack, "SF ports are not supported."); return -EOPNOTSUPP; @@ -321,6 +321,10 @@ int mlx5_devlink_sf_port_new(struct devlink *devlink, return -EOPNOTSUPP; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Simon Horman" , Adithya Jayachandran , Jiri Pirko , Moshe Shemesh , Or Har-Toov , Shay Drori , Parav Pandit , Daniel Jurgens , Kees Cook , Cosmin Ratiu , Carolina Jubran , , , , Gal Pressman Subject: [PATCH net-next 08/12] net/mlx5: Register devlink ports for satellite PFs Date: Thu, 21 May 2026 14:08:39 +0300 Message-ID: <20260521110843.367329-9-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260521110843.367329-1-tariqt@nvidia.com> References: <20260521110843.367329-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD76:EE_|MN0PR12MB5811:EE_ X-MS-Office365-Filtering-Correlation-Id: e9e0b3cf-5a54-43a8-09b2-08deb729da32 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|7416014|36860700016|22082099003|18002099003|56012099003|11063799006|6133799003; X-Microsoft-Antispam-Message-Info: 2yX6uDyDBLPpdE3xULneWjur5enAFs+ZWNegM0i/QmU2cuJZozfb5sjjV9YGcLy3es9erx2M0gydVzlbOVzNg25bUpexb+sKSMr6S+/7xeCniXxQ476uTLHHI5zgA6wsCD/aFZQd/hFWK9RD8IU+TvEj/YHtOWe7jKW5KePlllwjxU4YJ0pa5b0xyO3M8IoXpO7JxxyuPJPN2IL85SiHuqzQp93q/tozFSwF4BxPHfcoIu3Ce9lH31kcJovZzOaTFVOfonY6RwzCaMbAQ9qMHKT4kPiXFXMIuS9aMZgnE7J1Fwf79PmsHr7b6uUh+GhztsqlHGdrJa9Vg4Xe+SPcra8Y4dTgVgEAn2I6Q1PM7K5jbT/z3Mu8k2k62udgBxh3s3rWeMifMBd4hTlUqmVN29WYp4jj0WhLXdtdeNTrlsz4y1ZCdDEW4/kAV8O3gnvkY9cvjZ2tGujJa3166FG4gYqXRKbHoavtn+XGn5nTLT9b3XzwXc6dN+WJbYLCr8A3wbnPonfibQqTPQikwsJqiRWiSUneAjnNFz9zf1l/7BCInW3F6kSdG3Iinl6N+4ufNEP7bIiIaDMpFOcapKfPKAkr9rXhsJVXhNMQmxNLAdqnPFes5H2hjVm6cFWeJ0NGDWbDsIrAcNDJdnH2xmW/KorURNucGrWUIZl8eOzJOz0/H7n4qG9fitb2jYrVv+EsIqfx3Zqai45DFE5FqKwliDcLCUo6JN0L30UcE0SqOhs= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(7416014)(36860700016)(22082099003)(18002099003)(56012099003)(11063799006)(6133799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: SQj2LItuCVYVr4vkwSBGYh6eJYMsNaUeVYRRaQlQ1E5h28GYYHPbscuRJug1aDD2S3JvpxuvIs4DzaPeHtw0KL1q9OhHi3Lv0y6vwbEkvp7BSDnDLglBulOYR3CZsdKVOy4n2CehDwA62i7jQcScMq9EmqHiCv1YZCEOt9a6fTbH7CEsCVsKdIlmjZk15KRCUmHxJuGQAB00sE7qOan4TMerFwgNpaNsAFGK51anaavVNKAmHdjwGYaNQ4Jy+hV43ORCRutXhLyHUc8iQQCAlMZwdTpjh7XFRZm8bkUWETKRP1Oxa7N+H7WW6WDDrVT04C2JEnIBJ9DVeHYMvUNvECzb/fmunzIYJza4MN+QjrDyZjWqqQKho06S3rTDArvrkO/Nxl6VDlfjhBUpaYQiN3av9wHI18vOM7PajZlPZX452Tfg9b9ZPL5sjc2+MpAA X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2026 11:12:31.3815 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e9e0b3cf-5a54-43a8-09b2-08deb729da32 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD76.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5811 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Include satellite PFs in mlx5_eswitch_is_pf_vf_vport() so they receive the standard PF/VF devlink port operations. Update mlx5_esw_devlink_port_supported() and devlink port attribute setup to register SPF devlink ports with controller number and PF number. Add mlx5_esw_spf_vport_to_idx() to look up the SPF array index by vport number, and mlx5_esw_is_spf_vport() boolean wrapper to identify satellite PF vports. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/esw/devlink_port.c | 13 +++++++++++- .../net/ethernet/mellanox/mlx5/core/eswitch.c | 21 ++++++++++++++++++- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 2 ++ 3 files changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c b/d= rivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c index fddb108bcbff..05d89769b917 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c @@ -16,7 +16,8 @@ static bool mlx5_esw_devlink_port_supported(struct mlx5_e= switch *esw, u16 vport_ return (mlx5_core_is_ecpf(esw->dev) && vport_num =3D=3D MLX5_VPORT_HOST_PF) || mlx5_eswitch_is_vf_vport(esw, vport_num) || - mlx5_core_is_ec_vf_vport(esw->dev, vport_num); + mlx5_core_is_ec_vf_vport(esw->dev, vport_num) || + mlx5_esw_is_spf_vport(esw, vport_num); } =20 static void mlx5_esw_offloads_pf_vf_devlink_port_attrs_set(struct mlx5_esw= itch *esw, @@ -64,6 +65,16 @@ static void mlx5_esw_offloads_pf_vf_devlink_port_attrs_s= et(struct mlx5_eswitch * dl_port->attrs.switch_id.id_len =3D ppid.id_len; devlink_port_attrs_pci_vf_set(dl_port, 0, pfnum, vport_num - base_vport, false); + } else if (mlx5_esw_is_spf_vport(esw, vport_num)) { + int spf_idx =3D mlx5_esw_spf_vport_to_idx(esw, vport_num); + + controller_num =3D esw->esw_funcs.spfs[spf_idx].host_number + 1; + pfnum =3D esw->esw_funcs.spfs[spf_idx].pf_num; + + memcpy(dl_port->attrs.switch_id.id, ppid.id, ppid.id_len); + dl_port->attrs.switch_id.id_len =3D ppid.id_len; + devlink_port_attrs_pci_pf_set(dl_port, controller_num, pfnum, + true); } } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index f734f9364b2c..8bee014140b8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -2651,10 +2651,29 @@ bool mlx5_eswitch_is_vf_vport(struct mlx5_eswitch *= esw, u16 vport_num) return mlx5_esw_check_port_type(esw, vport_num, MLX5_ESW_VPT_VF); } =20 +int mlx5_esw_spf_vport_to_idx(struct mlx5_eswitch *esw, u16 vport_num) +{ + struct mlx5_esw_functions *esw_funcs =3D &esw->esw_funcs; + int i; + + for (i =3D 0; i < esw_funcs->num_spfs; i++) { + if (esw_funcs->spfs[i].vport_num =3D=3D vport_num) + return i; + } + + return -ENOENT; +} + +bool mlx5_esw_is_spf_vport(struct mlx5_eswitch *esw, u16 vport_num) +{ + return mlx5_esw_spf_vport_to_idx(esw, vport_num) >=3D 0; +} + bool mlx5_eswitch_is_pf_vf_vport(struct mlx5_eswitch *esw, u16 vport_num) { return vport_num =3D=3D MLX5_VPORT_HOST_PF || - mlx5_eswitch_is_vf_vport(esw, vport_num); + mlx5_eswitch_is_vf_vport(esw, vport_num) || + mlx5_esw_is_spf_vport(esw, vport_num); } =20 bool mlx5_esw_is_sf_vport(struct mlx5_eswitch *esw, u16 vport_num) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index f85be8e39953..7da1a888aa7c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -798,6 +798,8 @@ struct mlx5_vport *__must_check mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Simon Horman" , Adithya Jayachandran , Jiri Pirko , Moshe Shemesh , Or Har-Toov , Shay Drori , Parav Pandit , Daniel Jurgens , Kees Cook , Cosmin Ratiu , Carolina Jubran , , , , Gal Pressman Subject: [PATCH net-next 09/12] net/mlx5: Register SF resource on satellite PF ports Date: Thu, 21 May 2026 14:08:40 +0300 Message-ID: <20260521110843.367329-10-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260521110843.367329-1-tariqt@nvidia.com> References: <20260521110843.367329-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CE:EE_|MW6PR12MB8959:EE_ X-MS-Office365-Filtering-Correlation-Id: 00061c75-2307-47c6-0d65-08deb729dc86 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|7416014|36860700016|1800799024|6133799003|11063799006|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: wgUTrl5Zy43XIGb4HqE+ocwC9ESq27+YsfGnFvoxeIFsBGbCKzXgoCPS3B5EDNzm4pX4t9GK7RHEoK/yfTgxyMyvfQZLRuU1j1WY331udxfMkxrFRxVp8brZi5JWxAp1LiPE+weCf6G47oPircLa9APtkeB6F/kbImsBQVv4qFu+Tk8YEkdlMgx7eLMW495tGV12/XA0O+xAyocx7TbJeOrdM2HCs4lGljWti7wQdJr0DXaEqIcDuE9/XeB/BUyQ/4n3QfiUK/6W4U/VpdsNqyyK297SkTmS3ciniiEvKfLPu7Q/qLq3ql9uGGzbS73cBtupXBRi4DWTSdR5/jUJSIhLXIuUczKnjFuW63gV/qm/lUN6BdGZvUBbDW6xxVt027Yd+VUeXZEI+pCzG9XrftJbBD6pnKfq2VsX4ucQ3w3RzEkflLJBN/AEx8VgIOmhimhOLkL/VQtf6/NMp4BT8OhXpwzryj72hebyogGZoixVz/9gE72fvkqyZIh/9wKanmVlFoe2ZUZrGE58D/e3iziEus/WIj486EkPKRkEEmkNNAHUqS+gy9/4fLu7AJfMfIyGd3cUW8lgwIwit0nun197FIlNDo5CLgY5F4CtJb9E+wjM4gO3GA8FDLg8Wxos0HIXPt9BJAjzKUakpIG0t3mtmflonMjCdkVZwdHQsJBLrZ8bA5iShzh5UOSdmtWXbfwj7TVuCHsjwxsXeqInDhV1BdpX+a8xUNsVro7MIv8= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(7416014)(36860700016)(1800799024)(6133799003)(11063799006)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: xuJZnwLWaXvYKDLnZYC2iN1MCVTIoSz1uWjJbWDO43JlV9t1Wmkts25k77+aivdQiqViUouZHE3t7x2a45p0Am8IP4Nk9lSS1WExEAvqNsvDC+rRcLircwlhhD5J960Ox1Y+lu3dZ1nQ0q/lc/ZKIObdTDezFn1uVZEC5YT4/8Z2ebS4oVezNvwy8Y5X1r9Gbh8zCJRo2oih/38q7DpxSV6uhOeg7zQFZnvlck0G9YAZkz6+AXPujFUdx/lDFPmgG9KKmNieDDNJhR/olurK1Pj2hZYmuNQTgBo83ihhW+a8Q0T8C2+WMrrQIdX3ifH3/WUCjrI/BC4DjlYOTKM//Al/uGwgGL/UBP9YRhZd0Jm8qOqzW1qH40x9EVEPE0KyRVXD9xXslmO06TbnOtwK90QRZYKtU20R3ObjXlMJTEslHl0/ei3adNqTsmGXfT5y X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2026 11:12:35.3165 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 00061c75-2307-47c6-0d65-08deb729dc86 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8959 Content-Type: text/plain; charset="utf-8" From: Or Har-Toov Extend port-level resource registration to satellite PF vports. Signed-off-by: Or Har-Toov Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/esw/devlink_port.c | 31 +++++++++++++------ 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c b/d= rivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c index 05d89769b917..6e50311faa27 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c @@ -176,14 +176,28 @@ static const struct devlink_port_ops mlx5_esw_dl_sf_p= ort_ops =3D { }; =20 static int mlx5_esw_devlink_port_res_register(struct mlx5_eswitch *esw, - struct devlink_port *dl_port) + struct devlink_port *dl_port, + u16 vport_num) { struct devlink_resource_size_params size_params; struct mlx5_core_dev *dev =3D esw->dev; u16 max_sfs, sf_base_id; int err; =20 - err =3D mlx5_esw_sf_max_hpf_functions(dev, &max_sfs, &sf_base_id); + if (vport_num !=3D MLX5_VPORT_HOST_PF && + !mlx5_esw_is_spf_vport(esw, vport_num)) + return 0; + + if (vport_num =3D=3D MLX5_VPORT_HOST_PF) { + err =3D mlx5_esw_sf_max_hpf_functions(dev, &max_sfs, + &sf_base_id); + } else { + int spf_idx =3D mlx5_esw_spf_vport_to_idx(esw, vport_num); + + err =3D mlx5_esw_sf_max_spf_functions(dev, spf_idx, &max_sfs, + &sf_base_id); + } + if (err) return err; =20 @@ -232,14 +246,11 @@ int mlx5_esw_offloads_devlink_port_register(struct ml= x5_eswitch *esw, struct mlx if (err) goto rate_err; =20 - if (vport_num =3D=3D MLX5_VPORT_HOST_PF) { - err =3D mlx5_esw_devlink_port_res_register(esw, - &dl_port->dl_port); - if (err) - mlx5_core_dbg(dev, - "Failed to register port resources: %d\n", - err); - } + err =3D mlx5_esw_devlink_port_res_register(esw, &dl_port->dl_port, + vport_num); + if (err) + mlx5_core_dbg(dev, "Failed to register port resources: %d\n", + err); =20 return 0; =20 --=20 2.44.0 From nobody Sun May 24 21:37:40 2026 Received: from PH7PR06CU001.outbound.protection.outlook.com (mail-westus3azon11010019.outbound.protection.outlook.com [52.101.201.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CFCA37CD4D; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Simon Horman" , Adithya Jayachandran , Jiri Pirko , Moshe Shemesh , Or Har-Toov , Shay Drori , Parav Pandit , Daniel Jurgens , Kees Cook , Cosmin Ratiu , Carolina Jubran , , , , Gal Pressman Subject: [PATCH net-next 10/12] net/mlx5: Support state get/set for satellite PF ports Date: Thu, 21 May 2026 14:08:41 +0300 Message-ID: <20260521110843.367329-11-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260521110843.367329-1-tariqt@nvidia.com> References: <20260521110843.367329-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CB:EE_|DS0PR12MB8414:EE_ X-MS-Office365-Filtering-Correlation-Id: cb90d2aa-126e-444b-fa89-08deb729df6f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|7416014|376014|1800799024|82310400026|18002099003|22082099003|56012099003|3023799007|11063799006|6133799003; X-Microsoft-Antispam-Message-Info: 3P8ass9NQCYhnfXsKXCZLjeaXeAgtnKg5j22aUCpZDDixzqXz0v4XUQGmv9lU4rJL09X4iJIzy8aBavAJFllUj0s9eTdOmYArJUGbV95pBPsE0ZJ5BdpfvSEbfkDunW7uxUBqQoODww6aSeBZF/YhaT2L/pGjQ4KdhplmT/lx/pQdReIM8WhjWE2+UsHLZnyDYQxOQohLG/ix7u90+SnvZjI/cY4rntId0Bi6qZrcNZT1dtVf8YN1snmkDDCAbGcJFI5caT7WxALaqE4s8bpXYSwsa23RdzWnfLaxsEMwBrDSK5TrfdG0d2xETViM5dUWihnsIBNoAixXVmX1FNe+zNYXrgt4oEl05y35wDh8hValE5gWcaESUoCYz7DdrVBO1RjHMmssRWfTnO3e2ecq+uaWVx7tKhnJLVOQ6yJQ1HgDvT4/FeB1xh91OF8YzVhynsfFyn/wkwVpnU8O3tQsadGVlnrZhsIT3Iz42m1TJhY1eXcjurV9R7UhofZj75/E8XEYpO7eezEiTvdN30AjVMlkcGuTlsKhYCgwPDLUk2VuEzIuhYxtakR5DSy3C/TVxiPs2E8dSTnxytGqTLzO1Ll281xJtlIF2tNiVyhYfDOXG2d82B4EnvU92+0aEnKeuMqsR8PQWwAdFb95+wFaGDh3D/P1PnqWqZoRxX/Mf0NVOBLMOHm/v4rafZdAauvh2bIeZmT6HLcqaySFaq6Wc13r7aELoEd29N3ObLjaeM= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(7416014)(376014)(1800799024)(82310400026)(18002099003)(22082099003)(56012099003)(3023799007)(11063799006)(6133799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jfHIYkfitbQVrb+v693CeqwGiG3JelyIL9jU7iXOMSuRPRR3nHjMuxtGfsuOpl2s23K/VfiNSQFzMRLcF10VAsHAQwNw/YsyR/8BG9rWR1YKDDs6fhxOHzRwM7RkQ0udAhx+jK07uH41PimdRZgLc1yp3gWg1odJn4y6NBgkg4j1xt8WiSLIGL/OiruOz9imN7LR/9dk6JBG8r7EE6XrWHOpBGSFDaGWNPd+oBzjhPLWN8g0a6/NLmIoeL8KkywVma9vLBFCxWV70iChRPazjTelSKm+C8NGALSTXXzZ/PeeFd3fG03iVxl2RPuTPTineU4CysaNEoN+La5DVJhQg8700g9iDepT4EsSXGnW/+nFx4D1JlZ9zf2ULSx2rqB5dwYuTpJ2E6IInhwMYD1o42kemWuX1gGwDamlRjtYWOeXP0xsyYso4r/KVEx4/J4O X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2026 11:12:40.2045 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cb90d2aa-126e-444b-fa89-08deb729df6f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CB.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8414 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Extend mlx5_devlink_pf_port_fn_state_get() to support satellite PF vports by querying their vhca_state from the query_esw_functions output using the vport's vhca_id. Extend mlx5_devlink_pf_port_fn_state_set() to support satellite PFs by using the generic mlx5_esw_pf_enable/disable_hca() functions. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/eswitch.c | 31 +++++++++++++++++-- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 4 +++ .../mellanox/mlx5/core/eswitch_offloads.c | 28 +++++++++++------ 3 files changed, 52 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index 8bee014140b8..9f82fc4dbf43 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -1187,6 +1187,33 @@ mlx5_esw_get_host_pf_info(struct mlx5_core_dev *dev,= const u32 *out) return mlx5_esw_host_pf_from_host_params(entry); } =20 +bool mlx5_esw_get_spf_disabled(struct mlx5_core_dev *dev, const u32 *out, + u16 vhca_id) +{ + int num_entries; + const u8 *entry; + int i; + + num_entries =3D MLX5_GET(query_esw_functions_out, out, net_function_num); + entry =3D MLX5_ADDR_OF(query_esw_functions_out, out, net_function_params); + + for (i =3D 0; i < num_entries; i++) { + u16 entry_vhca_id =3D MLX5_GET(network_function_params, + entry, vhca_id); + + if (entry_vhca_id =3D=3D vhca_id) { + int state; + + state =3D MLX5_GET(network_function_params, entry, + vhca_state); + return state !=3D MLX5_VHCA_STATE_IN_USE; + } + entry +=3D MLX5_UN_SZ_BYTES(net_function_params); + } + + return true; +} + static int mlx5_esw_host_functions_enabled_query(struct mlx5_eswitch *esw) { struct mlx5_esw_pf_info host_pf_info; @@ -1454,7 +1481,7 @@ static int mlx5_eswitch_load_ec_vf_vports(struct mlx5= _eswitch *esw, u16 num_ec_v return err; } =20 -static int mlx5_esw_pf_enable_hca(struct mlx5_core_dev *dev, u16 vport_num) +int mlx5_esw_pf_enable_hca(struct mlx5_core_dev *dev, u16 vport_num) { struct mlx5_eswitch *esw =3D dev->priv.eswitch; struct mlx5_vport *vport; @@ -1480,7 +1507,7 @@ static int mlx5_esw_pf_enable_hca(struct mlx5_core_de= v *dev, u16 vport_num) return 0; } =20 -static int mlx5_esw_pf_disable_hca(struct mlx5_core_dev *dev, u16 vport_nu= m) +int mlx5_esw_pf_disable_hca(struct mlx5_core_dev *dev, u16 vport_num) { struct mlx5_eswitch *esw =3D dev->priv.eswitch; struct mlx5_vport *vport; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index 7da1a888aa7c..1d8e2486d518 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -671,6 +671,10 @@ bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *d= ev0, const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev); struct mlx5_esw_pf_info mlx5_esw_get_host_pf_info(struct mlx5_core_dev *de= v, const u32 *out); +bool mlx5_esw_get_spf_disabled(struct mlx5_core_dev *dev, const u32 *out, + u16 vhca_id); +int mlx5_esw_pf_enable_hca(struct mlx5_core_dev *dev, u16 vport_num); +int mlx5_esw_pf_disable_hca(struct mlx5_core_dev *dev, u16 vport_num); int mlx5_esw_host_pf_enable_hca(struct mlx5_core_dev *dev); int mlx5_esw_host_pf_disable_hca(struct mlx5_core_dev *dev); =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index c229a96a111f..59446c444570 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -4961,10 +4961,11 @@ int mlx5_devlink_pf_port_fn_state_get(struct devlin= k_port *port, struct netlink_ext_ack *extack) { struct mlx5_vport *vport =3D mlx5_devlink_port_vport_get(port); - struct mlx5_esw_pf_info host_pf_info; + struct mlx5_eswitch *esw =3D vport->dev->priv.eswitch; const u32 *query_out; + bool pf_disabled; =20 - if (vport->vport !=3D MLX5_VPORT_HOST_PF) { + if (mlx5_eswitch_is_vf_vport(esw, vport->vport)) { NL_SET_ERR_MSG_MOD(extack, "State get is not supported for VF"); return -EOPNOTSUPP; } @@ -4976,11 +4977,19 @@ int mlx5_devlink_pf_port_fn_state_get(struct devlin= k_port *port, if (IS_ERR(query_out)) return PTR_ERR(query_out); =20 - host_pf_info =3D mlx5_esw_get_host_pf_info(vport->dev, query_out); + if (vport->vport =3D=3D MLX5_VPORT_HOST_PF) { + struct mlx5_esw_pf_info host_pf_info; + + host_pf_info =3D mlx5_esw_get_host_pf_info(vport->dev, + query_out); + pf_disabled =3D host_pf_info.pf_disabled; + } else { + pf_disabled =3D mlx5_esw_get_spf_disabled(vport->dev, query_out, + vport->vhca_id); + } =20 - *opstate =3D host_pf_info.pf_disabled ? - DEVLINK_PORT_FN_OPSTATE_DETACHED : - DEVLINK_PORT_FN_OPSTATE_ATTACHED; + *opstate =3D pf_disabled ? DEVLINK_PORT_FN_OPSTATE_DETACHED : + DEVLINK_PORT_FN_OPSTATE_ATTACHED; =20 kvfree(query_out); return 0; @@ -4991,9 +5000,10 @@ int mlx5_devlink_pf_port_fn_state_set(struct devlink= _port *port, struct netlink_ext_ack *extack) { struct mlx5_vport *vport =3D mlx5_devlink_port_vport_get(port); + struct mlx5_eswitch *esw =3D vport->dev->priv.eswitch; struct mlx5_core_dev *dev; =20 - if (vport->vport !=3D MLX5_VPORT_HOST_PF) { + if (mlx5_eswitch_is_vf_vport(esw, vport->vport)) { NL_SET_ERR_MSG_MOD(extack, "State set is not supported for VF"); return -EOPNOTSUPP; } @@ -5002,9 +5012,9 @@ int mlx5_devlink_pf_port_fn_state_set(struct devlink_= port *port, =20 switch (state) { case DEVLINK_PORT_FN_STATE_ACTIVE: - return mlx5_esw_host_pf_enable_hca(dev); + return mlx5_esw_pf_enable_hca(dev, vport->vport); case DEVLINK_PORT_FN_STATE_INACTIVE: - return mlx5_esw_host_pf_disable_hca(dev); + return mlx5_esw_pf_disable_hca(dev, vport->vport); default: return -EOPNOTSUPP; } --=20 2.44.0 From nobody Sun May 24 21:37:40 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012041.outbound.protection.outlook.com [52.101.43.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E4203C4577; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Simon Horman" , Adithya Jayachandran , Jiri Pirko , Moshe Shemesh , Or Har-Toov , Shay Drori , Parav Pandit , Daniel Jurgens , Kees Cook , Cosmin Ratiu , Carolina Jubran , , , , Gal Pressman Subject: [PATCH net-next 11/12] net/mlx5: Add FDB peer miss rules for satellite PFs Date: Thu, 21 May 2026 14:08:42 +0300 Message-ID: <20260521110843.367329-12-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260521110843.367329-1-tariqt@nvidia.com> References: <20260521110843.367329-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7A:EE_|SJ5PPF000ACABD1:EE_ X-MS-Office365-Filtering-Correlation-Id: 8be5823d-8fed-4d7f-106c-08deb729e32a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700016|7416014|82310400026|56012099003|11063799006|22082099003|18002099003|6133799003; X-Microsoft-Antispam-Message-Info: A8MqFl5UEecu1E6N+vh8x9T7JZFxy2yimat/2CLok6tpWssj42r0DxVkICOMPgLpAdjsQBWTxxqrS0jH9aBBubtmmVWwJ/ociCFecwYg9XeDARfGq7Rb6eYB+/urazszArghDrvsbpt1io2v6u9mmiVrSgHI5YtYjIXdwQwRB6DG+I1Pfp0qoTYKZIG0K2fEjPkv2nw+YK0D+kdg5cs0O14CUr8HBOt4nzMiuKU01S/wU6hhY7VhoI0f9k9tK6luBU6wg8PHPddIblDGZM7gmou9DtNQWlOTWUOU1Qpcp6Ysb75Nx0svQvzfKWR/4xS76QPIR9Qm10dJb13sakSQHwjKJIDbVAZVe6wQK/xy9TDdfzbg1iq4mSSo08CRzde5y275HBiU4IY/b+0GMQPb/MEX6yhpCsDDB7QpzNy5D7dGmswaJIJnEMAJFTGNVRE5TvO43g4l+2IC4pNqC8oEBtTGy2tym4T6nesWSM+p1z8aiW1fADz4i5TLhy4Y9EXsVrkHLmiE1CjcngfFafoBKoEuQixI/CZ0MHK2MJoDmyKlAZYEeuW4pCIDFVCBAjq2/tNGPYYeXPAqB55Md0fM4V6ch8GdsV8wFUxw5GV/mSvjEDQL61cQPTG4xKUIOidsaBsHpV6lXw+Sm6c3bN6IsxWAEoIICvykVdyWrycEyFGhX4CUPRomc9eX5rclP+Uuy8j84FsOW+72hLDWmhAg3gq0UiXMSeXuh1awGyYzkKM= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700016)(7416014)(82310400026)(56012099003)(11063799006)(22082099003)(18002099003)(6133799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: kAdYx7Xo44IogNdxqLMFORsCE4yCWbM6lvzVAKvOUQhNMKZzZKe+6HP3RtOZ+UJitmcL1p+YVuxvR1hU4CNqBj8ymcXXrEBS3lcK3chwLnjkxkli7qFfVeULCXR22wTslGuje6e5hDezn4ElCRn7KI78/bbGR3NJJc+QzMIdotrIdLnr0+II6YoH+UxFgsWCCh96BYC3rmj/PhQCclq7KYQYCJU1yLbAcQCXULe6botOVM/TMfjyCPI9yRlB/IRIFZqrG6iLgY0qfB3ek49nThvrlebNAgig3rckvrWod+HloTCup3QUPusunQH43BYK4W6WKL7966da+mBzbLUnqejuJKVYcvqN6/4OfP4PVqObRJdeApXLI3QN6c2hmbl61HGf/3vIgtt9nQmuIhpst7OB/FGtj1TNP5fZHDl4Q3YwHe8yjw6cT1l3KEsyWJwL X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2026 11:12:46.4194 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8be5823d-8fed-4d7f-106c-08deb729e32a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ5PPF000ACABD1 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Add satellite PF (SPF) vports to the FDB peer miss rules flow. Introduce mlx5_esw_for_each_spf_vport() macro to iterate SPF vports. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 10 +++++++++ .../mellanox/mlx5/core/eswitch_offloads.c | 22 ++++++++++++++++++- 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index 1d8e2486d518..c8d6c94a4475 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -790,6 +790,16 @@ void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch= *esw); MLX5_CAP_GEN_2((esw->dev), ec_vf_vport_base) +\ (last) - 1) =20 +/* SPF vport numbers are not contiguous, iterate via the spfs array + * and look up each vport in the xarray. + */ +#define mlx5_esw_for_each_spf_vport(esw, index, vport) \ + for ((index) =3D 0; \ + (index) < (esw)->esw_funcs.num_spfs && \ + ((vport) =3D xa_load(&(esw)->vports, \ + (esw)->esw_funcs.spfs[(index)].vport_num)); \ + (index)++) + #define mlx5_esw_for_each_rep(esw, i, rep) \ xa_for_each(&((esw)->offloads.vport_reps), i, rep) =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 59446c444570..355d27934fb4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -1231,6 +1231,19 @@ static int esw_add_fdb_peer_miss_rules(struct mlx5_e= switch *esw, flows[peer_vport->index] =3D flow; } =20 + mlx5_esw_for_each_spf_vport(peer_esw, i, peer_vport) { + esw_set_peer_miss_rule_source_port(esw, peer_esw, spec, + peer_vport->vport); + + flow =3D mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw), + spec, &flow_act, &dest, 1); + if (IS_ERR(flow)) { + err =3D PTR_ERR(flow); + goto add_ecpf_flow_err; + } + flows[peer_vport->index] =3D flow; + } + if (mlx5_ecpf_vport_exists(peer_dev)) { peer_vport =3D mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_ECPF); MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF); @@ -1299,7 +1312,11 @@ static int esw_add_fdb_peer_miss_rules(struct mlx5_e= switch *esw, mlx5_del_flow_rules(flows[peer_vport->index]); } add_ecpf_flow_err: - + mlx5_esw_for_each_spf_vport(peer_esw, i, peer_vport) { + if (!flows[peer_vport->index]) + continue; + mlx5_del_flow_rules(flows[peer_vport->index]); + } if (mlx5_core_is_ecpf_esw_manager(peer_dev) && mlx5_esw_host_functions_enabled(peer_dev)) { peer_vport =3D mlx5_eswitch_get_vport(peer_esw, @@ -1343,6 +1360,9 @@ static void esw_del_fdb_peer_miss_rules(struct mlx5_e= switch *esw, mlx5_del_flow_rules(flows[peer_vport->index]); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Simon Horman" , Adithya Jayachandran , Jiri Pirko , Moshe Shemesh , Or Har-Toov , Shay Drori , Parav Pandit , Daniel Jurgens , Kees Cook , Cosmin Ratiu , Carolina Jubran , , , , Gal Pressman Subject: [PATCH net-next 12/12] net/mlx5: Add SPF function type for page management Date: Thu, 21 May 2026 14:08:43 +0300 Message-ID: <20260521110843.367329-13-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260521110843.367329-1-tariqt@nvidia.com> References: <20260521110843.367329-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7B:EE_|CY3PR12MB9679:EE_ X-MS-Office365-Filtering-Correlation-Id: 4354091d-a0aa-4813-08f0-08deb729e701 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|7416014|376014|82310400026|18002099003|22082099003|56012099003|11063799006; X-Microsoft-Antispam-Message-Info: gwd+KIoou5WJLxwGx/uWR5BUaO38P7OqAdl0/3VylO2vqH1qeEyEHku6PdgxkTf546e11CNMJeQ9vkn6o8s1plPTy1Qrn5XrnrtR0xRUvNT52UwZxNE/2m278U/VFfTx9qIR5oEyofbO1Q1GkkkjAoobl9IUoq6BHbKgFoLHgR1OiwPMRo9TMcuYHXyrro0jNt2A2z/KXqIorwVSJyT3rldJPqwuLwuIKJUUJOq1EdUY4Sgtv2VHhYCdUX/XMFLWnTlSW/fuiQ7mO4zhruqyY1f8X2zwY8Bwb6B8yUohW48/q29F6Hcb1zmKKEKdmEbmITMuUETO/xB+QcBwVL5Etk+mNseQMDgBF+L2MJq3gr2MvNwEugtMY1Dpernx4XyV5SWfHsCWuTOJww2zxAKW26KiCkxjKUYJUUvoCAPXs3LPU/w9I3STwKTzsn6ilJVUshritx48G+vX9+qhuocxf3ZwbUFYnCThyFyLMwHc+MMphExUOU2ON8HBL1Ekpm4fhRc+w7Hn5r7H4dsj2bKb3F5nUkNgBszOBM4bYj72SfGJ7WBTpwgSuS6LI3tPRty8RjUGqFE/jGQWEKDMS0foVMVAG3zXEIzNeUnj15sJTvUksoiZJ6WSneMgXJEQoYrMn/WH29WVYV+BV9o3kTSycwepM+Q+WzXdVQ097hQstEvMcIB8mKfV+iU2P59zpjn9wS1Jrw+1cqMSyVBD1+GQKp4VGhQZAWR1FC1nXswiYbc= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(7416014)(376014)(82310400026)(18002099003)(22082099003)(56012099003)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: XcTqnetZ4yzxBPOI47por7CCBK4pIV7dn2W0+LSO290DjmYGPNuBcQA/MCx7k8XcqATOg28RvpS4y/GNwxKPn6IxIX/EM5ujHfz/t7zwp4HmwhS3hrhbSIWiJEAmFecK/ekJcNLcSz+YM6JsTBxjPTQPdCNhzETNk7v9JfPMvnA0jxTXyqlLkWFhAKCETpCC7WoaXHpgG1iKNnihp2BRSiyLloxyRCSaFduIdE5a6+qOzkRID7TaJWNzVd110XLomcnhRDJJ/2r5tAkuqS6EM8uWGUXbw3oL+7lDjvZmfM1hgyp+61Cto4Mo2IYcPsz68mRT0jQiHHnvisZu5lZwdGbewFeakxWVsqlKbb9juvffeMqsgfm63tN7mXcTUNVW/TC5jjJPGfUfL6Fk/ebeVPp6xSexNFK90tWKQyjpnI0qV0u6zarGeGAn4S1WEZyW X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2026 11:12:52.8600 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4354091d-a0aa-4813-08f0-08deb729e701 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR12MB9679 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Add MLX5_SPF to enum mlx5_func_type so SPFs get their own page counter, and add the corresponding WARN check at page cleanup. Wait for SPF pages to be reclaimed during ECPF teardown, alongside the existing host PF and VF page waits. SPF page requests are always identified by vhca_id, so the legacy func_id_to_type() path is not reached for satellite PFs. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/debugfs.c | 3 +++ drivers/net/ethernet/mellanox/mlx5/core/ecpf.c | 5 +++++ drivers/net/ethernet/mellanox/mlx5/core/eswitch.c | 2 ++ drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c | 3 +++ include/linux/mlx5/driver.h | 1 + 5 files changed, 14 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/debugfs.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/debugfs.c index 6347957fefcb..30be2b631e7c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/debugfs.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/debugfs.c @@ -316,6 +316,8 @@ void mlx5_pages_by_func_type_debugfs_init(struct mlx5_c= ore_dev *dev) &dev->priv.page_counters[MLX5_SF]); debugfs_create_u32("fw_pages_host_pf", 0400, pages, &dev->priv.page_counters[MLX5_HOST_PF]); + debugfs_create_u32("fw_pages_spfs", 0400, pages, + &dev->priv.page_counters[MLX5_SPF]); } =20 void mlx5_pages_by_func_type_debugfs_cleanup(struct mlx5_core_dev *dev) @@ -329,6 +331,7 @@ void mlx5_pages_by_func_type_debugfs_cleanup(struct mlx= 5_core_dev *dev) debugfs_lookup_and_remove("fw_pages_ec_vfs", pages); debugfs_lookup_and_remove("fw_pages_sfs", pages); debugfs_lookup_and_remove("fw_pages_host_pf", pages); + debugfs_lookup_and_remove("fw_pages_spfs", pages); } =20 static u64 qp_read_field(struct mlx5_core_dev *dev, struct mlx5_core_qp *q= p, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/ecpf.c b/drivers/net/e= thernet/mellanox/mlx5/core/ecpf.c index 350c47d3643b..9839f1a58640 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/ecpf.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/ecpf.c @@ -102,6 +102,11 @@ void mlx5_ec_cleanup(struct mlx5_core_dev *dev) if (err) mlx5_core_warn(dev, "Timeout reclaiming external host PF pages err(%d)\n= ", err); =20 + err =3D mlx5_wait_for_pages(dev, &dev->priv.page_counters[MLX5_SPF]); + if (err) + mlx5_core_warn(dev, "Timeout reclaiming SPF pages err(%d)\n", + err); + err =3D mlx5_wait_for_pages(dev, &dev->priv.page_counters[MLX5_VF]); if (err) mlx5_core_warn(dev, "Timeout reclaiming external host VFs pages err(%d)\= n", err); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index 9f82fc4dbf43..5df3ec641ae3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -863,6 +863,8 @@ esw_vport_to_func_type(struct mlx5_eswitch *esw, struct= mlx5_vport *vport) return MLX5_SF; if (xa_get_mark(&esw->vports, vport_num, MLX5_ESW_VPT_VF)) return MLX5_VF; + if (mlx5_esw_is_spf_vport(esw, vport_num)) + return MLX5_SPF; return MLX5_EC_VF; } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c b/drivers/= net/ethernet/mellanox/mlx5/core/pagealloc.c index ce2f7fa9bd48..7fef3a7fee6e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c @@ -885,6 +885,9 @@ int mlx5_reclaim_startup_pages(struct mlx5_core_dev *de= v) WARN(dev->priv.page_counters[MLX5_HOST_PF], "External host PF FW pages counter is %d after reclaiming all pages\= n", dev->priv.page_counters[MLX5_HOST_PF]); + WARN(dev->priv.page_counters[MLX5_SPF], + "SPFs FW pages counter is %d after reclaiming all pages\n", + dev->priv.page_counters[MLX5_SPF]); WARN(dev->priv.page_counters[MLX5_EC_VF], "EC VFs FW pages counter is %d after reclaiming all pages\n", dev->priv.page_counters[MLX5_EC_VF]); diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 9a4bb25d8e0a..b1871c0821d0 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -557,6 +557,7 @@ enum mlx5_func_type { MLX5_VF, MLX5_SF, MLX5_HOST_PF, + MLX5_SPF, MLX5_EC_VF, MLX5_FUNC_TYPE_NUM, MLX5_FUNC_TYPE_NONE =3D MLX5_FUNC_TYPE_NUM, --=20 2.44.0