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charset="utf-8" Define SMCCC Arch function IDs for CLEAN_INV_MEMREGION and its ATTRIBUTES call, and add RATE_LIMITED/BUSY return codes from DEN0028 for callers that need transient error handling. Signed-off-by: Srirangan Madhavan --- include/linux/arm-smccc.h | 17 +++++++++++++++-- tools/include/linux/arm-smccc.h | 17 +++++++++++++++-- 2 files changed, 30 insertions(+), 4 deletions(-) diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 50b47eba7d01..cca9adbcc433 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -105,6 +105,18 @@ ARM_SMCCC_SMC_32, \ 0, 0x3fff) =20 +#define ARM_SMCCC_ARCH_CLEAN_INV_MEMREGION \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x5) + +#define ARM_SMCCC_ARCH_CLEAN_INV_MEMREGION_ATTRIBUTES \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x6) + #define ARM_SMCCC_VENDOR_HYP_CALL_UID_FUNC_ID \ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ ARM_SMCCC_SMC_32, \ @@ -294,13 +306,14 @@ 0x53) =20 /* - * Return codes defined in ARM DEN 0070A - * ARM DEN 0070A is now merged/consolidated into ARM DEN 0028 C + * Return codes defined by Arm SMCCC (DEN0028). */ #define SMCCC_RET_SUCCESS 0 #define SMCCC_RET_NOT_SUPPORTED -1 #define SMCCC_RET_NOT_REQUIRED -2 #define SMCCC_RET_INVALID_PARAMETER -3 +#define SMCCC_RET_RATE_LIMITED -4 +#define SMCCC_RET_BUSY -5 =20 #ifndef __ASSEMBLY__ =20 diff --git a/tools/include/linux/arm-smccc.h b/tools/include/linux/arm-smcc= c.h index 63ce9bebccd3..65fd4630e739 100644 --- a/tools/include/linux/arm-smccc.h +++ b/tools/include/linux/arm-smccc.h @@ -96,6 +96,18 @@ ARM_SMCCC_SMC_32, \ 0, 0x3fff) =20 +#define ARM_SMCCC_ARCH_CLEAN_INV_MEMREGION \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x5) + +#define ARM_SMCCC_ARCH_CLEAN_INV_MEMREGION_ATTRIBUTES \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x6) + #define ARM_SMCCC_VENDOR_HYP_CALL_UID_FUNC_ID \ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ ARM_SMCCC_SMC_32, \ @@ -182,12 +194,13 @@ 0x53) =20 /* - * Return codes defined in ARM DEN 0070A - * ARM DEN 0070A is now merged/consolidated into ARM DEN 0028 C + * Return codes defined by Arm SMCCC (DEN0028). */ #define SMCCC_RET_SUCCESS 0 #define SMCCC_RET_NOT_SUPPORTED -1 #define SMCCC_RET_NOT_REQUIRED -2 #define SMCCC_RET_INVALID_PARAMETER -3 +#define SMCCC_RET_RATE_LIMITED -4 +#define SMCCC_RET_BUSY -5 =20 #endif /*__LINUX_ARM_SMCCC_H*/ --=20 2.43.0 From nobody Sun May 24 21:37:41 2026 Received: from CO1PR03CU002.outbound.protection.outlook.com (mail-westus2azon11010060.outbound.protection.outlook.com [52.101.46.60]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B19B346771 for ; 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charset="utf-8" Add an arm64 cache maintenance backend that discovers SMCCC cache clean+invalidate support, queries attributes, handles transient BUSY and RATE_LIMITED responses with bounded retries, and registers with the generic cache coherency framework. Signed-off-by: Srirangan Madhavan --- MAINTAINERS | 1 + arch/arm64/mm/Makefile | 1 + arch/arm64/mm/cache_maint.c | 180 ++++++++++++++++++++++++++++++++++++ 3 files changed, 182 insertions(+) create mode 100644 arch/arm64/mm/cache_maint.c diff --git a/MAINTAINERS b/MAINTAINERS index 2fb1c75afd16..33c35f8e6e40 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -25383,6 +25383,7 @@ M: Jonathan Cameron S: Maintained T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ F: Documentation/devicetree/bindings/cache/ +F: arch/arm64/mm/cache_maint.c F: drivers/cache F: include/linux/cache_coherency.h F: lib/cache_maint.c diff --git a/arch/arm64/mm/Makefile b/arch/arm64/mm/Makefile index c26489cf96cd..b247dc5dfd45 100644 --- a/arch/arm64/mm/Makefile +++ b/arch/arm64/mm/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_TRANS_TABLE) +=3D trans_pgd-asm.o obj-$(CONFIG_DEBUG_VIRTUAL) +=3D physaddr.o obj-$(CONFIG_ARM64_MTE) +=3D mteswap.o obj-$(CONFIG_ARM64_GCS) +=3D gcs.o +obj-$(CONFIG_ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION) +=3D cache_maint.o KASAN_SANITIZE_physaddr.o +=3D n =20 obj-$(CONFIG_KASAN) +=3D kasan_init.o diff --git a/arch/arm64/mm/cache_maint.c b/arch/arm64/mm/cache_maint.c new file mode 100644 index 000000000000..ea7dd30d5dfa --- /dev/null +++ b/arch/arm64/mm/cache_maint.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 NVIDIA Corporation + * + * Arm64 cache maintenance provider using SMCCC cache clean+invalidate cal= ls. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SMCCC_CACHE_MAX_RETRIES 5 +#define SMCCC_CACHE_MAX_DELAY_US 20000 + +/* DEN0028 v1.7: bit[0] =3D=3D 1 means implementation flushes all caches g= lobally */ +#define SMCCC_CACHE_ATTR_GLOBAL_OP BIT(0) + +struct arm64_smccc_cache { + /* Must be first member */ + struct cache_coherency_ops_inst cci; + struct mutex lock; /* Serializes SMCCC cache maintenance calls. */ + u32 latency_us; + u32 rate_limit; + bool global_op; + u64 global_flush_gen; +}; + +static struct arm64_smccc_cache *arm64_smccc_cache; + +static int smccc_cache_status_to_errno(s32 status) +{ + switch (status) { + case SMCCC_RET_SUCCESS: + return 0; + case SMCCC_RET_NOT_SUPPORTED: + case SMCCC_RET_NOT_REQUIRED: + return -EOPNOTSUPP; + case SMCCC_RET_INVALID_PARAMETER: + return -EINVAL; + case SMCCC_RET_RATE_LIMITED: + return -EAGAIN; + case SMCCC_RET_BUSY: + return -EBUSY; + default: + return -EIO; + } +} + +static int smccc_cache_delay_us(const struct arm64_smccc_cache *cache) +{ + u64 delay_us =3D 0; + + if (cache->rate_limit) + delay_us =3D DIV_ROUND_UP_ULL(USEC_PER_SEC, cache->rate_limit); + + if (cache->latency_us) + delay_us =3D max_t(u64, delay_us, cache->latency_us); + + if (!delay_us) + delay_us =3D 1000; + + return min_t(u64, delay_us, SMCCC_CACHE_MAX_DELAY_US); +} + +static int arm64_smccc_cache_wbinv(struct cache_coherency_ops_inst *cci, + struct cc_inval_params *invp) +{ + struct arm64_smccc_cache *cache =3D + container_of(cci, struct arm64_smccc_cache, cci); + struct arm_smccc_res res =3D {}; + int delay_us =3D smccc_cache_delay_us(cache); + u64 gen =3D 0; + s32 status; + int ret; + int i; + + if (!invp->size) + return -EINVAL; + + if (cache->global_op) + gen =3D READ_ONCE(cache->global_flush_gen); + + guard(mutex)(&cache->lock); + + /* + * If firmware reports a global operation type, a successful operation + * covers every request that was already waiting behind it. Skip if the + * generation advanced while this request was waiting to enter the + * serialized firmware call path. + */ + if (cache->global_op && gen !=3D READ_ONCE(cache->global_flush_gen)) + return 0; + + for (i =3D 0; i < SMCCC_CACHE_MAX_RETRIES; i++) { + /* Long firmware operations can trigger watchdog checks. */ + touch_nmi_watchdog(); + + arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_CLEAN_INV_MEMREGION, + invp->addr, invp->size, 0UL, &res); + status =3D (s32)res.a0; + ret =3D smccc_cache_status_to_errno(status); + if (!ret) { + if (cache->global_op) { + WRITE_ONCE(cache->global_flush_gen, + cache->global_flush_gen + 1); + } + return 0; + } + + if (ret !=3D -EBUSY && ret !=3D -EAGAIN) + return ret; + + usleep_range(delay_us, delay_us + 100); + } + + return -EBUSY; +} + +static const struct cache_coherency_ops arm64_smccc_cache_ops =3D { + .wbinv =3D arm64_smccc_cache_wbinv, +}; + +static int __init arm64_smccc_cache_init(void) +{ + struct arm_smccc_res res =3D {}; + s32 status; + int ret; + + if (arm_smccc_get_version() < ARM_SMCCC_VERSION_1_1) + return -ENODEV; + + if (arm_smccc_1_1_get_conduit() =3D=3D SMCCC_CONDUIT_NONE) + return -ENODEV; + + arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, + ARM_SMCCC_ARCH_CLEAN_INV_MEMREGION, &res); + status =3D (s32)res.a0; + if (status < 0) + return -ENODEV; + + arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, + ARM_SMCCC_ARCH_CLEAN_INV_MEMREGION_ATTRIBUTES, &res); + status =3D (s32)res.a0; + if (status < 0) + return -ENODEV; + + arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_CLEAN_INV_MEMREGION_ATTRIBUTES, &res); + status =3D (s32)res.a0; + if (status) + return -ENODEV; + + arm64_smccc_cache =3D + cache_coherency_ops_instance_alloc(&arm64_smccc_cache_ops, + struct arm64_smccc_cache, + cci); + if (!arm64_smccc_cache) + return -ENOMEM; + + mutex_init(&arm64_smccc_cache->lock); + arm64_smccc_cache->latency_us =3D lower_32_bits(res.a2); + arm64_smccc_cache->rate_limit =3D lower_32_bits(res.a3); + arm64_smccc_cache->global_op =3D !!(res.a1 & SMCCC_CACHE_ATTR_GLOBAL_OP); + + ret =3D cache_coherency_ops_instance_register(&arm64_smccc_cache->cci); + if (ret) { + cache_coherency_ops_instance_put(&arm64_smccc_cache->cci); + arm64_smccc_cache =3D NULL; + return ret; + } + + pr_info("SMCCC cache clean+invalidate provider registered\n"); + return 0; +} +arch_initcall(arm64_smccc_cache_init); --=20 2.43.0