[RFC PATCH 0/2] arm64: add SMCCC cache invalidation backend for memregion users

Srirangan Madhavan posted 2 patches 3 days, 13 hours ago
MAINTAINERS                     |   1 +
arch/arm64/mm/Makefile          |   1 +
arch/arm64/mm/cache_maint.c     | 180 ++++++++++++++++++++++++++++++++
include/linux/arm-smccc.h       |  17 ++-
tools/include/linux/arm-smccc.h |  17 ++-
5 files changed, 212 insertions(+), 4 deletions(-)
create mode 100644 arch/arm64/mm/cache_maint.c
[RFC PATCH 0/2] arm64: add SMCCC cache invalidation backend for memregion users
Posted by Srirangan Madhavan 3 days, 13 hours ago
This series adds an arm64 backend for memregion cache invalidation users
based on the Arm SMCCC cache clean+invalidate interface.

Per DEN0028, this interface targets systems where a Normal Cacheable
memory region can be modified in ways that are not handled by usual PE
coherency mechanisms, and where VA-based CMOs may be too slow or
insufficient for large ranges and/or system-cache implementations.

Representative use cases include device-backed memory state transitions
where stale CPU/system cache lines must be invalidated reliably (for
example secure erase, reset/offline flows, and dynamic memory
reconfiguration).

Patch 1 introduces the Arm SMCCC cache clean/invalidate function IDs and
transient return codes needed by callers [1].

Patch 2 adds an arm64 cache maintenance provider that:
- discovers SMCCC support and attributes at init time
- registers with the generic cache coherency framework used by
  cpu_cache_invalidate_memregion()
- handles transient BUSY/RATE_LIMITED responses with bounded retries
- coalesces waiters when firmware reports a global operation type

This patch set does not add a software fallback path; when firmware does
not implement the SMCCC cache maintenance interface, the provider is not
registered and existing behavior is preserved.

Reference:
[1] https://developer.arm.com/documentation/den0028/latest

Srirangan Madhavan (2):
  arm64: smccc: add cache clean/invalidate IDs and return codes
  arm64: mm: add SMCCC-backed cache invalidate provider

 MAINTAINERS                     |   1 +
 arch/arm64/mm/Makefile          |   1 +
 arch/arm64/mm/cache_maint.c     | 180 ++++++++++++++++++++++++++++++++
 include/linux/arm-smccc.h       |  17 ++-
 tools/include/linux/arm-smccc.h |  17 ++-
 5 files changed, 212 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm64/mm/cache_maint.c


base-commit: 3b3bea6d4b9c162f9e555905d96b8c1da67ecd5b
-- 
2.43.0
Re: [RFC PATCH 0/2] arm64: add SMCCC cache invalidation backend for memregion users
Posted by Jonathan Cameron 3 days, 9 hours ago
On Thu, 21 May 2026 07:30:45 +0000
Srirangan Madhavan <smadhavan@nvidia.com> wrote:

> This series adds an arm64 backend for memregion cache invalidation users
> based on the Arm SMCCC cache clean+invalidate interface.
> 
> Per DEN0028, this interface targets systems where a Normal Cacheable
> memory region can be modified in ways that are not handled by usual PE
> coherency mechanisms, and where VA-based CMOs may be too slow or
> insufficient for large ranges and/or system-cache implementations.
> 
> Representative use cases include device-backed memory state transitions
> where stale CPU/system cache lines must be invalidated reliably (for
> example secure erase, reset/offline flows, and dynamic memory
> reconfiguration).
> 
Hi Srirangan,

Great to see this moving forwards. I was wondering when it would
surface upstream :)

Usual thing for an RFC is to have some reference to why it is an RFC.
I'm not immediately spotting any open questions or dependencies to
stop this going upstream now (if review of actual code goes well).

So why RFC?  Is the spec still in beta?

> Patch 1 introduces the Arm SMCCC cache clean/invalidate function IDs and
> transient return codes needed by callers [1].
> 
> Patch 2 adds an arm64 cache maintenance provider that:
> - discovers SMCCC support and attributes at init time
> - registers with the generic cache coherency framework used by
>   cpu_cache_invalidate_memregion()
> - handles transient BUSY/RATE_LIMITED responses with bounded retries
> - coalesces waiters when firmware reports a global operation type
> 
> This patch set does not add a software fallback path; when firmware does
> not implement the SMCCC cache maintenance interface, the provider is not
> registered and existing behavior is preserved.

By which you mean it kicks out an error? This kind of hints there
might be a software fallback (assuming no other implementation has
registered). In many cases there isn't a safe software solution.

Jonathan

> 
> Reference:
> [1] https://developer.arm.com/documentation/den0028/latest
> 
> Srirangan Madhavan (2):
>   arm64: smccc: add cache clean/invalidate IDs and return codes
>   arm64: mm: add SMCCC-backed cache invalidate provider
> 
>  MAINTAINERS                     |   1 +
>  arch/arm64/mm/Makefile          |   1 +
>  arch/arm64/mm/cache_maint.c     | 180 ++++++++++++++++++++++++++++++++
>  include/linux/arm-smccc.h       |  17 ++-
>  tools/include/linux/arm-smccc.h |  17 ++-
>  5 files changed, 212 insertions(+), 4 deletions(-)
>  create mode 100644 arch/arm64/mm/cache_maint.c
> 
> 
> base-commit: 3b3bea6d4b9c162f9e555905d96b8c1da67ecd5b