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Thu, 21 May 2026 00:24:54 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Jonathan Corbet , Shuah Khan , Jiri Pirko , Simon Horman , "Saeed Mahameed" , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Borislav Petkov (AMD)" , Andrew Morton , Randy Dunlap , Thomas Gleixner , Petr Mladek , "Peter Zijlstra (Intel)" , "Tejun Heo" , Vlastimil Babka , Feng Tang , Christian Brauner , "Dave Hansen" , Dapeng Mi , Kees Cook , Marco Elver , Li RongQing , Eric Biggers , "Paul E. McKenney" , , , , , Gal Pressman , Dragos Tatulea , Jiri Pirko , Shay Drori , Moshe Shemesh Subject: [PATCH net-next 1/3] net/mlx5: Clear FW reset-in-progress bit before reload Date: Thu, 21 May 2026 10:24:32 +0300 Message-ID: <20260521072434.362624-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260521072434.362624-1-tariqt@nvidia.com> References: <20260521072434.362624-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E5F:EE_|DS7PR12MB6261:EE_ X-MS-Office365-Filtering-Correlation-Id: 431180ed-9e73-4cae-68e4-08deb70a1d45 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|376014|7416014|82310400026|22082099003|56012099003|18002099003|11063799006; X-Microsoft-Antispam-Message-Info: rFkd2NAdPHy0LxWGNX1MI7583EqqCqkM3wZ3/rGeKxArh0l6YsXyQNpNNDN3SzobLIWQPlH099fetIhEix8GOUknjv7jd2UF6HxU3KmhmR1l0sZvVIZYnddpBXQYDzCn+9UINe96c1znqxMMWw92MNP8p/QwLzmzpXFhRlyHG6rWImfJW41XtsOo3WC1qp9U9i02MbipVansMed1EI8NwMo4v3qQxd9YXhyqCWdo0dw0ExsOQ/Y8pektmw2RI2R1sPr1sEnX1TPtXw7G39NUD/FnDw83Mrke3YL8USErJQANnQ1ViTtg+gNxtgm8I7x+o2PNA6W6oyNj84CPMOxURGYx/d49PJ/mXDxzfownrdhl4v+BG7N5NAO7fbPopyOAjpCWxnECjNpfxcgfIXfPIjqK9vHhIbZbyYGRg2gSetYKoabQcupPUoCcoH9PIVSw4MQXxsmyZwkHKpAIabwwaJLmXJjFXCiOpOAPTUBCNCENsqN1XyaGTJrPyY+AR8OA/6/vrvT98o8Gh+03blhBdgJkZwtTOX6Ne6LroVw2Ll5qs0VAuucYDzynV4L7k1/nWS3AKtQJUd+HItR2w+No4e8BnwaG10XJ1d8+VD1mgNARFtmfsU3FmVCVHeJFO/53Ar7QvSh5pRdFR+bu3CM+YRZc1NnLIRrMyPCeIIbbnBZ2SVeoafFl8kvaz6rsG+PnUfZru0VFYyk8OXmRISd/SO+EPpCBA/9MPtO37LacjpM= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(376014)(7416014)(82310400026)(22082099003)(56012099003)(18002099003)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: odMayCZjGkBeqF19hxKslJhC1Fk0h8Mu0UA91FzGjBd4qbO45QEibWx0pNtA754IK5jomoWsRxKothuuJvIR2NqAH3z3wi0iEm4Y42IG1uayAuSMl2qtlkTBAIidlel1kndG4RLtaMKlxvcJOprBpcrP3hLifV2NVCaaJvhK9RXiHnM5ghkR2oahd0foimct3f3xUIJ0asBVuJDE4AqaO9JlMO4KTQWWbssL9sjfiTRGw4Uuf4XZC6jHHOoGt3eiGvZub7icjxxAYC2G8SFYYrwcso9o7gwsw2PFNlLRUGnVgGVsveTwgU1WBaeSGpyparJhaw8yk38S8CuCv8Rg/A8HlqznbvU7TN2vc2dAB6Q41JhIMI04qSHXq2jySANl9yFIW9/iwsYzRwQ8PM4WuaaNm1idz9AP3aTb/SRjFOuORT6NsnViX18mJsVZtGNw X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2026 07:25:20.1162 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 431180ed-9e73-4cae-68e4-08deb70a1d45 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E5F.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6261 Content-Type: text/plain; charset="utf-8" From: Mark Bloch mlx5 sets MLX5_FW_RESET_FLAGS_RESET_IN_PROGRESS when acknowledging a sync reset request. This bit blocks devlink reload and other devlink operations while the firmware reset is running, but it was kept set until after the driver reload finished. Clear the reset-in-progress bit once the reset unload flow is done and PCI access is back, before reloading the device. For a reset initiated through devlink, clear it before completing the reload waiter. For a reset reported through an asynchronous firmware event, keep the unload flow outside devl_lock, then take devl_lock before clearing the bit and reloading through the devl-locked load helper. Signed-off-by: Mark Bloch Reviewed-by: Shay Drori Reviewed-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/fw_reset.c | 28 +++++++++++-------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c b/drivers/n= et/ethernet/mellanox/mlx5/core/fw_reset.c index 07440c58713a..7283e5b49eed 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c @@ -238,24 +238,30 @@ static void mlx5_fw_reset_complete_reload(struct mlx5= _core_dev *dev) { struct mlx5_fw_reset *fw_reset =3D dev->priv.fw_reset; struct devlink *devlink =3D priv_to_devlink(dev); + int err; =20 /* if this is the driver that initiated the fw reset, devlink completed t= he reload */ if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) { + clear_bit(MLX5_FW_RESET_FLAGS_RESET_IN_PROGRESS, + &fw_reset->reset_flags); complete(&fw_reset->done); - } else { - mlx5_sync_reset_unload_flow(dev, false); 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Miller" CC: Jonathan Corbet , Shuah Khan , Jiri Pirko , Simon Horman , "Saeed Mahameed" , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Borislav Petkov (AMD)" , Andrew Morton , Randy Dunlap , Thomas Gleixner , Petr Mladek , "Peter Zijlstra (Intel)" , "Tejun Heo" , Vlastimil Babka , Feng Tang , Christian Brauner , "Dave Hansen" , Dapeng Mi , Kees Cook , Marco Elver , Li RongQing , Eric Biggers , "Paul E. McKenney" , , , , , Gal Pressman , Dragos Tatulea , Jiri Pirko Subject: [PATCH net-next 2/3] devlink: Add eswitch mode boot defaults Date: Thu, 21 May 2026 10:24:33 +0300 Message-ID: <20260521072434.362624-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260521072434.362624-1-tariqt@nvidia.com> References: <20260521072434.362624-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E62:EE_|CY8PR12MB7267:EE_ X-MS-Office365-Filtering-Correlation-Id: f587456b-6da8-4f34-b0f7-08deb70a234a X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700016|7416014|11063799006|6133799003|3023799007|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: 7xNOZAS6EHO7yDJlULd/WZPSjV1eIBKMiLo5695qKcDWSs8rpJ8Eily458SqKqELxuDgSI0HPIWuAlkZuTFZgBsIFxevKo+ydOo+7WPWO3R1SZaAh5YgKZ9nnlTpLNyGWnFHgiUFMByyHfo5tbMMXcEzX3lJFvxzZmCu9gO+YAQi7fph0tfKQUmyUC6sNjsGjA/yxQyKm6NtaYQN9eHg6+/pUSIH41HObjIP38BNGjc5pMdFW7xkHcHMoLy+izidIcgtgwEtlGgOfPdmhU2pBprNFKBabSdUGoJ/+9cL5kPQxvMZ3SO/BTZQHdxC3DodTyIsMVdfW5/uQ2V0QHpAoIFlUBNACZYsfR1Gd+07vl9edj4zW2JTh7EejqFsJzSXUFnHJzvcN/h/ln7ib5U98MQte85FXUCPWHK/lbcpu5HxEWRWG7Jfhl07qXUDPJVwA+tIKBCJ5AMAlcSKndt3wodWoUgnX7P+BoMWYm0/2czhCz2zUeP9Geq4wxZ+iR/iz1dftqssGU4/+TnuA2ezYV5zlY+lCY3slQanKm+jC6CC5BG6nC7Z8v/2AFF7IdxHypBkW+rrhGaUmgMVo+RUDeP5hK+A9HscCzqvp9fsj6568V5vsR5BvV78VWaYMLu/EBIIIXYkg99TyqlYHFzWYvbmSBQl7gEM+EnQ2bItFEsD89/ME7AYiX0ToUED/c4lcrjDBjZ9kB0omoNNenZvK4bQP9Fd2/iwMgosB3wv2zQ= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(36860700016)(7416014)(11063799006)(6133799003)(3023799007)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 1CZksGaLLbYyFHwHkDz1ZaCx6xHM+d160lMeT2ulxJnBsB+xAz/czjGliKwQ7QtZUvLkkwYtXieVdJbxJp7vuHbkqVvnpwKxp7/PXQfXZdfUJ+mTuo0kN0bbsVx1mGE5aphjvlMKnZMOvsQS0m/JEqA6XU0lg+rEYroBObcYP/TPHYP4/KupiLOzPhfXasB+cntdxmJLF8qboKqwgMdvc3GFFhrDJhr9Eo2i35ZYd5vCyYVj/BXP6C6TXizge4DhrJ5W99Y/E/5XCMzj/LR6NCyQFfYf7I0HV0l2FYucRn9jckkwvcuL7LKke9A6vKMzB81d/sKOFopcGyxF+RvbMWy3+jheK5Rt9vFec73vAt1pzb+qwk2NXpajybCr4hoHBfAP093IkNlaEYbGa84Znpbq+2wggjseb6TRrylRgDHa7sgzkdo4/uHikdqhsy4W X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2026 07:25:30.2148 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f587456b-6da8-4f34-b0f7-08deb70a234a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E62.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7267 Content-Type: text/plain; charset="utf-8" From: Mark Bloch Add devlink_eswitch_mode=3D command line support for setting an eswitch mode during device initialization. The supported syntax selects either all devlink handles or one explicit comma-separated handle list: devlink_eswitch_mode=3D[*]: devlink_eswitch_mode=3D[[,...]]: where is one of legacy, switchdev or switchdev_inactive. All selected handles receive the same mode. Assigning different modes to different handle lists in the same parameter value is not supported. The default is applied through the existing eswitch_mode_set() devlink operation, matching the userspace devlink eswitch set command. Expose devl_apply_default_esw_mode() so drivers can apply the default at the point where their devlink instance and eswitch operations are ready. Document the devlink_eswitch_mode=3D syntax and duplicate handle handling. Signed-off-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../admin-guide/kernel-parameters.txt | 25 ++ .../networking/devlink/devlink-defaults.rst | 80 ++++++ Documentation/networking/devlink/index.rst | 1 + include/net/devlink.h | 1 + net/devlink/core.c | 255 ++++++++++++++++++ 5 files changed, 362 insertions(+) create mode 100644 Documentation/networking/devlink/devlink-defaults.rst diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 7834ee927310..f87ae561c0dc 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1278,6 +1278,31 @@ Kernel parameters dell_smm_hwmon.fan_max=3D [HW] Maximum configurable fan speed. =20 + devlink_eswitch_mode=3D + [NET] + Format: + []: + + : + * | [,...] + + : + / + + Configure default devlink eswitch mode for matching + devlink instances during device initialization. + + : + legacy | switchdev | switchdev_inactive + + Examples: + devlink_eswitch_mode=3D[*]:switchdev + devlink_eswitch_mode=3D[pci/0000:08:00.0]:switchdev + devlink_eswitch_mode=3D[pci/0000:08:00.0,pci/0000:09:00.1]:legacy + + See Documentation/networking/devlink/devlink-defaults.rst + for the full syntax. + dfltcc=3D [HW,S390] Format: { on | off | def_only | inf_only | always } on: s390 zlib hardware support for compression on diff --git a/Documentation/networking/devlink/devlink-defaults.rst b/Docume= ntation/networking/devlink/devlink-defaults.rst new file mode 100644 index 000000000000..b554e75eeeea --- /dev/null +++ b/Documentation/networking/devlink/devlink-defaults.rst @@ -0,0 +1,80 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D +Devlink Eswitch Mode Defaults +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D + +Devlink eswitch mode defaults allow the eswitch mode to be provided on the +kernel command line and applied to matching devlink instances during device +initialization. + +The devlink device is selected by its devlink handle. For PCI devices this= is +the same handle shown by ``devlink dev show``, for example +``pci/0000:08:00.0``. + +Kernel command line syntax +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D + +Defaults are specified with the ``devlink_eswitch_mode=3D`` kernel command= line +parameter. + +The general syntax is:: + + devlink_eswitch_mode=3D[]: + +```` is either ``*`` or one or more devlink handles:: + + * | /[,/...] + +``*`` applies the mode to every devlink instance. All handles in the same +``[]`` list receive the same eswitch mode. + +```` is one of ``legacy``, ``switchdev`` or ``switchdev_inactive``. + +Syntax rules +------------ + +The following syntax rules apply: + +* Specify the default in one ``devlink_eswitch_mode=3D`` parameter. Repeat= ed + ``devlink_eswitch_mode=3D`` parameters are not accumulated. +* The ``devlink_eswitch_mode=3D`` value is limited by the kernel command l= ine + size. +* Whitespace is not allowed within the parameter value. +* ```` must be either ``*`` or a handle list. ``*`` cannot be + combined with explicit handles. +* ```` and ```` must not be empty. +* ```` must not contain ``:``. +* ```` may contain ``:``. This allows PCI names such as + ``0000:08:00.0``. +* Handles must not contain whitespace, ``[``, ``]``, ``*`` or more than one + ``/``. +* A comma inside ``[]`` separates handles. +* Comma-separated default groups are not supported. +* Duplicate handles are rejected and the devlink eswitch mode default is + ignored. + +The eswitch mode default corresponds to the userspace command:: + + devlink dev eswitch set mode + + +Examples +=3D=3D=3D=3D=3D=3D=3D=3D + +Set all devlink instances to switchdev mode:: + + devlink_eswitch_mode=3D[*]:switchdev + +Set one PCI devlink instance to switchdev mode:: + + devlink_eswitch_mode=3D[pci/0000:08:00.0]:switchdev + +Set two PCI devlink instances to legacy mode:: + + devlink_eswitch_mode=3D[pci/0000:08:00.0,pci/0000:09:00.1]:legacy + +The following is invalid because comma-separated default groups are not +supported:: + + devlink_eswitch_mode=3D[pci/0000:08:00.0]:switchdev,[pci/0000:09:00.0]:s= witchdev_inactive diff --git a/Documentation/networking/devlink/index.rst b/Documentation/net= working/devlink/index.rst index f7ba7dcf477d..0d27a7008b14 100644 --- a/Documentation/networking/devlink/index.rst +++ b/Documentation/networking/devlink/index.rst @@ -56,6 +56,7 @@ general. :maxdepth: 1 =20 devlink-dpipe + devlink-defaults devlink-eswitch-attr devlink-flash devlink-health diff --git a/include/net/devlink.h b/include/net/devlink.h index bcd31de1f890..98885f7c6c10 100644 --- a/include/net/devlink.h +++ b/include/net/devlink.h @@ -1622,6 +1622,7 @@ int devl_trylock(struct devlink *devlink); void devl_unlock(struct devlink *devlink); void devl_assert_locked(struct devlink *devlink); bool devl_lock_is_held(struct devlink *devlink); +int devl_apply_default_esw_mode(struct devlink *devlink); DEFINE_GUARD(devl, struct devlink *, devl_lock(_T), devl_unlock(_T)); =20 struct ib_device; diff --git a/net/devlink/core.c b/net/devlink/core.c index eeb6a71f5f56..4bc1734878d1 100644 --- a/net/devlink/core.c +++ b/net/devlink/core.c @@ -4,6 +4,10 @@ * Copyright (c) 2016 Jiri Pirko */ =20 +#include +#include +#include +#include #include #define CREATE_TRACE_POINTS #include @@ -16,6 +20,233 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(devlink_trap_report); =20 DEFINE_XARRAY_FLAGS(devlinks, XA_FLAGS_ALLOC); =20 +static char *devlink_default_esw_mode_param; +static bool devlink_default_esw_mode_match_all; +static enum devlink_eswitch_mode devlink_default_esw_mode; +static LIST_HEAD(devlink_default_esw_mode_nodes); + +struct devlink_default_esw_mode_node { + struct list_head list; + char *bus_name; + char *dev_name; +}; + +static int __init +devlink_default_esw_mode_to_value(const char *str, + enum devlink_eswitch_mode *mode) +{ + if (!strcmp(str, "legacy")) { + *mode =3D DEVLINK_ESWITCH_MODE_LEGACY; + return 0; + } + if (!strcmp(str, "switchdev")) { + *mode =3D DEVLINK_ESWITCH_MODE_SWITCHDEV; + return 0; + } + if (!strcmp(str, "switchdev_inactive")) { + *mode =3D DEVLINK_ESWITCH_MODE_SWITCHDEV_INACTIVE; + return 0; + } + + return -EINVAL; +} + +static int devlink_default_esw_mode_apply(struct devlink *devlink) +{ + const struct devlink_ops *ops =3D devlink->ops; + + if (!ops->eswitch_mode_set) + return -EOPNOTSUPP; + + return ops->eswitch_mode_set(devlink, devlink_default_esw_mode, + NULL); +} + +static int __init +devlink_default_esw_mode_handle_parse(char *handle, char **bus_name, + char **dev_name) +{ + char *slash; + char *p; + + if (!handle || !*handle) + return -EINVAL; + + for (p =3D handle; *p; p++) { + if (*p =3D=3D '[' || *p =3D=3D ']' || *p =3D=3D '*') + return -EINVAL; + } + + slash =3D strchr(handle, '/'); + if (!slash || slash =3D=3D handle || !slash[1]) + return -EINVAL; + if (strchr(slash + 1, '/')) + return -EINVAL; + + *slash =3D '\0'; + if (strchr(handle, ':')) + return -EINVAL; + + *bus_name =3D handle; + *dev_name =3D slash + 1; + return 0; +} + +static struct devlink_default_esw_mode_node * +devlink_default_esw_mode_node_find(const char *bus_name, const char *dev_n= ame) +{ + struct devlink_default_esw_mode_node *node; + + list_for_each_entry(node, &devlink_default_esw_mode_nodes, list) { + if (!strcmp(node->bus_name, bus_name) && + !strcmp(node->dev_name, dev_name)) + return node; + } + + return NULL; +} + +static int __init +devlink_default_esw_mode_node_add(const char *bus_name, const char *dev_na= me) +{ + struct devlink_default_esw_mode_node *node; + + if (devlink_default_esw_mode_node_find(bus_name, dev_name)) + return -EEXIST; + + node =3D kzalloc_obj(*node); + if (!node) + return -ENOMEM; + + INIT_LIST_HEAD(&node->list); + node->bus_name =3D kstrdup(bus_name, GFP_KERNEL); + node->dev_name =3D kstrdup(dev_name, GFP_KERNEL); + if (!node->bus_name || !node->dev_name) { + kfree(node->bus_name); + kfree(node->dev_name); + kfree(node); + return -ENOMEM; + } + + list_add_tail(&node->list, &devlink_default_esw_mode_nodes); + return 0; +} + +static int __init devlink_default_esw_mode_handles_parse(char *handles) +{ + char *handle; + int err; + + if (!strcmp(handles, "*")) { + devlink_default_esw_mode_match_all =3D true; + return 0; + } + + while ((handle =3D strsep(&handles, ",")) !=3D NULL) { + char *bus_name; + char *dev_name; + + err =3D devlink_default_esw_mode_handle_parse(handle, &bus_name, + &dev_name); + if (err) + return err; + + err =3D devlink_default_esw_mode_node_add(bus_name, dev_name); + if (err) + return err; + } + + return 0; +} + +static void __init +devlink_default_esw_mode_node_free(struct devlink_default_esw_mode_node *n= ode) +{ + kfree(node->bus_name); + kfree(node->dev_name); + kfree(node); +} + +static void __init devlink_default_esw_mode_nodes_clear(void) +{ + struct devlink_default_esw_mode_node *node; + struct devlink_default_esw_mode_node *node_tmp; + + list_for_each_entry_safe(node, node_tmp, + &devlink_default_esw_mode_nodes, list) { + list_del(&node->list); + devlink_default_esw_mode_node_free(node); + } + + devlink_default_esw_mode_match_all =3D false; +} + +static int __init devlink_default_esw_mode_parse(char *str) +{ + char *handles_end; + char *handles; + char *mode; + int err; + + if (!str || *str !=3D '[') + return -EINVAL; + + handles =3D str + 1; + handles_end =3D strchr(handles, ']'); + if (!handles_end || handles_end[1] !=3D ':' || !handles_end[2]) + return -EINVAL; + + *handles_end =3D '\0'; + mode =3D handles_end + 2; + if (!*handles) + return -EINVAL; + + err =3D devlink_default_esw_mode_to_value(mode, + &devlink_default_esw_mode); + if (err) + return err; + + err =3D devlink_default_esw_mode_handles_parse(handles); + if (err) + devlink_default_esw_mode_nodes_clear(); + + return err; +} + +/** + * devl_apply_default_esw_mode - Apply default eswitch mode to devlink ins= tance + * @devlink: devlink + * + * The caller must hold the devlink instance lock. + * + * Return: 0 on success, negative error code otherwise. + */ +int devl_apply_default_esw_mode(struct devlink *devlink) +{ + const char *bus_name =3D devlink_bus_name(devlink); + const char *dev_name =3D devlink_dev_name(devlink); + struct devlink_default_esw_mode_node *node; + + devl_assert_locked(devlink); + + if (devlink_default_esw_mode_match_all) + return devlink_default_esw_mode_apply(devlink); + + node =3D devlink_default_esw_mode_node_find(bus_name, dev_name); + if (node) + return devlink_default_esw_mode_apply(devlink); + + return 0; +} +EXPORT_SYMBOL_GPL(devl_apply_default_esw_mode); + +static int __init devlink_default_esw_mode_setup(char *str) +{ + devlink_default_esw_mode_param =3D str; + return 1; +} +__setup("devlink_eswitch_mode=3D", devlink_default_esw_mode_setup); + static struct devlink *devlinks_xa_get(unsigned long index) { struct devlink *devlink; @@ -578,6 +809,27 @@ static int __init devlink_init(void) { int err; =20 + if (devlink_default_esw_mode_param) { + char *def; + + def =3D kstrdup(devlink_default_esw_mode_param, GFP_KERNEL); + if (!def) { + err =3D -ENOMEM; + goto out; + } + err =3D devlink_default_esw_mode_parse(def); + kfree(def); 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Miller" CC: Jonathan Corbet , Shuah Khan , Jiri Pirko , Simon Horman , "Saeed Mahameed" , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Borislav Petkov (AMD)" , Andrew Morton , Randy Dunlap , Thomas Gleixner , Petr Mladek , "Peter Zijlstra (Intel)" , "Tejun Heo" , Vlastimil Babka , Feng Tang , Christian Brauner , "Dave Hansen" , Dapeng Mi , Kees Cook , Marco Elver , Li RongQing , Eric Biggers , "Paul E. McKenney" , , , , , Gal Pressman , Dragos Tatulea , Jiri Pirko , Shay Drori , Moshe Shemesh Subject: [PATCH net-next 3/3] net/mlx5: Apply devlink default eswitch mode during init Date: Thu, 21 May 2026 10:24:34 +0300 Message-ID: <20260521072434.362624-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260521072434.362624-1-tariqt@nvidia.com> References: <20260521072434.362624-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000013F:EE_|SJ5PPF3487F9737:EE_ X-MS-Office365-Filtering-Correlation-Id: b37cb7f8-342b-465f-bb0a-08deb70a2483 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|82310400026|36860700016|18002099003|56012099003|22082099003|11063799006|6133799003; X-Microsoft-Antispam-Message-Info: Dy7r6D2pgtg2RyrNA5tzLZWdH7wOx6FGrsIi/eyw43HlKqzJ2p9bcWuYwYsizon6Q9UQ9G2dAIVdONPNkYiQYEclo3adycw44oY1K5wFhWWDnI+8MeLid99Kij0aArSdUpra4rDUZVrAcB6sK3JPA7ris3fxfTvwW5Mn904AMPuT/iq4gA2AiHtPwGBP5f140asqetv0cbM+jw2MiUrqWMS6Wd8MQUA5H9e7lgdatlq0zJasdyQffPGX/Bj9XenFfT3xfzKXibxH6Zf+tKU7HXXJVXwgz8iZ4y/+riE7JCYNrti9jt8YaGY6pXe8nZbi3TBepBfyJdOUi4Gu7nQR78r0Bu2Y82P8JsVwTixc50oj97pAFLXSBatgTyjIgmx+3GPxI3ZvPvf7Z16V/jK2osBB5LVq7lbmr9qKehmZMA3flK1luV/bWtiXLmelqdrjXhguADjMU/zvdsScF5R1mXd6KKajhFPzNaxSZUhejsaj2wsXmWVv7pT2KvxGvXXm1hJXTQGTK1rsqy3/Mn8SEGfPZe2z15cj5zstA83YYtSUZp7+OkybUau18ZlZnU7D7k6VWLBvgyaYitRo46v/msNEjZTr5UgTI/Dd2vxy82jgHUObGhwAbRTcTyC3mC7gvqkrEqlTMBGassmPYxol6+R5bGMnIUn7mTAxf7rcwA75g7b5DfgXliVubgf+rztyF/pAQxMNrox/LwQYHI7IJ6BomHolZtoA3iIc0Yx8X5U= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(82310400026)(36860700016)(18002099003)(56012099003)(22082099003)(11063799006)(6133799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: HXmBGxuGdBRao+yXce6uDnVj+Fs39B0Y8Zhm6f9t7VtYVPBVKSxM+Vv9q0DXOKQBJAWu652+3Yvi4dUPcaEU0zX0VcxV481YEYhl4AlHgDMz9G6rRK/JKlThTyXqhgKz+nQazZu73R/nxheOwekEibuDoMU99gXLI+LNYnpfRBtynrrStZxPGcQjmFLmFheN/C+Kwpb+tkbMxzyVSdzVJW8xls7iG0n2dXj0Tcg3Wpn98NZNRPHAtrXV2Sl2d8rVxOl9ii3kbXyZ5JOJ1mHmEHc6i1k4//CuqlCZPdxdYpdaN3fQlkrfNckefPrWoaJtmdfRAAm0QieHp8uVMt/4Wgq5YGjxLxAptb4Nn40jdFpQHHTHhPI9lHTLf35a8wohuSDyHOUxbFKSxesnsQHmYL8A+jKJjUOkqYh9T2vvjpHcXCSJ23iyrSE0I2LeshbZ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2026 07:25:32.2248 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b37cb7f8-342b-465f-bb0a-08deb70a2483 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ5PPF3487F9737 Content-Type: text/plain; charset="utf-8" From: Mark Bloch Apply devlink default eswitch mode for mlx5 devices after successful device initialization while holding the devlink instance lock. At this point the devlink instance is registered and the mlx5 devlink operations are available, so the default eswitch mode can be applied to the matching PCI devlink handle. Signed-off-by: Mark Bloch Reviewed-by: Shay Drori Reviewed-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/main.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/e= thernet/mellanox/mlx5/core/main.c index 0c6e4efe38c8..4528097f3d84 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -1391,6 +1391,21 @@ static void mlx5_unload(struct mlx5_core_dev *dev) mlx5_free_bfreg(dev, &dev->priv.bfreg); } =20 +static void mlx5_devl_apply_default_esw_mode(struct mlx5_core_dev *dev) +{ + struct devlink *devlink =3D priv_to_devlink(dev); + int err; + + if (!MLX5_ESWITCH_MANAGER(dev)) + return; + + devl_assert_locked(devlink); + err =3D devl_apply_default_esw_mode(devlink); + if (err) + mlx5_core_warn(dev, "Couldn't apply default eswitch mode, err %d\n", + err); +} + int mlx5_init_one_devl_locked(struct mlx5_core_dev *dev) { bool light_probe =3D mlx5_dev_is_lightweight(dev); @@ -1437,6 +1452,7 @@ int mlx5_init_one_devl_locked(struct mlx5_core_dev *d= ev) mlx5_core_err(dev, "mlx5_hwmon_dev_register failed with error code %d\n"= , err); =20 mutex_unlock(&dev->intf_state_mutex); + mlx5_devl_apply_default_esw_mode(dev); return 0; =20 err_register: @@ -1538,6 +1554,7 @@ int mlx5_load_one_devl_locked(struct mlx5_core_dev *d= ev, bool recovery) goto err_attach; =20 mutex_unlock(&dev->intf_state_mutex); + mlx5_devl_apply_default_esw_mode(dev); return 0; =20 err_attach: --=20 2.44.0