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charset="utf-8" Define the BAR-resident metadata format used by endpoint functions that expose an endpoint-integrated DMA controller to the host. A VSEC-based discovery scheme would be a natural fit, and existing dw-edma-pcie providers such as Synopsys EDDA and AMD/Xilinx MDB already use VSECs for DMA discovery. However, some endpoint controllers cannot provide enough writable configuration-space storage for a complete, controller-defined payload. Keep the extensible metadata in a BAR instead, where the endpoint function controls the layout and size. The format describes the DMA register window, exported channel counts, descriptor windows, optional auxiliary windows, endpoint-local descriptor and auxiliary DMA addresses, and a ready bit that tells the host when the described BAR windows are usable. Channel entries keep the auxiliary window optional so layouts that need a separate data or auxiliary aperture can describe it without a format bump. Signed-off-by: Koichiro Den --- MAINTAINERS | 1 + include/linux/pci-ep-dma.h | 163 +++++++++++++++++++++++++++++++++++++ 2 files changed, 164 insertions(+) create mode 100644 include/linux/pci-ep-dma.h diff --git a/MAINTAINERS b/MAINTAINERS index 2fb1c75afd16..416c8c063113 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20508,6 +20508,7 @@ F: Documentation/PCI/endpoint/* F: Documentation/misc-devices/pci-endpoint-test.rst F: drivers/misc/pci_endpoint_test.c F: drivers/pci/endpoint/ +F: include/linux/pci-ep-dma.h F: tools/testing/selftests/pci_endpoint/ =20 PCI ENHANCED ERROR HANDLING (EEH) FOR POWERPC diff --git a/include/linux/pci-ep-dma.h b/include/linux/pci-ep-dma.h new file mode 100644 index 000000000000..c5fd7aab2101 --- /dev/null +++ b/include/linux/pci-ep-dma.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_PCI_EP_DMA_H +#define __LINUX_PCI_EP_DMA_H + +#include + +/* + * BAR metadata format used by PCI endpoint functions that expose an + * endpoint-integrated DMA controller to a PCI host. + * + * Offsets are relative to the beginning of the metadata blob. Multi-byte + * fields are little-endian. The blob is normally placed at offset 0 of a + * function BAR selected by the endpoint function and discovered by the ho= st + * driver using device-specific policy. Other data in the same BAR, such a= s a + * standard MSI-X table or PBA, is outside this metadata format. + * + * 31 = 0 + * +-------------------------------------------------------------= --+ + * +0x000 | metadata magic = | + * +-------------------------------------------------------------= --+ + * 31 16 15 8 7 = 0 + * +-------------------------------+---------------+-------------= --+ + * +0x004 | metadata length | reserved | revision = | + * +-------------------------------+---------------+-------------= --+ + * 31 30 29 27 26 19 18 11 10 3 2= 0 + * +--+--+--------+--------------+--------------+--------------+-= --+ + * +0x008 |R |H |reserved| ch entry size| RD count | WR count |B= AR| + * +--+--+--------+--------------+--------------+--------------+-= --+ + * +0x00c | register window offset[31:0] = | + * +-------------------------------------------------------------= --+ + * +0x010 | register window offset[63:32] = | + * +-------------------------------------------------------------= --+ + * 31 16 15 8 7 = 0 + * +-------------------------------+---------------+-------------= --+ + * +0x014 | reserved | layout data | layout = | + * +-------------------------------+---------------+-------------= --+ + * +0x018 | register window size = | + * +-------------------------------------------------------------= --+ + * +0x01c | write table = | + * | ( channel table entries #0 ~ #N ) = | + * +-------------------------------------------------------------= --+ + * | read table = | + * | ( channel table entries #0 ~ #N ) = | + * +-------------------------------------------------------------= --+ + * + * metadata magic: PCI_EP_DMA_METADATA_MAGIC. + * metadata length: byte size of the whole metadata blob. + * revision: metadata format revision. + * R: ready bit. Set when all BAR windows described by this metad= ata + * have been programmed and can be used by the host. + * H: host-request bit. Set by the host driver after it has found= this + * metadata. The endpoint may use this as the trigger to progr= am + * DMA window BAR subrange mappings. + * ch entry size: byte stride between consecutive channel table + * entries. Revision 1 requires at least + * PCI_EP_DMA_METADATA_CH_ENTRY_SIZE bytes. + * RD count: number of exposed RC-to-endpoint DMA read channels a= nd + * read channel-table entries. + * WR count: number of exposed endpoint-to-RC DMA write channels = and + * write channel-table entries. + * BAR: BAR that contains the DMA controller register window. + * register window offset: BAR-local byte offset of the DMA contr= oller + * register window in BAR. + * register window size: DMA controller register window size in b= ytes. + * layout: DMA controller register layout identifier. + * layout data: layout-specific data. For + * PCI_EP_DMA_METADATA_REG_LAYOUT_DW_EDMA this is the + * DesignWare eDMA/HDMA map format. + * write table: starts at PCI_EP_DMA_METADATA_HDR_LEN if write ch= annel + * count is non-zero. + * read table: starts at PCI_EP_DMA_METADATA_HDR_LEN plus the wri= te + * table size if read channel count is non-zero. + * + * + * Channel table entry: + * + * 31 17 16 15 14 12 11 10 8 7 = 0 + * +--------------------+--+--+-------+--+--------+--------------= --+ + * +0x000 | reserved |A |rs|aux BAR|rs|desc BAR|hardware chann= el| + * +--------------------+--+--+-------+--+--------+--------------= --+ + * +0x004 | descriptor window BAR offset[31:0] = | + * +-------------------------------------------------------------= --+ + * +0x008 | descriptor window BAR offset[63:32] = | + * +-------------------------------------------------------------= --+ + * +0x00c | descriptor window size = | + * +-------------------------------------------------------------= --+ + * +0x010 | descriptor DMA address[31:0] = | + * +-------------------------------------------------------------= --+ + * +0x014 | descriptor DMA address[63:32] = | + * +-------------------------------------------------------------= --+ + * +0x018 | auxiliary window BAR offset[31:0] = | + * +-------------------------------------------------------------= --+ + * +0x01c | auxiliary window BAR offset[63:32] = | + * +-------------------------------------------------------------= --+ + * +0x020 | auxiliary window size = | + * +-------------------------------------------------------------= --+ + * +0x024 | auxiliary DMA address[31:0] = | + * +-------------------------------------------------------------= --+ + * +0x028 | auxiliary DMA address[63:32] = | + * +-------------------------------------------------------------= --+ + * + * A: auxiliary-window-valid bit. If clear, aux BAR and auxiliary + * window fields are ignored. + * aux BAR: BAR that contains the optional auxiliary window. + * desc BAR: BAR that contains the descriptor window. + * hardware channel: DMA controller's hardware channel number. + * Revision 1 entries are currently consumed in= dense + * 0-based order. + * descriptor window BAR offset: BAR-local byte offset of the + * descriptor window in desc BAR. + * descriptor window size: descriptor window size in bytes. + * descriptor DMA address: endpoint-local address used by the DMA + * controller to fetch descriptors. + * auxiliary window BAR offset: BAR-local byte offset of the auxi= liary + * window in aux BAR. + * auxiliary window size: auxiliary window size in bytes. + * auxiliary DMA address: endpoint-local address corresponding to= the + * auxiliary window. + */ +#define PCI_EP_DMA_METADATA_MAGIC 0x4d444550 /* "PEDM" */ +#define PCI_EP_DMA_METADATA_REV 0x1 + +#define PCI_EP_DMA_METADATA_HDR_LEN 0x1c + +#define PCI_EP_DMA_METADATA_HDR 0x04 +#define PCI_EP_DMA_METADATA_HDR_REV GENMASK(7, 0) +#define PCI_EP_DMA_METADATA_HDR_LEN_FIELD GENMASK(31, 16) + +#define PCI_EP_DMA_METADATA_CTRL 0x08 +#define PCI_EP_DMA_METADATA_CTRL_REG_BAR GENMASK(2, 0) +#define PCI_EP_DMA_METADATA_CTRL_WR_CH_COUNT GENMASK(10, 3) +#define PCI_EP_DMA_METADATA_CTRL_RD_CH_COUNT GENMASK(18, 11) +#define PCI_EP_DMA_METADATA_CTRL_CH_ENTRY_SIZE GENMASK(26, 19) +#define PCI_EP_DMA_METADATA_CTRL_HOST_REQ BIT(30) +#define PCI_EP_DMA_METADATA_CTRL_READY BIT(31) + +#define PCI_EP_DMA_METADATA_REG_OFF_LO 0x0c +#define PCI_EP_DMA_METADATA_REG_OFF_HI 0x10 +#define PCI_EP_DMA_METADATA_REG_LAYOUT 0x14 +#define PCI_EP_DMA_METADATA_REG_LAYOUT_ID GENMASK(7, 0) +#define PCI_EP_DMA_METADATA_REG_LAYOUT_DATA GENMASK(15, 8) +#define PCI_EP_DMA_METADATA_REG_SIZE 0x18 + +#define PCI_EP_DMA_METADATA_REG_LAYOUT_DW_EDMA 0x1 + +#define PCI_EP_DMA_METADATA_CH_ENTRY_SIZE 0x2c +#define PCI_EP_DMA_METADATA_CH_CTRL 0x00 +#define PCI_EP_DMA_METADATA_CH_CTRL_HW_CH GENMASK(7, 0) +#define PCI_EP_DMA_METADATA_CH_CTRL_DESC_BAR GENMASK(10, 8) +#define PCI_EP_DMA_METADATA_CH_CTRL_AUX_BAR GENMASK(14, 12) +#define PCI_EP_DMA_METADATA_CH_CTRL_AUX_VALID BIT(16) +#define PCI_EP_DMA_METADATA_CH_DESC_OFF_LO 0x04 +#define PCI_EP_DMA_METADATA_CH_DESC_OFF_HI 0x08 +#define PCI_EP_DMA_METADATA_CH_DESC_SIZE 0x0c +#define PCI_EP_DMA_METADATA_CH_DESC_ADDR_LO 0x10 +#define PCI_EP_DMA_METADATA_CH_DESC_ADDR_HI 0x14 +#define PCI_EP_DMA_METADATA_CH_AUX_OFF_LO 0x18 +#define PCI_EP_DMA_METADATA_CH_AUX_OFF_HI 0x1c +#define PCI_EP_DMA_METADATA_CH_AUX_SIZE 0x20 +#define PCI_EP_DMA_METADATA_CH_AUX_ADDR_LO 0x24 +#define PCI_EP_DMA_METADATA_CH_AUX_ADDR_HI 0x28 + +#endif /* __LINUX_PCI_EP_DMA_H */ --=20 2.51.0 From nobody Sun May 24 21:39:23 2026 Received: from TY3P286CU002.outbound.protection.outlook.com (mail-japaneastazon11020080.outbound.protection.outlook.com [52.101.229.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 630AC394EAF; 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charset="utf-8" Extend EPC auxiliary resource metadata so endpoint functions can discover controller-owned DMA registers and descriptor memory. The DMA metadata is intentionally generic at the EPC layer. A backend reports the register layout, channel counts, descriptor memory, hardware channel numbers and, when available, the local DMAengine channel for exact ownership reservation. An endpoint function can then decide whether it can expose those resources to the host. For DesignWare controllers, reg_layout_data carries the eDMA/HDMA map format so a consumer can distinguish legacy, unroll, HDMA compatible, and HDMA native register layouts without making the EPC API itself DesignWare-specific. Signed-off-by: Koichiro Den --- include/linux/pci-epc.h | 43 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index f247cf9bcf1a..1afa491ff6e7 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -11,6 +11,7 @@ =20 #include =20 +struct dma_chan; struct pci_epc; =20 enum pci_epc_interface_type { @@ -65,6 +66,8 @@ struct pci_epc_map { * enum pci_epc_aux_resource_type - auxiliary resource type identifiers * @PCI_EPC_AUX_DOORBELL_MMIO: Doorbell MMIO, that might be outside the DMA * controller register window + * @PCI_EPC_AUX_DMA_CTRL_MMIO: DMA controller MMIO register window + * @PCI_EPC_AUX_DMA_DESC_MEM: DMA descriptor memory * * EPC backends may expose auxiliary blocks (e.g. DMA engines) by mapping = their * register windows and descriptor memories into BAR space. This enum @@ -72,6 +75,26 @@ struct pci_epc_map { */ enum pci_epc_aux_resource_type { PCI_EPC_AUX_DOORBELL_MMIO, + PCI_EPC_AUX_DMA_CTRL_MMIO, + PCI_EPC_AUX_DMA_DESC_MEM, +}; + +/** + * enum pci_epc_aux_dma_reg_layout - DMA controller register layout + * @PCI_EPC_AUX_DMA_REG_LAYOUT_DW_EDMA: Synopsys DesignWare eDMA/HDMA layo= ut + */ +enum pci_epc_aux_dma_reg_layout { + PCI_EPC_AUX_DMA_REG_LAYOUT_DW_EDMA, +}; + +/** + * enum pci_epc_aux_dma_dir - DMA channel direction relative to the endpoi= nt + * @PCI_EPC_AUX_DMA_EP_TO_RC: channel moves data from endpoint to root com= plex + * @PCI_EPC_AUX_DMA_RC_TO_EP: channel moves data from root complex to endp= oint + */ +enum pci_epc_aux_dma_dir { + PCI_EPC_AUX_DMA_EP_TO_RC, + PCI_EPC_AUX_DMA_RC_TO_EP, }; =20 /** @@ -99,6 +122,26 @@ struct pci_epc_aux_resource { int irq; /* IRQ number for the doorbell handler */ u32 data; /* write value to ring the doorbell */ } db_mmio; + + /* PCI_EPC_AUX_DMA_CTRL_MMIO */ + struct { + enum pci_epc_aux_dma_reg_layout reg_layout; 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charset="utf-8" Expose the DesignWare endpoint-integrated eDMA register window and linked-list descriptor memories through the EPC auxiliary resource API. This lets endpoint functions decide which channels to publish to the host. When the DMA register window is already visible through a reserved BAR region, report its BAR and offset. Otherwise report it as a normal physical resource so an endpoint function can map it. Descriptor resources also carry the local DMAengine channel pointer so consumers can reserve exact channels before delegation. Signed-off-by: Koichiro Den --- .../pci/controller/dwc/pcie-designware-ep.c | 77 ++++++++++++++++++- 1 file changed, 73 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index e4c6f7193495..155a2287363e 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -866,14 +866,26 @@ dw_pcie_ep_get_aux_resources_count(struct pci_epc *ep= c, u8 func_no, struct dw_pcie_ep *ep =3D epc_get_drvdata(epc); struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); struct dw_edma_chip *edma =3D &pci->edma; + unsigned int i; + int count =3D 1; =20 if (!pci->edma_reg_size) return 0; =20 - if (edma->db_offset =3D=3D ~0) - return 0; + for (i =3D 0; i < edma->ll_wr_cnt; i++) { + if (edma->ll_region_wr[i].sz) + count++; + } + + for (i =3D 0; i < edma->ll_rd_cnt; i++) { + if (edma->ll_region_rd[i].sz) + count++; + } + + if (edma->db_offset !=3D ~0) + count++; =20 - return 1; + return count; } =20 static int @@ -889,6 +901,7 @@ dw_pcie_ep_get_aux_resources(struct pci_epc *epc, u8 fu= nc_no, u8 vfunc_no, resource_size_t db_offset =3D edma->db_offset; resource_size_t dma_ctrl_bar_offset =3D 0; resource_size_t dma_reg_size; + unsigned int i; int count; =20 count =3D dw_pcie_ep_get_aux_resources_count(epc, func_no, vfunc_no); @@ -910,6 +923,62 @@ dw_pcie_ep_get_aux_resources(struct pci_epc *epc, u8 f= unc_no, u8 vfunc_no, if (rsvd && rsvd->size < dma_reg_size) dma_reg_size =3D rsvd->size; =20 + count =3D 0; + resources[count++] =3D (struct pci_epc_aux_resource) { + .type =3D PCI_EPC_AUX_DMA_CTRL_MMIO, + .phys_addr =3D pci->edma_reg_phys, + .size =3D dma_reg_size, + .bar =3D dma_ctrl_bar, + .bar_offset =3D dma_ctrl_bar !=3D NO_BAR ? dma_ctrl_bar_offset : 0, + .u.dma_ctrl =3D { + .reg_layout =3D PCI_EPC_AUX_DMA_REG_LAYOUT_DW_EDMA, + .reg_layout_data =3D edma->mf, + .ep_to_rc_ch_cnt =3D edma->ll_wr_cnt, + .rc_to_ep_ch_cnt =3D edma->ll_rd_cnt, + }, + }; + + for (i =3D 0; i < edma->ll_wr_cnt; i++) { + struct dw_edma_region *ll =3D &edma->ll_region_wr[i]; + + if (!ll->sz) + continue; + + resources[count++] =3D (struct pci_epc_aux_resource) { + .type =3D PCI_EPC_AUX_DMA_DESC_MEM, + .phys_addr =3D ll->paddr, + .size =3D ll->sz, + .bar =3D NO_BAR, + .u.dma_desc =3D { + .dir =3D PCI_EPC_AUX_DMA_EP_TO_RC, + .hw_ch =3D i, + .dma_chan =3D dw_edma_find_channel(edma, true, i), + }, + }; + } + + for (i =3D 0; i < edma->ll_rd_cnt; i++) { + struct dw_edma_region *ll =3D &edma->ll_region_rd[i]; + + if (!ll->sz) + continue; + + resources[count++] =3D (struct pci_epc_aux_resource) { + .type =3D PCI_EPC_AUX_DMA_DESC_MEM, + .phys_addr =3D ll->paddr, + .size =3D ll->sz, + .bar =3D NO_BAR, + .u.dma_desc =3D { + .dir =3D PCI_EPC_AUX_DMA_RC_TO_EP, + .hw_ch =3D i, + .dma_chan =3D dw_edma_find_channel(edma, false, i), + }, + }; + } + + if (db_offset =3D=3D ~0) + return 0; + /* * For interrupt-emulation doorbells, report a standalone resource * instead of bundling it into the DMA controller MMIO resource. @@ -918,7 +987,7 @@ dw_pcie_ep_get_aux_resources(struct pci_epc *epc, u8 fu= nc_no, u8 vfunc_no, sizeof(u32), dma_reg_size)) return -EINVAL; =20 - resources[0] =3D (struct pci_epc_aux_resource) { + resources[count] =3D (struct pci_epc_aux_resource) { .type =3D PCI_EPC_AUX_DOORBELL_MMIO, .phys_addr =3D pci->edma_reg_phys + db_offset, .size =3D sizeof(u32), --=20 2.51.0