From nobody Sun May 24 21:40:17 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26BBE2BE655; Thu, 21 May 2026 08:27:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779352028; cv=none; b=X/KFJai2OB4kZ4BfciW7JusqpfRK/hpN9ZGsIPgMmW+pwz08GxFK1p4xaE9uy6bVOmusSudL0L7DE7sr4w2Po+Q05zmBIzQTgsZAoOwKeJC6c4Nv2aEtP5cnv97ZQclsSzKIJMr6Hly41xt0AQiXDsPfwDcoBG6aEPbb+95NOcs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779352028; c=relaxed/simple; bh=zmdM0qo8CX3kHCzsu50etCsSTnTDcsKCliyCWlfpcmk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fiOkz6A61tDiMPIwF4Tle73tH/yTrM0oqq35XZzW2UwQj5oJvE1axUu0hbBy9kgf4wDdaWkomrUMxT7+Y2Qrw0FA5bqLgzG/lQojKgeoqfV7PNya/VCRwayxqFy4tftnpjLZpc5YrPjKewjSEHlKRmsZFw2dBqdjDXZbAGf+tS4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=O6yFaNgd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="O6yFaNgd" Received: by smtp.kernel.org (Postfix) with ESMTPS id C1425C2BCB9; Thu, 21 May 2026 08:27:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779352027; bh=zmdM0qo8CX3kHCzsu50etCsSTnTDcsKCliyCWlfpcmk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=O6yFaNgdZ24tPvORkMDqT/9LMQnMurDaB0VGaCv9k2n6g3R9AwMAoTJ8gKyvmhPD3 shazdxiAydFEJEEnQAmFvRmKU0m84kZm22IuS/Np+c+V40xeFCf3s6LDRmF8pwy3HE 4b8+yxbhzCE81SMAbb8XgA954uxpsAX8hnZ2YoBWwoDPDVAn5KWUUm/URlGtcNEzZ2 OtL5+5yewLoVWNLO1qi76SG6BDi7W5gSND+3G/Xn44EdCgmfDQhsqARSuzu4822RXJ itwfKx4+5OF2Fa2D2vRF7SNK/KHd+KzMu1DTtKHO3WPzfUMI+UIPpVx7rXLUZHE2hg 33AwzqyPSVbWg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8943CD5BA4; Thu, 21 May 2026 08:27:07 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Thu, 21 May 2026 08:26:58 +0000 Subject: [PATCH v3 1/2] dt-bindings: pwm: amlogic: Add new bindings for S6 S7 S7D Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-s6-s7-pwm-v3-1-57b073fbafef@amlogic.com> References: <20260521-s6-s7-pwm-v3-0-57b073fbafef@amlogic.com> In-Reply-To: <20260521-s6-s7-pwm-v3-0-57b073fbafef@amlogic.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, Xianwei Zhao , Junyi Zhao , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779352023; l=1811; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=jS//+H3tRKyNMEGVeMFEtfJwKQUz9wNI3mixje/H5hM=; b=PTJfkqLpXJY8CG2/1IeUXY0TgYTNOuKXgdnZYkkPlxN0t1ApFPyV18CZTxkHoADQboPPPivj7 f3OMlkjxr+uBJGdSELInRiYPfY0nFDOF5SUPm9lkgXkrKh4Qv+106lU X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Junyi Zhao Amlogic S7/S7D/S6 different from the previous SoCs, a controller includes one pwm, at the same time, the controller has only one input clock source. Signed-off-by: Junyi Zhao Reviewed-by: Krzysztof Kozlowski Reviewed-by: Martin Blumenstingl Signed-off-by: Xianwei Zhao --- .../devicetree/bindings/pwm/pwm-amlogic.yaml | 19 +++++++++++++++= ++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml b/Docum= entation/devicetree/bindings/pwm/pwm-amlogic.yaml index c337d85da40f..93fa97f4011b 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml @@ -37,6 +37,7 @@ properties: - enum: - amlogic,meson8-pwm-v2 - amlogic,meson-s4-pwm + - amlogic,s7-pwm - items: - enum: - amlogic,a4-pwm @@ -45,6 +46,11 @@ properties: - amlogic,t7-pwm - amlogic,meson-a1-pwm - const: amlogic,meson-s4-pwm + - items: + - enum: + - amlogic,s6-pwm + - amlogic,s7d-pwm + - const: amlogic,s7-pwm - items: - enum: - amlogic,meson8b-pwm-v2 @@ -146,6 +152,19 @@ allOf: clock-names: false required: - clocks + - if: + properties: + compatible: + contains: + enum: + - amlogic,s7-pwm + then: + properties: + clocks: + maxItems: 1 + clock-names: false + required: + - clocks =20 - if: properties: --=20 2.52.0 From nobody Sun May 24 21:40:17 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26B4B261B91; Thu, 21 May 2026 08:27:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779352028; cv=none; b=F8AWqCZ1xyxYAzutVgM1mMfH1WoFqD2fQm/0ml14TXNDwUtWK9QbkBncZDl3digOk7VpOONiJfMBVavU9RV/8CUwZOjAUj9OD0EsOQX+id1u9eS6NQIUF+HdzQQo10SxT8EFVRCRKbVa0l3SI3ctg5xIJVsTLaBeyF9nvaZN+cM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779352028; c=relaxed/simple; bh=nrmg3HWgO9uceNXtSgM/Z0gIFOwywmG6C/cjZ3MQNRg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nqtduBRdOmaw80E+nx0UFpY38uMpK4E0grpk4RPoJ9VkBm+4E5DkJ+BDPV/tEGMbvt6XKNl7gKiHkZ7KDRTNCIfOQ3/EHK/+hgyNAt1BS2CJ1Uiy5nm1OxtHkFSBk2PMFQDGhBSO6jH3UrqQrug6e5HTXfldNZ+Jh6k1ZIkfY64= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lsbs/SCa; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lsbs/SCa" Received: by smtp.kernel.org (Postfix) with ESMTPS id D278AC4AF0C; Thu, 21 May 2026 08:27:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779352027; bh=nrmg3HWgO9uceNXtSgM/Z0gIFOwywmG6C/cjZ3MQNRg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=lsbs/SCa6p3fbOzxKPf34ToX+DYsBS5QxvDLoTNHqWIRdx14VpoHl0McLsd9Cmf5F Ca7WXCX7Uh68tuyMhLF8/OeeVIWZ3EUGKMNgAZwFRFmsHDClBs/ATGXRLXPppTzMt9 ZLobIdIPV0q8aZjX0npQFH2hAzCzFZEsjafiBSmkC9krjvHAaTYa0ZqyfSJ8PkSy6k LywhsXikY28TB3eW2Ko612L2KZ6gK+KyJXg739OA/TkEXmrU5QOXMVxiudW74ddPCJ Vvb15xvM3g2dO2lPY+t8N2Fs+LC46tj1mne3UulrO8LaNMIevGYawA4z23D5f4oioP PyLXYwhMHUyrg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0881CD5BAF; Thu, 21 May 2026 08:27:07 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Thu, 21 May 2026 08:26:59 +0000 Subject: [PATCH v3 2/2] pwm: meson: Add support for Amlogic S7 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-s6-s7-pwm-v3-2-57b073fbafef@amlogic.com> References: <20260521-s6-s7-pwm-v3-0-57b073fbafef@amlogic.com> In-Reply-To: <20260521-s6-s7-pwm-v3-0-57b073fbafef@amlogic.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779352023; l=5104; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=ee7S/9E5/xxvFyHNx3kYA681vl0XgvW4Y8eFZhpoo0U=; b=TXiAdEYbw/KybAgqyonbV6T/exp3oQ74Da0C919cp5Yin7jK9EMw1J+LofGU2rmIBRHa/Yom2 qGwM9+P1ScGAT1BFgu9YEEYa3gT6jpNbGBiMxyO/URz5UFU2L/CFeJe X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Add support for Amlogic S7 PWM. Amlogic S7 different from the previous SoCs, a controller includes one pwm, at the same time, the controller has only one input clock source. Signed-off-by: Xianwei Zhao --- drivers/pwm/pwm-meson.c | 41 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 38 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 8c6bf3d49753..66c41bf036de 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -113,6 +113,7 @@ struct meson_pwm_data { int (*channels_init)(struct pwm_chip *chip); bool has_constant; bool has_polarity; + u8 npwm; }; =20 struct meson_pwm { @@ -503,6 +504,18 @@ static void meson_pwm_s4_put_clk(void *data) clk_put(clk); } =20 +static int meson_pwm_init_channels_s7(struct pwm_chip *chip) +{ + struct device *dev =3D pwmchip_parent(chip); + struct meson_pwm *meson =3D to_meson_pwm(chip); + + meson->channels[0].clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(meson->channels[0].clk)) + return dev_err_probe(dev, PTR_ERR(meson->channels[0].clk), + "Failed to get clk\n"); + return 0; +} + static int meson_pwm_init_channels_s4(struct pwm_chip *chip) { struct device *dev =3D pwmchip_parent(chip); @@ -530,6 +543,7 @@ static int meson_pwm_init_channels_s4(struct pwm_chip *= chip) static const struct meson_pwm_data pwm_meson8b_data =3D { .parent_names =3D { "xtal", NULL, "fclk_div4", "fclk_div3" }, .channels_init =3D meson_pwm_init_channels_meson8b_legacy, + .npwm =3D MESON_NUM_PWMS, }; =20 /* @@ -539,6 +553,7 @@ static const struct meson_pwm_data pwm_meson8b_data =3D= { static const struct meson_pwm_data pwm_gxbb_ao_data =3D { .parent_names =3D { "xtal", "clk81", NULL, NULL }, .channels_init =3D meson_pwm_init_channels_meson8b_legacy, + .npwm =3D MESON_NUM_PWMS, }; =20 static const struct meson_pwm_data pwm_axg_ee_data =3D { @@ -546,6 +561,7 @@ static const struct meson_pwm_data pwm_axg_ee_data =3D { .channels_init =3D meson_pwm_init_channels_meson8b_legacy, .has_constant =3D true, .has_polarity =3D true, + .npwm =3D MESON_NUM_PWMS, }; =20 static const struct meson_pwm_data pwm_axg_ao_data =3D { @@ -553,6 +569,7 @@ static const struct meson_pwm_data pwm_axg_ao_data =3D { .channels_init =3D meson_pwm_init_channels_meson8b_legacy, .has_constant =3D true, .has_polarity =3D true, + .npwm =3D MESON_NUM_PWMS, }; =20 static const struct meson_pwm_data pwm_g12a_ee_data =3D { @@ -560,6 +577,7 @@ static const struct meson_pwm_data pwm_g12a_ee_data =3D= { .channels_init =3D meson_pwm_init_channels_meson8b_legacy, .has_constant =3D true, .has_polarity =3D true, + .npwm =3D MESON_NUM_PWMS, }; =20 static const struct meson_pwm_data pwm_g12a_ao_ab_data =3D { @@ -567,6 +585,7 @@ static const struct meson_pwm_data pwm_g12a_ao_ab_data = =3D { .channels_init =3D meson_pwm_init_channels_meson8b_legacy, .has_constant =3D true, .has_polarity =3D true, + .npwm =3D MESON_NUM_PWMS, }; =20 static const struct meson_pwm_data pwm_g12a_ao_cd_data =3D { @@ -574,22 +593,33 @@ static const struct meson_pwm_data pwm_g12a_ao_cd_dat= a =3D { .channels_init =3D meson_pwm_init_channels_meson8b_legacy, .has_constant =3D true, .has_polarity =3D true, + .npwm =3D MESON_NUM_PWMS, }; =20 static const struct meson_pwm_data pwm_meson8_v2_data =3D { .channels_init =3D meson_pwm_init_channels_meson8b_v2, + .npwm =3D MESON_NUM_PWMS, }; =20 static const struct meson_pwm_data pwm_meson_axg_v2_data =3D { .channels_init =3D meson_pwm_init_channels_meson8b_v2, .has_constant =3D true, .has_polarity =3D true, + .npwm =3D MESON_NUM_PWMS, }; =20 static const struct meson_pwm_data pwm_s4_data =3D { .channels_init =3D meson_pwm_init_channels_s4, .has_constant =3D true, .has_polarity =3D true, + .npwm =3D MESON_NUM_PWMS, +}; + +static const struct meson_pwm_data pwm_s7_data =3D { + .channels_init =3D meson_pwm_init_channels_s7, + .has_constant =3D true, + .has_polarity =3D true, + .npwm =3D 1, }; =20 static const struct of_device_id meson_pwm_matches[] =3D { @@ -642,7 +672,11 @@ static const struct of_device_id meson_pwm_matches[] = =3D { .compatible =3D "amlogic,meson-s4-pwm", .data =3D &pwm_s4_data }, - {}, + { + .compatible =3D "amlogic,s7-pwm", + .data =3D &pwm_s7_data + }, + { } }; MODULE_DEVICE_TABLE(of, meson_pwm_matches); =20 @@ -650,9 +684,10 @@ static int meson_pwm_probe(struct platform_device *pde= v) { struct pwm_chip *chip; struct meson_pwm *meson; + const struct meson_pwm_data *pdata =3D of_device_get_match_data(&pdev->de= v); int err; =20 - chip =3D devm_pwmchip_alloc(&pdev->dev, MESON_NUM_PWMS, sizeof(*meson)); + chip =3D devm_pwmchip_alloc(&pdev->dev, pdata->npwm, sizeof(*meson)); if (IS_ERR(chip)) return PTR_ERR(chip); meson =3D to_meson_pwm(chip); @@ -664,7 +699,7 @@ static int meson_pwm_probe(struct platform_device *pdev) spin_lock_init(&meson->lock); chip->ops =3D &meson_pwm_ops; =20 - meson->data =3D of_device_get_match_data(&pdev->dev); + meson->data =3D pdata; =20 err =3D meson->data->channels_init(chip); if (err < 0) --=20 2.52.0