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Replace it with the correct sequence to queue the `GetGspStaticInfo` command directly. Reviewed-by: Eliot Courtney Reviewed-by: Gary Guo Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/gsp/boot.rs | 2 +- drivers/gpu/nova-core/gsp/commands.rs | 8 +------- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index df105ef4b371..e838d61bef50 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -243,7 +243,7 @@ pub(crate) fn boot( commands::wait_gsp_init_done(&self.cmdq)?; =20 // Obtain and display basic GPU information. - let info =3D commands::get_gsp_info(&self.cmdq, bar)?; + let info =3D self.cmdq.send_command(bar, commands::GetGspStaticInf= o)?; match info.gpu_name() { Ok(name) =3D> dev_info!(pdev, "GPU name: {}\n", name), Err(e) =3D> dev_warn!(pdev, "GPU name unavailable: {:?}\n", e), diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/= gsp/commands.rs index 0da5b92f4b27..74a8a79bd2d6 100644 --- a/drivers/gpu/nova-core/gsp/commands.rs +++ b/drivers/gpu/nova-core/gsp/commands.rs @@ -18,7 +18,6 @@ }; =20 use crate::{ - driver::Bar0, gsp::{ cmdq::{ Cmdq, @@ -176,7 +175,7 @@ pub(crate) fn wait_gsp_init_done(cmdq: &Cmdq) -> Result= { } =20 /// The `GetGspStaticInfo` command. -struct GetGspStaticInfo; +pub(crate) struct GetGspStaticInfo; =20 impl CommandToGsp for GetGspStaticInfo { const FUNCTION: MsgFunction =3D MsgFunction::GetGspStaticInfo; @@ -232,8 +231,3 @@ pub(crate) fn gpu_name(&self) -> core::result::Result<&= str, GpuNameError> { .map_err(GpuNameError::InvalidUtf8) } } - -/// Send the [`GetGspInfo`] command and awaits for its reply. -pub(crate) fn get_gsp_info(cmdq: &Cmdq, bar: &Bar0) -> Result { - cmdq.send_command(bar, GetGspStaticInfo) -} --=20 2.54.0 From nobody Sun May 24 20:35:16 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013059.outbound.protection.outlook.com [40.93.201.59]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 974773D3CED; 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Furthermore it makes it impossible to create commands that have the same name as their firmware command. Thus, stop importing all commands and refer to them from the `fw` module instead. Reviewed-by: Eliot Courtney Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/gsp/commands.rs | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/= gsp/commands.rs index 74a8a79bd2d6..cc8df448ff39 100644 --- a/drivers/gpu/nova-core/gsp/commands.rs +++ b/drivers/gpu/nova-core/gsp/commands.rs @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AF= FILIATES. All rights reserved. =20 use core::{ array, @@ -26,7 +27,7 @@ NoReply, // }, fw::{ - commands::*, + self, MsgFunction, // }, }, @@ -47,12 +48,12 @@ pub(crate) fn new(pdev: &'bound pci::Device) -> Self { =20 impl<'bound> CommandToGsp for SetSystemInfo<'bound> { const FUNCTION: MsgFunction =3D MsgFunction::GspSetSystemInfo; - type Command =3D GspSetSystemInfo; + type Command =3D fw::commands::GspSetSystemInfo; type Reply =3D NoReply; type InitError =3D Error; =20 fn init(&self) -> impl Init { - GspSetSystemInfo::init(self.pdev) + Self::Command::init(self.pdev) } } =20 @@ -99,12 +100,12 @@ pub(crate) fn new() -> Self { =20 impl CommandToGsp for SetRegistry { const FUNCTION: MsgFunction =3D MsgFunction::SetRegistry; - type Command =3D PackedRegistryTable; + type Command =3D fw::commands::PackedRegistryTable; type Reply =3D NoReply; type InitError =3D Infallible; =20 fn init(&self) -> impl Init { - PackedRegistryTable::init(Self::NUM_ENTRIES as u32, self.variable_= payload_len() as u32) + Self::Command::init(Self::NUM_ENTRIES as u32, self.variable_payloa= d_len() as u32) } =20 fn variable_payload_len(&self) -> usize { @@ -112,22 +113,22 @@ fn variable_payload_len(&self) -> usize { for i in 0..Self::NUM_ENTRIES { key_size +=3D self.entries[i].key.len() + 1; // +1 for NULL te= rminator } - Self::NUM_ENTRIES * size_of::() + key_size + Self::NUM_ENTRIES * size_of::()= + key_size } =20 fn init_variable_payload( &self, dst: &mut SBufferIter>, ) -> Result { - let string_data_start_offset =3D - size_of::() + Self::NUM_ENTRIES * size_of= ::(); + let string_data_start_offset =3D size_of::() + + Self::NUM_ENTRIES * size_of::(); =20 // Array for string data. let mut string_data =3D KVec::new(); =20 for entry in self.entries.iter().take(Self::NUM_ENTRIES) { dst.write_all( - PackedRegistryEntry::new( + fw::commands::PackedRegistryEntry::new( (string_data_start_offset + string_data.len()) as u32, entry.value, ) @@ -179,12 +180,12 @@ pub(crate) fn wait_gsp_init_done(cmdq: &Cmdq) -> Resu= lt { =20 impl CommandToGsp for GetGspStaticInfo { const FUNCTION: MsgFunction =3D MsgFunction::GetGspStaticInfo; - type Command =3D GspStaticConfigInfo; + type Command =3D fw::commands::GspStaticConfigInfo; type Reply =3D GetGspStaticInfoReply; type InitError =3D Infallible; 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This is not great for several reasons, notably that it can still access shared memory areas that the kernel will now reclaim (especially problematic on setups without an IOMMU). Fix this by sending the `UNLOADING_GUEST_DRIVER` GSP command when unbinding. This stops the GSP and lets us proceed with the rest of the unbind sequence in a later patch. We make use of the `pci::Driver::unbind()` hook as we need access to the device in order to properly unbind. Reviewed-by: Eliot Courtney Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/driver.rs | 7 ++++ drivers/gpu/nova-core/gpu.rs | 7 ++++ drivers/gpu/nova-core/gsp/boot.rs | 45 +++++++++++++++++++= ++++ drivers/gpu/nova-core/gsp/commands.rs | 43 +++++++++++++++++++= +++ drivers/gpu/nova-core/gsp/fw.rs | 4 ++ drivers/gpu/nova-core/gsp/fw/commands.rs | 45 +++++++++++++++++++= ++++ drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs | 11 ++++++ 7 files changed, 162 insertions(+) diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver= .rs index 6571a8c59d09..ced1d38d206a 100644 --- a/drivers/gpu/nova-core/driver.rs +++ b/drivers/gpu/nova-core/driver.rs @@ -114,4 +114,11 @@ fn probe<'bound>( })) }) } + + fn unbind<'bound>( + dev: &'bound pci::Device, + this: Pin<&'bound Self::Data<'bound>>, + ) { + this.gpu.unbind(dev) + } } diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 4c329ab40955..75fe1bdb80fe 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -293,4 +293,11 @@ pub(crate) fn new( _: { gsp.boot(pdev, bar, spec.chipset, gsp_falcon, sec2_falcon= )? }, }) } + + pub(crate) fn unbind(&self, pdev: &'bound pci::Device) { + let _ =3D self + .gsp + .unload(pdev.as_ref(), self.bar, &self.gsp_falcon) + .inspect_err(|e| dev_err!(pdev, "failed to unload GSP: {:?}\n"= , e)); + } } diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index e838d61bef50..c123080148f1 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AF= FILIATES. All rights reserved. =20 use kernel::{ + bits, device, dma::Coherent, io::poll::read_poll_timeout, @@ -36,6 +38,7 @@ Chipset, // }, gsp::{ + cmdq::Cmdq, commands, sequencer::{ GspSequencer, @@ -251,4 +254,46 @@ pub(crate) fn boot( =20 Ok(()) } + + /// Shut down the GSP and wait until it is offline. + fn shutdown_gsp( + cmdq: &Cmdq, + bar: &Bar0, + gsp_falcon: &Falcon, + mode: commands::PowerStateLevel, + ) -> Result<()> { + // Command to shut the GSP down. + cmdq.send_command(bar, commands::UnloadingGuestDriver::new(mode))?; + + // Wait until GSP signals it is suspended. + const LIBOS_INTERRUPT_PROCESSOR_SUSPENDED: u32 =3D bits::bit_u32(3= 1); + read_poll_timeout( + || Ok(gsp_falcon.read_mailbox0(bar)), + |&mb0| mb0 & LIBOS_INTERRUPT_PROCESSOR_SUSPENDED !=3D 0, + Delta::from_millis(10), + Delta::from_secs(5), + ) + .map(|_| ()) + } + + /// Attempts to unload the GSP firmware. + /// + /// This stops all activity on the GSP. + pub(crate) fn unload( + &self, + dev: &device::Device, + bar: &Bar0, + gsp_falcon: &Falcon, + ) -> Result { + // Shut down the GSP. + Self::shutdown_gsp( + &self.cmdq, + bar, + gsp_falcon, + commands::PowerStateLevel::Level0, + ) + .inspect_err(|e| dev_err!(dev, "Unload guest driver failed: {:?}\n= ", e))?; + + Ok(()) + } } diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/= gsp/commands.rs index cc8df448ff39..1ab1f972249f 100644 --- a/drivers/gpu/nova-core/gsp/commands.rs +++ b/drivers/gpu/nova-core/gsp/commands.rs @@ -232,3 +232,46 @@ pub(crate) fn gpu_name(&self) -> core::result::Result<= &str, GpuNameError> { .map_err(GpuNameError::InvalidUtf8) } } + +pub(crate) use fw::commands::PowerStateLevel; + +/// The `UnloadingGuestDriver` command, used to shut down the GSP. +/// +/// Only used within the `gsp` module. +pub(super) struct UnloadingGuestDriver { + level: PowerStateLevel, +} + +impl UnloadingGuestDriver { + /// Creates a new `UnloadingGuestDriver` command for the given [`Power= StateLevel`]. + pub(super) fn new(level: PowerStateLevel) -> Self { + Self { level } + } +} + +impl CommandToGsp for UnloadingGuestDriver { + const FUNCTION: MsgFunction =3D MsgFunction::UnloadingGuestDriver; + type Command =3D fw::commands::UnloadingGuestDriver; + type Reply =3D UnloadingGuestDriverReply; + type InitError =3D Infallible; + + fn init(&self) -> impl Init { + fw::commands::UnloadingGuestDriver::new(self.level) + } +} + +/// The reply from the GSP to the [`UnloadingGuestDriver`] command. +pub(super) struct UnloadingGuestDriverReply; + +impl MessageFromGsp for UnloadingGuestDriverReply { + const FUNCTION: MsgFunction =3D MsgFunction::UnloadingGuestDriver; + type InitError =3D Infallible; + type Message =3D (); + + fn read( + _msg: &Self::Message, + _sbuffer: &mut SBufferIter>, + ) -> Result { + Ok(UnloadingGuestDriverReply) + } +} diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw= .rs index 3245793bbe42..33c9f5860771 100644 --- a/drivers/gpu/nova-core/gsp/fw.rs +++ b/drivers/gpu/nova-core/gsp/fw.rs @@ -279,6 +279,7 @@ pub(crate) enum MsgFunction { Nop =3D bindings::NV_VGPU_MSG_FUNCTION_NOP, SetGuestSystemInfo =3D bindings::NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM= _INFO, SetRegistry =3D bindings::NV_VGPU_MSG_FUNCTION_SET_REGISTRY, + UnloadingGuestDriver =3D bindings::NV_VGPU_MSG_FUNCTION_UNLOADING_GUES= T_DRIVER, =20 // Event codes GspInitDone =3D bindings::NV_VGPU_MSG_EVENT_GSP_INIT_DONE, @@ -323,6 +324,9 @@ fn try_from(value: u32) -> Result { Ok(MsgFunction::SetGuestSystemInfo) } bindings::NV_VGPU_MSG_FUNCTION_SET_REGISTRY =3D> Ok(MsgFunctio= n::SetRegistry), + bindings::NV_VGPU_MSG_FUNCTION_UNLOADING_GUEST_DRIVER =3D> { + Ok(MsgFunction::UnloadingGuestDriver) + } =20 // Event codes bindings::NV_VGPU_MSG_EVENT_GSP_INIT_DONE =3D> Ok(MsgFunction:= :GspInitDone), diff --git a/drivers/gpu/nova-core/gsp/fw/commands.rs b/drivers/gpu/nova-co= re/gsp/fw/commands.rs index d3ef7ecdd73e..00e54361839a 100644 --- a/drivers/gpu/nova-core/gsp/fw/commands.rs +++ b/drivers/gpu/nova-core/gsp/fw/commands.rs @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AF= FILIATES. All rights reserved. =20 use kernel::{ device, @@ -131,3 +132,47 @@ unsafe impl AsBytes for GspStaticConfigInfo {} // SAFETY: This struct only contains integer types for which all bit patte= rns // are valid. unsafe impl FromBytes for GspStaticConfigInfo {} + +/// Power level requested to the [`UnloadingGuestDriver`] command. +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u32)] +#[expect(unused)] +pub(crate) enum PowerStateLevel { + /// Full unload. + Level0 =3D bindings::NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_0, + /// S3 (suspend to RAM). + Level3 =3D bindings::NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3, + /// Hibernate (suspend to disk). + Level7 =3D bindings::NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_7, +} + +impl PowerStateLevel { + /// Returns `true` if this state represents a power management transit= ion, i.e. some GPU state + /// must survive it (as opposed to a full unload). + pub(crate) fn is_power_transition(self) -> bool { + self !=3D PowerStateLevel::Level0 + } +} + +/// Payload of the `UnloadingGuestDriver` command and message. +#[repr(transparent)] +#[derive(Clone, Copy, Debug, Zeroable)] +pub(crate) struct UnloadingGuestDriver(bindings::rpc_unloading_guest_drive= r_v1F_07); + +impl UnloadingGuestDriver { + pub(crate) fn new(level: PowerStateLevel) -> Self { + Self(bindings::rpc_unloading_guest_driver_v1F_07 { + bInPMTransition: u8::from(level.is_power_transition()), + bGc6Entering: 0, + newLevel: level as u32, + ..Zeroable::zeroed() + }) + } +} + +// SAFETY: Padding is explicit and will not contain uninitialized data. +unsafe impl AsBytes for UnloadingGuestDriver {} + +// SAFETY: This struct only contains integer types for which all bit patte= rns +// are valid. +unsafe impl FromBytes for UnloadingGuestDriver {} diff --git a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs b/drivers/gp= u/nova-core/gsp/fw/r570_144/bindings.rs index 334e8be5fde8..f82ed097b283 100644 --- a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs +++ b/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs @@ -30,6 +30,9 @@ fn fmt(&self, fmt: &mut ::core::fmt::Formatter<'_>) -> ::= core::fmt::Result { fmt.write_str("__IncompleteArrayField") } } +pub const NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_0: u32 =3D 0; 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Suggested-by: Danilo Krummrich Signed-off-by: John Hubbard Co-developed-by: Alexandre Courbot Signed-off-by: Alexandre Courbot Reviewed-by: Eliot Courtney --- drivers/gpu/nova-core/firmware/booter.rs | 31 ++++++++++++++++++++++++++++= +++ drivers/gpu/nova-core/gsp/boot.rs | 30 ++++++++--------------------= -- 2 files changed, 39 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/nova-core/firmware/booter.rs b/drivers/gpu/nova-co= re/firmware/booter.rs index de2a4536b532..e45e5dc8d5d2 100644 --- a/drivers/gpu/nova-core/firmware/booter.rs +++ b/drivers/gpu/nova-core/firmware/booter.rs @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AF= FILIATES. All rights reserved. =20 //! Support for loading and patching the `Booter` firmware. `Booter` is a = Heavy Secured firmware //! running on [`Sec2`], that is used on Turing/Ampere to load the GSP fir= mware into the GSP falcon @@ -8,6 +9,7 @@ =20 use kernel::{ device, + dma::Coherent, prelude::*, transmute::FromBytes, // }; @@ -396,6 +398,35 @@ pub(crate) fn new( ucode: ucode_signed, }) } + + /// Load and run the booter firmware on SEC2. + /// + /// Resets SEC2, loads this firmware image, then boots with the WPR me= tadata + /// address passed via the SEC2 mailboxes. + pub(crate) fn run( + &self, + dev: &device::Device, + bar: &Bar0, + sec2_falcon: &Falcon, + wpr_meta: &Coherent, + ) -> Result { + sec2_falcon.reset(bar)?; + sec2_falcon.load(dev, bar, self)?; + let wpr_handle =3D wpr_meta.dma_handle(); + let (mbox0, mbox1) =3D sec2_falcon.boot( + bar, + Some(wpr_handle as u32), + Some((wpr_handle >> 32) as u32), + )?; + dev_dbg!(dev, "SEC2 MBOX0: {:#x}, MBOX1: {:#x}\n", mbox0, mbox1); + + if mbox0 !=3D 0 { + dev_err!(dev, "Booter-load failed with error {:#x}\n", mbox0); + return Err(ENODEV); + } + + Ok(()) + } } =20 impl FalconDmaLoadable for BooterFirmware { diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index c123080148f1..4f654e10259a 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -174,15 +174,6 @@ pub(crate) fn boot( Self::run_fwsec_frts(dev, chipset, gsp_falcon, bar, &bios, &fb= _layout)?; } =20 - let booter_loader =3D BooterFirmware::new( - dev, - BooterKind::Loader, - chipset, - FIRMWARE_VERSION, - sec2_falcon, - bar, - )?; - let wpr_meta =3D Coherent::init(dev, GFP_KERNEL, GspFwWprMeta::new= (&gsp_fw, &fb_layout))?; =20 self.cmdq @@ -204,20 +195,15 @@ pub(crate) fn boot( "Using SEC2 to load and run the booter_load firmware...\n" ); =20 - sec2_falcon.reset(bar)?; - sec2_falcon.load(dev, bar, &booter_loader)?; - let wpr_handle =3D wpr_meta.dma_handle(); - let (mbox0, mbox1) =3D sec2_falcon.boot( + BooterFirmware::new( + dev, + BooterKind::Loader, + chipset, + FIRMWARE_VERSION, + sec2_falcon, bar, - Some(wpr_handle as u32), - Some((wpr_handle >> 32) as u32), - )?; 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Reorganize the boot code a bit so the chipset-specific parts are clumped together, which will make their extraction into a HAL easier. This has no effect on the GSP boot process. Reviewed-by: Eliot Courtney Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/gsp/boot.rs | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index 4f654e10259a..11b1cd2db8cb 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -169,18 +169,13 @@ pub(crate) fn boot( let fb_layout =3D FbLayout::new(chipset, bar, &gsp_fw)?; dev_dbg!(dev, "{:#x?}\n", fb_layout); =20 + let wpr_meta =3D Coherent::init(dev, GFP_KERNEL, GspFwWprMeta::new= (&gsp_fw, &fb_layout))?; + // FWSEC-FRTS is not executed on chips where the FRTS region size = is 0 (e.g. GA100). if !fb_layout.frts.is_empty() { Self::run_fwsec_frts(dev, chipset, gsp_falcon, bar, &bios, &fb= _layout)?; } =20 - let wpr_meta =3D Coherent::init(dev, GFP_KERNEL, GspFwWprMeta::new= (&gsp_fw, &fb_layout))?; - - self.cmdq - .send_command_no_wait(bar, commands::SetSystemInfo::new(pdev))= ?; - self.cmdq - .send_command_no_wait(bar, commands::SetRegistry::new())?; - gsp_falcon.reset(bar)?; let libos_handle =3D self.libos.dma_handle(); let (mbox0, mbox1) =3D gsp_falcon.boot( @@ -217,6 +212,11 @@ pub(crate) fn boot( =20 dev_dbg!(pdev, "RISC-V active? {}\n", gsp_falcon.is_riscv_active(b= ar),); =20 + self.cmdq + .send_command_no_wait(bar, commands::SetSystemInfo::new(pdev))= ?; + self.cmdq + .send_command_no_wait(bar, commands::SetRegistry::new())?; + // Create and run the GSP sequencer. let seq_params =3D GspSequencerParams { bootloader_app_version: gsp_fw.bootloader.app_version, --=20 2.54.0 From nobody Sun May 24 20:35:16 2026 Received: from BN8PR05CU002.outbound.protection.outlook.com (mail-eastus2azon11011025.outbound.protection.outlook.com [52.101.57.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA8D03806C1; Thu, 21 May 2026 13:51:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.57.25 ARC-Seal: i=2; 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Move the parts that are chipset-specific under a HAL. This does not change much at the moment, since the differences between Turing and Ampere are rather benign, but will become critical to properly support the FSP boot process used by Hopper and Blackwell. The Hopper/Blackwell support is not merged yet, so their HAL is a stub for now. This patch is intended to be a mechanical code extraction with no behavioral changes. Signed-off-by: Alexandre Courbot Reviewed-by: Eliot Courtney --- drivers/gpu/nova-core/gsp.rs | 1 + drivers/gpu/nova-core/gsp/boot.rs | 168 +++------------------------ drivers/gpu/nova-core/gsp/hal.rs | 74 ++++++++++++ drivers/gpu/nova-core/gsp/hal/gh100.rs | 50 ++++++++ drivers/gpu/nova-core/gsp/hal/tu102.rs | 206 +++++++++++++++++++++++++++++= ++++ 5 files changed, 345 insertions(+), 154 deletions(-) diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs index ba5b7f990031..38378f104068 100644 --- a/drivers/gpu/nova-core/gsp.rs +++ b/drivers/gpu/nova-core/gsp.rs @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 =20 mod boot; +mod hal; =20 use kernel::{ debugfs, diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index 11b1cd2db8cb..447c9b083039 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -6,7 +6,6 @@ device, dma::Coherent, io::poll::read_poll_timeout, - io::Io, pci, prelude::*, time::Delta, // @@ -21,122 +20,18 @@ }, fb::FbLayout, firmware::{ - booter::{ - BooterFirmware, - BooterKind, // - }, - fwsec::{ - bootloader::FwsecFirmwareWithBl, - FwsecCommand, - FwsecFirmware, // - }, gsp::GspFirmware, FIRMWARE_VERSION, // }, - gpu::{ - Architecture, - Chipset, // - }, + gpu::Chipset, gsp::{ cmdq::Cmdq, commands, - sequencer::{ - GspSequencer, - GspSequencerParams, // - }, GspFwWprMeta, // }, - regs, - vbios::Vbios, }; =20 impl super::Gsp { - /// Helper function to load and run the FWSEC-FRTS firmware and confir= m that it has properly - /// created the WPR2 region. - fn run_fwsec_frts( - dev: &device::Device, - chipset: Chipset, - falcon: &Falcon, - bar: &Bar0, - bios: &Vbios, - fb_layout: &FbLayout, - ) -> Result<()> { - // Check that the WPR2 region does not already exists - if it does= , we cannot run - // FWSEC-FRTS until the GPU is reset. - if bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI).higher_bound() !=3D= 0 { - dev_err!( - dev, - "WPR2 region already exists - GPU needs to be reset to pro= ceed\n" - ); - return Err(EBUSY); - } - - // FWSEC-FRTS will create the WPR2 region. - let fwsec_frts =3D FwsecFirmware::new( - dev, - falcon, - bar, - bios, - FwsecCommand::Frts { - frts_addr: fb_layout.frts.start, - frts_size: fb_layout.frts.len(), - }, - )?; - - if chipset.needs_fwsec_bootloader() { - let fwsec_frts_bl =3D FwsecFirmwareWithBl::new(fwsec_frts, dev= , chipset)?; - // Load and run the bootloader, which will load FWSEC-FRTS and= run it. - fwsec_frts_bl.run(dev, falcon, bar)?; - } else { - // Load and run FWSEC-FRTS directly. - fwsec_frts.run(dev, falcon, bar)?; - } - - // SCRATCH_E contains the error code for FWSEC-FRTS. - let frts_status =3D bar - .read(regs::NV_PBUS_SW_SCRATCH_0E_FRTS_ERR) - .frts_err_code(); - if frts_status !=3D 0 { - dev_err!( - dev, - "FWSEC-FRTS returned with error code {:#x}\n", - frts_status - ); - - return Err(EIO); - } - - // Check that the WPR2 region has been created as we requested. - let (wpr2_lo, wpr2_hi) =3D ( - bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_LO).lower_bound(), - bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI).higher_bound(), - ); - - match (wpr2_lo, wpr2_hi) { - (_, 0) =3D> { - dev_err!(dev, "WPR2 region not created after running FWSEC= -FRTS\n"); - - Err(EIO) - } - (wpr2_lo, _) if wpr2_lo !=3D fb_layout.frts.start =3D> { - dev_err!( - dev, - "WPR2 region created at unexpected address {:#x}; expe= cted {:#x}\n", - wpr2_lo, - fb_layout.frts.start, - ); - - Err(EIO) - } - (wpr2_lo, wpr2_hi) =3D> { - dev_dbg!(dev, "WPR2: {:#x}-{:#x}\n", wpr2_lo, wpr2_hi); - dev_dbg!(dev, "GPU instance built\n"); - - Ok(()) - } - } - } - /// Attempt to boot the GSP. /// /// This is a GPU-dependent and complex procedure that involves loadin= g firmware files from @@ -145,24 +40,15 @@ fn run_fwsec_frts( /// /// Upon return, the GSP is up and running, and its runtime object giv= en as return value. pub(crate) fn boot( - self: Pin<&mut Self>, + mut self: Pin<&mut Self>, pdev: &pci::Device, bar: &Bar0, chipset: Chipset, gsp_falcon: &Falcon, sec2_falcon: &Falcon, ) -> Result { - // The FSP boot process of Hopper+ is not supported for now. - if matches!( - chipset.arch(), - Architecture::Hopper | Architecture::BlackwellGB10x | Architec= ture::BlackwellGB20x - ) { - return Err(ENOTSUPP); - } - let dev =3D pdev.as_ref(); - - let bios =3D Vbios::new(dev, bar)?; + let hal =3D super::hal::gsp_hal(chipset); =20 let gsp_fw =3D KBox::pin_init(GspFirmware::new(dev, chipset, FIRMW= ARE_VERSION), GFP_KERNEL)?; =20 @@ -171,38 +57,21 @@ pub(crate) fn boot( =20 let wpr_meta =3D Coherent::init(dev, GFP_KERNEL, GspFwWprMeta::new= (&gsp_fw, &fb_layout))?; =20 - // FWSEC-FRTS is not executed on chips where the FRTS region size = is 0 (e.g. GA100). - if !fb_layout.frts.is_empty() { - Self::run_fwsec_frts(dev, chipset, gsp_falcon, bar, &bios, &fb= _layout)?; - } - - gsp_falcon.reset(bar)?; - let libos_handle =3D self.libos.dma_handle(); - let (mbox0, mbox1) =3D gsp_falcon.boot( - bar, - Some(libos_handle as u32), - Some((libos_handle >> 32) as u32), - )?; - dev_dbg!(pdev, "GSP MBOX0: {:#x}, MBOX1: {:#x}\n", mbox0, mbox1); - - dev_dbg!( - pdev, - "Using SEC2 to load and run the booter_load firmware...\n" - ); - - BooterFirmware::new( + // Perform the chipset-specific boot sequence. + hal.boot( + self.as_mut(), dev, - BooterKind::Loader, - chipset, - FIRMWARE_VERSION, - sec2_falcon, bar, - )? - .run(dev, bar, sec2_falcon, &wpr_meta)?; + chipset, + &fb_layout, + &wpr_meta, + gsp_falcon, + sec2_falcon, + )?; =20 gsp_falcon.write_os_version(bar, gsp_fw.bootloader.app_version); =20 - // Poll for RISC-V to become active before running sequencer + // Poll for RISC-V to become active before continuing. read_poll_timeout( || Ok(gsp_falcon.is_riscv_active(bar)), |val: &bool| *val, @@ -217,16 +86,7 @@ pub(crate) fn boot( self.cmdq .send_command_no_wait(bar, commands::SetRegistry::new())?; =20 - // Create and run the GSP sequencer. - let seq_params =3D GspSequencerParams { - bootloader_app_version: gsp_fw.bootloader.app_version, - libos_dma_handle: libos_handle, - gsp_falcon, - sec2_falcon, - dev: pdev.as_ref().into(), - bar, - }; - GspSequencer::run(&self.cmdq, seq_params)?; + hal.post_boot(self.as_mut(), dev, bar, &gsp_fw, gsp_falcon, sec2_f= alcon)?; =20 // Wait until GSP is fully initialized. commands::wait_gsp_init_done(&self.cmdq)?; diff --git a/drivers/gpu/nova-core/gsp/hal.rs b/drivers/gpu/nova-core/gsp/h= al.rs new file mode 100644 index 000000000000..ae16fd6ba7fb --- /dev/null +++ b/drivers/gpu/nova-core/gsp/hal.rs @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIA= TES. All rights reserved. + +mod gh100; +mod tu102; + +use kernel::prelude::*; + +use kernel::{ + device, + dma::Coherent, // +}; + +use crate::{ + driver::Bar0, + falcon::{ + gsp::Gsp as GspEngine, + sec2::Sec2, + Falcon, // + }, + fb::FbLayout, + firmware::gsp::GspFirmware, + gpu::{ + Architecture, + Chipset, // + }, + gsp::{ + Gsp, + GspFwWprMeta, // + }, +}; + +/// Trait implemented by GSP HALs. +pub(super) trait GspHal: Send { + /// Performs the GSP boot process, loading and running the required fi= rmwares as needed. + #[allow(clippy::too_many_arguments)] + fn boot( + &self, + gsp: Pin<&mut Gsp>, + dev: &device::Device, + bar: &Bar0, + chipset: Chipset, + fb_layout: &FbLayout, + wpr_meta: &Coherent, + gsp_falcon: &Falcon, + sec2_falcon: &Falcon, + ) -> Result; + + /// Performs HAL-specific post-GSP boot tasks. + /// + /// This method is called by the GSP boot code after the GSP is confir= med to be running, and + /// after the initialization commands have been pushed onto its queue. + fn post_boot( + &self, + _gsp: Pin<&mut Gsp>, + _dev: &device::Device, + _bar: &Bar0, + _gsp_fw: &GspFirmware, + _gsp_falcon: &Falcon, + _sec2_falcon: &Falcon, + ) -> Result { + Ok(()) + } +} + +/// Returns the GSP HAL to be used for `chipset`. +pub(super) fn gsp_hal(chipset: Chipset) -> &'static dyn GspHal { + match chipset.arch() { + Architecture::Turing | Architecture::Ampere | Architecture::Ada = =3D> tu102::TU102_HAL, + Architecture::Hopper | Architecture::BlackwellGB10x | Architecture= ::BlackwellGB20x =3D> { + gh100::GH100_HAL + } + } +} diff --git a/drivers/gpu/nova-core/gsp/hal/gh100.rs b/drivers/gpu/nova-core= /gsp/hal/gh100.rs new file mode 100644 index 000000000000..187fb7dbe40a --- /dev/null +++ b/drivers/gpu/nova-core/gsp/hal/gh100.rs @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIA= TES. All rights reserved. + +use kernel::prelude::*; + +use kernel::{ + device, + dma::Coherent, // +}; + +use crate::{ + driver::Bar0, + falcon::{ + gsp::Gsp as GspEngine, + sec2::Sec2, + Falcon, // + }, + fb::FbLayout, + gpu::Chipset, + gsp::{ + hal::GspHal, + Gsp, + GspFwWprMeta, // + }, +}; + +struct Gh100; + +impl GspHal for Gh100 { + /// Boot GSP via FSP Chain of Trust (Hopper/Blackwell+ path). + /// + /// This path uses FSP to establish a chain of trust and boot GSP-FMC.= FSP handles + /// the GSP boot internally - no manual GSP reset/boot is needed. + fn boot( + &self, + _gsp: Pin<&mut Gsp>, + _dev: &device::Device, + _bar: &Bar0, + _chipset: Chipset, + _fb_layout: &FbLayout, + _wpr_meta: &Coherent, + _gsp_falcon: &Falcon, + _sec2_falcon: &Falcon, + ) -> Result { + Err(ENOTSUPP) + } +} + +const GH100: Gh100 =3D Gh100; +pub(super) const GH100_HAL: &dyn GspHal =3D &GH100; diff --git a/drivers/gpu/nova-core/gsp/hal/tu102.rs b/drivers/gpu/nova-core= /gsp/hal/tu102.rs new file mode 100644 index 000000000000..b7a88f3ecea9 --- /dev/null +++ b/drivers/gpu/nova-core/gsp/hal/tu102.rs @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIA= TES. All rights reserved. + +use kernel::prelude::*; + +use kernel::{ + device, + dma::Coherent, + io::Io, // +}; + +use crate::{ + driver::Bar0, + falcon::{ + gsp::Gsp as GspEngine, + sec2::Sec2, + Falcon, // + }, + fb::FbLayout, + firmware::{ + booter::{ + BooterFirmware, + BooterKind, // + }, + fwsec::{ + bootloader::FwsecFirmwareWithBl, + FwsecCommand, + FwsecFirmware, // + }, + gsp::GspFirmware, + FIRMWARE_VERSION, // + }, + gpu::Chipset, + gsp::{ + hal::GspHal, + sequencer::{ + GspSequencer, + GspSequencerParams, // + }, + Gsp, + GspFwWprMeta, // + }, + regs, + vbios::Vbios, // +}; + +/// Helper function to load and run the FWSEC-FRTS firmware and confirm th= at it has properly +/// created the WPR2 region. +fn run_fwsec_frts( + dev: &device::Device, + chipset: Chipset, + falcon: &Falcon, + bar: &Bar0, + bios: &Vbios, + fb_layout: &FbLayout, +) -> Result<()> { + // Check that the WPR2 region does not already exist - if it does, we = cannot run + // FWSEC-FRTS until the GPU is reset. + if bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI).higher_bound() !=3D 0 { + dev_err!( + dev, + "WPR2 region already exists - GPU needs to be reset to proceed= \n" + ); + return Err(EBUSY); + } + + // FWSEC-FRTS will create the WPR2 region. + let fwsec_frts =3D FwsecFirmware::new( + dev, + falcon, + bar, + bios, + FwsecCommand::Frts { + frts_addr: fb_layout.frts.start, + frts_size: fb_layout.frts.len(), + }, + )?; + + if chipset.needs_fwsec_bootloader() { + let fwsec_frts_bl =3D FwsecFirmwareWithBl::new(fwsec_frts, dev, ch= ipset)?; + // Load and run the bootloader, which will load FWSEC-FRTS and run= it. + fwsec_frts_bl.run(dev, falcon, bar)?; + } else { + // Load and run FWSEC-FRTS directly. + fwsec_frts.run(dev, falcon, bar)?; + } + + // SCRATCH_E contains the error code for FWSEC-FRTS. + let frts_status =3D bar + .read(regs::NV_PBUS_SW_SCRATCH_0E_FRTS_ERR) + .frts_err_code(); + if frts_status !=3D 0 { + dev_err!( + dev, + "FWSEC-FRTS returned with error code {:#x}\n", + frts_status + ); + + return Err(EIO); + } + + // Check that the WPR2 region has been created as we requested. + let (wpr2_lo, wpr2_hi) =3D ( + bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_LO).lower_bound(), + bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI).higher_bound(), + ); + + match (wpr2_lo, wpr2_hi) { + (_, 0) =3D> { + dev_err!(dev, "WPR2 region not created after running FWSEC-FRT= S\n"); + + Err(EIO) + } + (wpr2_lo, _) if wpr2_lo !=3D fb_layout.frts.start =3D> { + dev_err!( + dev, + "WPR2 region created at unexpected address {:#x}; expected= {:#x}\n", + wpr2_lo, + fb_layout.frts.start, + ); + + Err(EIO) + } + (wpr2_lo, wpr2_hi) =3D> { + dev_dbg!(dev, "WPR2: {:#x}-{:#x}\n", wpr2_lo, wpr2_hi); + dev_dbg!(dev, "GPU instance built\n"); + + Ok(()) + } + } +} + +struct Tu102; + +impl GspHal for Tu102 { + fn boot( + &self, + gsp: Pin<&mut Gsp>, + dev: &device::Device, + bar: &Bar0, + chipset: Chipset, + fb_layout: &FbLayout, + wpr_meta: &Coherent, + gsp_falcon: &Falcon, + sec2_falcon: &Falcon, + ) -> Result { + let bios =3D Vbios::new(dev, bar)?; + + // FWSEC-FRTS is not executed on chips where the FRTS region size = is 0 (e.g. GA100). + if !fb_layout.frts.is_empty() { + run_fwsec_frts(dev, chipset, gsp_falcon, bar, &bios, fb_layout= )?; + } + + gsp_falcon.reset(bar)?; + let libos_handle =3D gsp.libos.dma_handle(); + let (mbox0, mbox1) =3D gsp_falcon.boot( + bar, + Some(libos_handle as u32), + Some((libos_handle >> 32) as u32), + )?; + dev_dbg!(dev, "GSP MBOX0: {:#x}, MBOX1: {:#x}\n", mbox0, mbox1); + + dev_dbg!( + dev, + "Using SEC2 to load and run the booter_load firmware...\n" + ); + + BooterFirmware::new( + dev, + BooterKind::Loader, + chipset, + FIRMWARE_VERSION, + sec2_falcon, + bar, + )? + .run(dev, bar, sec2_falcon, wpr_meta)?; + + Ok(()) + } + + fn post_boot( + &self, + gsp: Pin<&mut Gsp>, + dev: &device::Device, + bar: &Bar0, + gsp_fw: &GspFirmware, + gsp_falcon: &Falcon, + sec2_falcon: &Falcon, + ) -> Result { + // Create and run the GSP sequencer. + let seq_params =3D GspSequencerParams { + bootloader_app_version: gsp_fw.bootloader.app_version, + libos_dma_handle: gsp.libos.dma_handle(), + gsp_falcon, + sec2_falcon, + dev: dev.into(), + bar, + }; + GspSequencer::run(&gsp.cmdq, seq_params)?; + + Ok(()) + } +} + +const TU102: Tu102 =3D Tu102; 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These operations need to be reverted upon unloading, particularly the WPR2 secure region creation, as its presence prevents the driver from subsequently probing. Thus, prepare the Booter Unloader and FWSEC-SB firmwares when booting the GSP, so they can be executed at unbind time to put the GPU into a state where it can be probed again. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/driver.rs | 18 +++- drivers/gpu/nova-core/firmware/booter.rs | 1 - drivers/gpu/nova-core/firmware/fwsec.rs | 1 - drivers/gpu/nova-core/gpu.rs | 35 ++++++-- drivers/gpu/nova-core/gsp.rs | 3 + drivers/gpu/nova-core/gsp/boot.rs | 35 ++++++-- drivers/gpu/nova-core/gsp/hal.rs | 21 ++++- drivers/gpu/nova-core/gsp/hal/gh100.rs | 7 +- drivers/gpu/nova-core/gsp/hal/tu102.rs | 141 +++++++++++++++++++++++++++= +++- drivers/gpu/nova-core/regs.rs | 5 ++ 10 files changed, 242 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver= .rs index ced1d38d206a..20d38a64dcc7 100644 --- a/drivers/gpu/nova-core/driver.rs +++ b/drivers/gpu/nova-core/driver.rs @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 =20 +use core::cell::Cell; + use kernel::{ auxiliary, device::Core, @@ -21,7 +23,10 @@ types::ForLt, }; =20 -use crate::gpu::Gpu; +use crate::{ + gpu::Gpu, + gsp, // +}; =20 /// Counter for generating unique auxiliary device IDs. static AUXILIARY_ID_COUNTER: Atomic =3D Atomic::new(0); @@ -33,6 +38,10 @@ pub(crate) struct NovaCore<'bound> { bar: pci::Bar<'bound, BAR0_SIZE>, #[allow(clippy::type_complexity)] _reg: Devres>, + /// GSP unload bundle, if any. + /// + /// Stored into a `Cell` so it can be [taken](Cell::take) without a mu= table reference. + unload_bundle: Cell>, } =20 const BAR0_SIZE: usize =3D SZ_16M; @@ -94,6 +103,8 @@ fn probe<'bound>( // other threads of execution. unsafe { pdev.dma_set_mask_and_coherent(DmaMask::new::())? }; =20 + let mut unload_bundle =3D None; + Ok(try_pin_init!(NovaCore { bar: pdev.iomap_region_sized::(0, c"nova-core/b= ar0")?, // TODO: Use `&bar` self-referential pin-init syntax once = available. @@ -101,7 +112,7 @@ fn probe<'bound>( // SAFETY: `bar` is initialized before this expression is = evaluated // (`try_pin_init!()` initializes fields in declaration or= der), lives at a pinned // stable address, and is dropped after `gpu` (struct fiel= d drop order). - gpu <- Gpu::new(pdev, unsafe { &*core::ptr::from_ref(bar) = }), + gpu <- Gpu::new(pdev, unsafe { &*core::ptr::from_ref(bar) = }, &mut unload_bundle), _reg: auxiliary::Registration::new( pdev.as_ref(), c"nova-drm", @@ -111,6 +122,7 @@ fn probe<'bound>( crate::MODULE_NAME, (), )?, + unload_bundle: Cell::new(unload_bundle), })) }) } @@ -119,6 +131,6 @@ fn unbind<'bound>( dev: &'bound pci::Device, this: Pin<&'bound Self::Data<'bound>>, ) { - this.gpu.unbind(dev) + this.gpu.unbind(dev, this.unload_bundle.take()) } } diff --git a/drivers/gpu/nova-core/firmware/booter.rs b/drivers/gpu/nova-co= re/firmware/booter.rs index e45e5dc8d5d2..c5e17605e1a3 100644 --- a/drivers/gpu/nova-core/firmware/booter.rs +++ b/drivers/gpu/nova-core/firmware/booter.rs @@ -282,7 +282,6 @@ fn new_booter(data: &[u8]) -> Result { #[derive(Copy, Clone, Debug, PartialEq)] pub(crate) enum BooterKind { Loader, - #[expect(unused)] Unloader, } =20 diff --git a/drivers/gpu/nova-core/firmware/fwsec.rs b/drivers/gpu/nova-cor= e/firmware/fwsec.rs index 8810cb49db67..4108f28cd338 100644 --- a/drivers/gpu/nova-core/firmware/fwsec.rs +++ b/drivers/gpu/nova-core/firmware/fwsec.rs @@ -144,7 +144,6 @@ pub(crate) enum FwsecCommand { /// image into it. Frts { frts_addr: u64, frts_size: u64 }, /// Asks [`FwsecFirmware`] to load pre-OS apps on the PMU. - #[expect(dead_code)] Sb, } =20 diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 75fe1bdb80fe..5af04901b512 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -18,7 +18,10 @@ Falcon, // }, fb::SysmemFlush, - gsp::Gsp, + gsp::{ + self, + Gsp, // + }, regs, }; =20 @@ -261,10 +264,20 @@ pub(crate) struct Gpu<'bound> { } =20 impl<'bound> Gpu<'bound> { - pub(crate) fn new( + /// Create a new [`Gpu`] instance. + /// + /// `pdev` is the PCI device for the GPU, `bar` is its `Bar0` mapping. + /// + /// `unload_bundle` is an output parameter, where the [GSP unload bund= le](gsp::UnloadBundle) is + /// to be written. The driver layer will pass the written value back t= o [`Gpu::unbind`]. + pub(crate) fn new<'init>( pdev: &'bound pci::Device, bar: &'bound Bar0, - ) -> impl PinInit + 'bound { + unload_bundle: &'init mut Option, + ) -> impl PinInit + 'init + where + 'bound: 'init, + { try_pin_init!(Self { spec: Spec::new(pdev.as_ref(), bar).inspect(|spec| { dev_info!(pdev,"NVIDIA ({})\n", spec); @@ -290,14 +303,24 @@ pub(crate) fn new( =20 gsp <- Gsp::new(pdev), =20 - _: { gsp.boot(pdev, bar, spec.chipset, gsp_falcon, sec2_falcon= )? }, + _: { *unload_bundle =3D gsp.boot(pdev, bar, spec.chipset, gsp_= falcon, sec2_falcon)? }, }) } =20 - pub(crate) fn unbind(&self, pdev: &'bound pci::Device) { + pub(crate) fn unbind( + &self, + pdev: &'bound pci::Device, + unload_bundle: Option, + ) { let _ =3D self .gsp - .unload(pdev.as_ref(), self.bar, &self.gsp_falcon) + .unload( + pdev.as_ref(), + self.bar, + &self.gsp_falcon, + &self.sec2_falcon, + unload_bundle, + ) .inspect_err(|e| dev_err!(pdev, "failed to unload GSP: {:?}\n"= , e)); } } diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs index 38378f104068..1885cfa5cb38 100644 --- a/drivers/gpu/nova-core/gsp.rs +++ b/drivers/gpu/nova-core/gsp.rs @@ -185,3 +185,6 @@ pub(crate) fn new(pdev: &pci::Device) ->= impl PinInit); diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index 447c9b083039..2968178d0c6d 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -46,7 +46,7 @@ pub(crate) fn boot( chipset: Chipset, gsp_falcon: &Falcon, sec2_falcon: &Falcon, - ) -> Result { + ) -> Result> { let dev =3D pdev.as_ref(); let hal =3D super::hal::gsp_hal(chipset); =20 @@ -57,8 +57,8 @@ pub(crate) fn boot( =20 let wpr_meta =3D Coherent::init(dev, GFP_KERNEL, GspFwWprMeta::new= (&gsp_fw, &fb_layout))?; =20 - // Perform the chipset-specific boot sequence. - hal.boot( + // Perform the chipset-specific boot sequence, and retrieve the un= load bundle. + let unload_bundle =3D hal.boot( self.as_mut(), dev, bar, @@ -98,7 +98,7 @@ pub(crate) fn boot( Err(e) =3D> dev_warn!(pdev, "GPU name unavailable: {:?}\n", e), } =20 - Ok(()) + Ok(unload_bundle.map(super::UnloadBundle)) } =20 /// Shut down the GSP and wait until it is offline. @@ -130,16 +130,35 @@ pub(crate) fn unload( dev: &device::Device, bar: &Bar0, gsp_falcon: &Falcon, + sec2_falcon: &Falcon, + unload_bundle: Option, ) -> Result { - // Shut down the GSP. - Self::shutdown_gsp( + // Shut down the GSP. Keep going even in case of error. + let mut res =3D Self::shutdown_gsp( &self.cmdq, bar, gsp_falcon, commands::PowerStateLevel::Level0, ) - .inspect_err(|e| dev_err!(dev, "Unload guest driver failed: {:?}\n= ", e))?; + .inspect_err(|e| dev_err!(dev, "GSP shutdown failed: {:?}\n", e)); =20 - Ok(()) + // Run the unload bundle to reset the GSP so it can be booted agai= n. + if let Some(unload_bundle) =3D unload_bundle { + res =3D res.and( + unload_bundle + .0 + .run(dev, bar, gsp_falcon, sec2_falcon) + .inspect_err(|e| dev_err!(dev, "Unload bundle failed: = {:?}\n", e)), + ); + } else { + dev_warn!( + dev, + "Unload bundle is missing, GSP won't be properly reset.\n" + ); + + res =3D Err(EAGAIN); + } + + res.inspect(|()| dev_info!(dev, "GSP successfully unloaded\n")) } } diff --git a/drivers/gpu/nova-core/gsp/hal.rs b/drivers/gpu/nova-core/gsp/h= al.rs index ae16fd6ba7fb..fe591c124a94 100644 --- a/drivers/gpu/nova-core/gsp/hal.rs +++ b/drivers/gpu/nova-core/gsp/hal.rs @@ -30,9 +30,28 @@ }, }; =20 +/// Trait for types containing the resources and code required to fully re= set the GSP. +/// +/// The GSP unload code might run in a situation where we cannot load firm= ware dynamically (e.g. +/// because we are in shutdown and the file system is not accessible anymo= re). Thus, the firmware +/// required for unloading is prepared at load time, and stored here until= it needs to be run. +pub(super) trait UnloadBundle: Send { + /// Performs the steps required to properly reset the GSP after it has= been stopped. + fn run( + &self, + dev: &device::Device, + bar: &Bar0, + gsp_falcon: &Falcon, + sec2_falcon: &Falcon, + ) -> Result; +} + /// Trait implemented by GSP HALs. pub(super) trait GspHal: Send { /// Performs the GSP boot process, loading and running the required fi= rmwares as needed. + /// + /// Upon success, returns the [`UnloadBundle`] to be run (if any) in o= rder to properly reset the + /// GSP after it has been stopped. #[allow(clippy::too_many_arguments)] fn boot( &self, @@ -44,7 +63,7 @@ fn boot( wpr_meta: &Coherent, gsp_falcon: &Falcon, sec2_falcon: &Falcon, - ) -> Result; + ) -> Result>>; =20 /// Performs HAL-specific post-GSP boot tasks. /// diff --git a/drivers/gpu/nova-core/gsp/hal/gh100.rs b/drivers/gpu/nova-core= /gsp/hal/gh100.rs index 187fb7dbe40a..46ffc51dc385 100644 --- a/drivers/gpu/nova-core/gsp/hal/gh100.rs +++ b/drivers/gpu/nova-core/gsp/hal/gh100.rs @@ -18,7 +18,10 @@ fb::FbLayout, gpu::Chipset, gsp::{ - hal::GspHal, + hal::{ + GspHal, + UnloadBundle, // + }, Gsp, GspFwWprMeta, // }, @@ -41,7 +44,7 @@ fn boot( _wpr_meta: &Coherent, _gsp_falcon: &Falcon, _sec2_falcon: &Falcon, - ) -> Result { + ) -> Result>> { Err(ENOTSUPP) } } diff --git a/drivers/gpu/nova-core/gsp/hal/tu102.rs b/drivers/gpu/nova-core= /gsp/hal/tu102.rs index b7a88f3ecea9..fe6fcb84b03d 100644 --- a/drivers/gpu/nova-core/gsp/hal/tu102.rs +++ b/drivers/gpu/nova-core/gsp/hal/tu102.rs @@ -32,7 +32,10 @@ }, gpu::Chipset, gsp::{ - hal::GspHal, + hal::{ + GspHal, + UnloadBundle, // + }, sequencer::{ GspSequencer, GspSequencerParams, // @@ -44,6 +47,124 @@ vbios::Vbios, // }; =20 +// A ready-to-run FWSEC unload firmware. +// +// Since there are two variants of the prepared firmware (with and without= a bootloader), this type +// abstracts the difference. +enum FwsecUnloadFirmware { + WithoutBl(FwsecFirmware), + WithBl(FwsecFirmwareWithBl), +} + +impl FwsecUnloadFirmware { + /// Loads the FWSEC SB firmware, as well as its bootloader if `chipset= ` requires it. + fn new( + dev: &device::Device, + bar: &Bar0, + chipset: Chipset, + bios: &Vbios, + gsp_falcon: &Falcon, + ) -> Result { + let fwsec_sb =3D FwsecFirmware::new(dev, gsp_falcon, bar, bios, Fw= secCommand::Sb)?; + + Ok(if chipset.needs_fwsec_bootloader() { + Self::WithBl(FwsecFirmwareWithBl::new(fwsec_sb, dev, chipset)?) + } else { + Self::WithoutBl(fwsec_sb) + }) + } + + /// Runs the FWSEC SB firmware. + fn run( + &self, + dev: &device::Device, + bar: &Bar0, + gsp_falcon: &Falcon, + ) -> Result<()> { + match self { + Self::WithoutBl(fw) =3D> fw.run(dev, gsp_falcon, bar), + Self::WithBl(fw) =3D> fw.run(dev, gsp_falcon, bar), + } + } +} + +// Contains the firmware required to fully reset GSP on chipsets where the= GSP is started using +// FWSEC/Booter. +struct Sec2UnloadBundle { + fwsec_sb: FwsecUnloadFirmware, + booter_unloader: BooterFirmware, +} + +impl Sec2UnloadBundle { + /// Load and prepare the resources required to properly reset the GSP = after it has been stopped. + fn build( + dev: &device::Device, + bar: &Bar0, + chipset: Chipset, + bios: &Vbios, + gsp_falcon: &Falcon, + sec2_falcon: &Falcon, + ) -> Result> { + KBox::new( + Self { + fwsec_sb: FwsecUnloadFirmware::new(dev, bar, chipset, bios= , gsp_falcon)?, + booter_unloader: BooterFirmware::new( + dev, + BooterKind::Unloader, + chipset, + FIRMWARE_VERSION, + sec2_falcon, + bar, + )?, + }, + GFP_KERNEL, + ) + .map(|b| b as KBox) + .map_err(Into::into) + } +} + +impl UnloadBundle for Sec2UnloadBundle { + fn run( + &self, + dev: &device::Device, + bar: &Bar0, + gsp_falcon: &Falcon, + sec2_falcon: &Falcon, + ) -> Result<()> { + // Run FWSEC-SB to reset the GSP falcon to its pre-libos state. + self.fwsec_sb.run(dev, bar, gsp_falcon)?; + + // Remove WPR2 region if set. + let wpr2_hi =3D bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI); + if wpr2_hi.is_wpr2_set() { + sec2_falcon.reset(bar)?; + sec2_falcon.load(dev, bar, &self.booter_unloader)?; + + // Sentinel value to confirm that Booter Unloader has run. + const MAILBOX_SENTINEL: u32 =3D 0xff; + let (mbox0, _) =3D + sec2_falcon.boot(bar, Some(MAILBOX_SENTINEL), Some(MAILBOX= _SENTINEL))?; + if mbox0 !=3D 0 { + dev_err!(dev, "Booter Unloader returned error 0x{:x}\n", m= box0); + return Err(EINVAL); + } + + // Confirm that the WPR2 region has been removed. + let wpr2_hi =3D bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI); + if wpr2_hi.is_wpr2_set() { + dev_err!( + dev, + "WPR2 region still set after Booter Unloader returned\= n" + ); + return Err(EBUSY); + } + } + + Ok(()) + } +} + /// Helper function to load and run the FWSEC-FRTS firmware and confirm th= at it has properly /// created the WPR2 region. fn run_fwsec_frts( @@ -143,7 +264,7 @@ fn boot( wpr_meta: &Coherent, gsp_falcon: &Falcon, sec2_falcon: &Falcon, - ) -> Result { + ) -> Result>> { let bios =3D Vbios::new(dev, bar)?; =20 // FWSEC-FRTS is not executed on chips where the FRTS region size = is 0 (e.g. GA100). @@ -175,7 +296,21 @@ fn boot( )? .run(dev, bar, sec2_falcon, wpr_meta)?; =20 - Ok(()) + // Last, try and prepare the unload bundle. If this fails, the GPU= will need to be reset + // before the driver can be probed again. + let unload_bundle =3D + Sec2UnloadBundle::build(dev, bar, chipset, &bios, gsp_falcon, = sec2_falcon) + .inspect_err(|e| { + dev_warn!(dev, "Failed to prepare unload firmware: {:?= }\n", e); + dev_warn!(dev, "The GSP won't be able to unload proper= ly on unbind.\n"); + dev_warn!( + dev, + "The GPU will need to be reset before the driver c= an bind again.\n" + ); + }) + .ok(); + + Ok(unload_bundle) } =20 fn post_boot( diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 6faeed73901d..356fbf364ea5 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -175,6 +175,11 @@ impl NV_PFB_PRI_MMU_WPR2_ADDR_HI { pub(crate) fn higher_bound(self) -> u64 { u64::from(self.hi_val()) << 12 } + + /// Returns whether the WPR2 region is currently set. + pub(crate) fn is_wpr2_set(self) -> bool { + self.hi_val() !=3D 0 + } } =20 // PGSP --=20 2.54.0