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Extend the existing skip_init handling by introducing a skip_reset condition. When skip_init is active and the PHY status indicates that the PHY is already operational, skip asserting and deasserting the no-csr reset while still enabling the required resources during power-on. This allows reusing the bootloader-initialized PHY state and avoids redundant PHY reinitialization and PCIe link retraining, which can add hundred's of milliseconds of delay. This relies on the assumption that when skip_init is enabled and the PHY is reported as up, the bootloader has already configured the PHY correctly and the link is in a usable state. Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Tested-by: Qiang Yu Signed-off-by: Krishna Chaitanya Chundru --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 31 +++++++++++++++++++++-------= --- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index fed2fc9bb311..1458ac1478c7 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -4729,6 +4729,7 @@ static int qmp_pcie_init(struct phy *phy) struct qmp_pcie *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; void __iomem *pcs =3D qmp->pcs; + bool skip_reset; int ret; =20 /* @@ -4744,6 +4745,9 @@ static int qmp_pcie_init(struct phy *phy) qphy_checkbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START= ) && qphy_checkbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], cfg->pwrdn_c= trl); =20 + skip_reset =3D qmp->skip_init && !qphy_checkbits(pcs, cfg->regs[QPHY_PCS_= STATUS], + cfg->phy_status); + if (!qmp->skip_init && !cfg->tbls.serdes_num) { dev_err(qmp->dev, "Init sequence not available\n"); return -ENODATA; @@ -4767,13 +4771,15 @@ static int qmp_pcie_init(struct phy *phy) } } =20 - ret =3D reset_control_assert(qmp->nocsr_reset); - if (ret) { - dev_err(qmp->dev, "no-csr reset assert failed\n"); - goto err_assert_reset; - } + if (!skip_reset) { + ret =3D reset_control_assert(qmp->nocsr_reset); + if (ret) { + dev_err(qmp->dev, "no-csr reset assert failed\n"); + goto err_assert_reset; + } =20 - usleep_range(200, 300); + usleep_range(200, 300); + } =20 if (!qmp->skip_init) { ret =3D reset_control_bulk_deassert(cfg->num_resets, qmp->resets); @@ -4823,8 +4829,11 @@ static int qmp_pcie_power_on(struct phy *phy) void __iomem *pcs =3D qmp->pcs; void __iomem *status; unsigned int mask, val; + bool skip_reset; int ret; =20 + skip_reset =3D qmp->skip_init && !qphy_checkbits(pcs, cfg->regs[QPHY_PCS_= STATUS], + cfg->phy_status); /* * Write CSR register for PHY that doesn't support no_csr reset or has not * been initialized. @@ -4848,10 +4857,12 @@ static int qmp_pcie_power_on(struct phy *phy) if (ret) return ret; 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Requesting the GPIO with GPIOD_OUT_HIGH forces the line high during probe, which can unintentionally assert reset on devices already out of reset and break proper link sequencing. Change the request to use GPIOD_ASIS so the driver preserves the existing GPIO state configured by the bootloader or firmware. This allows platforms that manage PERST# externally to maintain correct reset sequencing. PERST# is asserted explicitly later during qcom_pcie_host_init(), so forcing it high at probe time is unnecessary. Tested-by: Qiang Yu Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index af6bf5cce65b..bfe873cbf44f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1707,7 +1707,7 @@ static int qcom_pcie_parse_perst(struct qcom_pcie *pc= ie, goto parse_child_node; =20 reset =3D devm_fwnode_gpiod_get(dev, of_fwnode_handle(np), "reset", - GPIOD_OUT_HIGH, "PERST#"); + GPIOD_ASIS, "PERST#"); if (IS_ERR(reset)) { /* * FIXME: GPIOLIB currently supports exclusive GPIO access only. @@ -1812,7 +1812,7 @@ static int qcom_pcie_parse_legacy_binding(struct qcom= _pcie *pcie) if (IS_ERR(phy)) return PTR_ERR(phy); =20 - reset =3D devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); + reset =3D devm_gpiod_get_optional(dev, "perst", GPIOD_ASIS); if (IS_ERR(reset)) return PTR_ERR(reset); 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Thu, 21 May 2026 05:57:13 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c85198f508bsm357984a12.20.2026.05.21.05.57.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 05:57:13 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Thu, 21 May 2026 18:26:35 +0530 Subject: [PATCH v2 3/4] PCI: qcom: Add link retention support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-link_retain-v2-3-08ed448b081c@oss.qualcomm.com> References: <20260521-link_retain-v2-0-08ed448b081c@oss.qualcomm.com> In-Reply-To: <20260521-link_retain-v2-0-08ed448b081c@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Philipp Zabel , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Krishna Chaitanya Chundru , Qiang Yu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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Reinitializing the controller and toggling PERST# in such cases is unnecessary when the driver does not need to retrain the link. Introduce link_retain in both qcom_pcie_cfg and qcom_pcie to indicate when link retention is supported. During initialization, check the LTSSM state; if the link is already in L0 or L1 idle and LTSSM is enabled, set link_retain and skip controller reset, PERST# toggling, and other post- init steps. If the current link speed or lane width does not satisfy the constraints specified by max-link-speed or num-lanes in the device tree, fall back to normal initialization and retrain the link instead of retaining it. Configure the DBI and ATU base addresses in the retention path, since the bootloader may use different base addresses than those provided by the device tree. Also fix the -EPROBE_DEFER error handling path to return 0 instead of propagating the error, avoiding unnecessary cleanup when probe deferral is requested. Tested-by: Qiang Yu Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware.h | 1 + drivers/pci/controller/dwc/pcie-qcom.c | 62 ++++++++++++++++++++++++= +--- 2 files changed, 58 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 3e69ef60165b..be6c4abf31e8 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -450,6 +450,7 @@ struct dw_pcie_rp { bool ecam_enabled; bool native_ecam; bool skip_l23_ready; + bool link_retain; }; =20 struct dw_pcie_ep_ops { diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index bfe873cbf44f..b061eaa227b3 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -253,12 +253,14 @@ struct qcom_pcie_ops { * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache * snooping * @firmware_managed: Set if the Root Complex is firmware managed + * @link_retain: Set if controller supports retaining link from bootloader */ struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; bool override_no_snoop; bool firmware_managed; bool no_l0s; + bool link_retain; }; =20 struct qcom_pcie_perst { @@ -960,6 +962,42 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_p= cie *pcie) return 0; } =20 +/* + * Determine whether the link established by the bootloader can be reused. + * + * Reuse the existing link only if its current speed and lane count match + * the max-link-speed and num-lanes specified in Device Tree; otherwise, + * retrain the link. + */ +static bool qcom_pcie_check_link_retain(struct qcom_pcie *pcie) +{ + u32 cap, speed, val, ltssm, width; + struct dw_pcie *pci =3D pcie->pci; + u8 offset; + + val =3D readl(pcie->parf + PARF_LTSSM); + ltssm =3D val & 0x1f; + if ((val & LTSSM_EN) && + (ltssm =3D=3D DW_PCIE_LTSSM_L0 || ltssm =3D=3D DW_PCIE_LTSSM_L1_IDLE)= ) { + qcom_pcie_configure_dbi_atu_base(pcie); + + offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + cap =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); + speed =3D FIELD_GET(PCI_EXP_LNKCAP_SLS, cap); + width =3D dw_pcie_link_get_max_link_width(pci); + + if (pci->max_link_speed > 0 && speed > pci->max_link_speed) + return false; + + if (pci->num_lanes > 0 && width > pci->num_lanes) + return false; + + return true; + } + + return false; +} + static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res =3D &pcie->res.v2_7_0; @@ -978,6 +1016,14 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pci= e) if (ret < 0) goto err_disable_regulators; =20 + if (pcie->cfg->link_retain) { + pci->pp.link_retain =3D qcom_pcie_check_link_retain(pcie); + if (pci->pp.link_retain) { + dev_info(dev, "Retaining PCIe link\n"); + return 0; + } + } + ret =3D reset_control_assert(res->rst); if (ret) { dev_err(dev, "reset assert failed (%d)\n", ret); @@ -1038,6 +1084,9 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie= *pcie) { const struct qcom_pcie_cfg *pcie_cfg =3D pcie->cfg; =20 + if (pcie->pci->pp.link_retain) + return 0; + if (pcie_cfg->override_no_snoop) writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN, pcie->parf + PARF_NO_SNOOP_OVERRIDE); @@ -1294,12 +1343,13 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *p= p) struct qcom_pcie *pcie =3D to_qcom_pcie(pci); int ret; =20 - qcom_pcie_perst_assert(pcie); - ret =3D pcie->cfg->ops->init(pcie); if (ret) return ret; =20 + if (!pp->link_retain) + qcom_pcie_perst_assert(pcie); + ret =3D qcom_pcie_phy_power_on(pcie); if (ret) goto err_deinit; @@ -1322,7 +1372,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) dw_pcie_remove_capability(pcie->pci, PCI_CAP_ID_MSIX); dw_pcie_remove_ext_capability(pcie->pci, PCI_EXT_CAP_ID_DPC); =20 - qcom_pcie_perst_deassert(pcie); + if (!pp->link_retain) + qcom_pcie_perst_deassert(pcie); =20 if (pcie->cfg->ops->config_sid) { ret =3D pcie->cfg->ops->config_sid(pcie); @@ -1337,8 +1388,9 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) err_pwrctrl_power_off: pci_pwrctrl_power_off_devices(pci->dev); err_pwrctrl_destroy: - if (ret !=3D -EPROBE_DEFER) - pci_pwrctrl_destroy_devices(pci->dev); + if (pp->link_retain && ret =3D=3D -EPROBE_DEFER) + return 0; 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To take advantage of this, introduce a specific configuration (cfg_x1e80100) with link_retain =3D true and update the device match table to use it. Tested-by: Qiang Yu Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index b061eaa227b3..8496eb87debb 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1557,6 +1557,12 @@ static const struct qcom_pcie_cfg cfg_sc8280xp =3D { .no_l0s =3D true, }; =20 +static const struct qcom_pcie_cfg cfg_x1e80100 =3D { + .ops =3D &ops_1_21_0, + .no_l0s =3D true, + .link_retain =3D true, +}; + static const struct qcom_pcie_cfg cfg_fw_managed =3D { .firmware_managed =3D true, }; @@ -2199,7 +2205,7 @@ static const struct of_device_id qcom_pcie_match[] = =3D { { .compatible =3D "qcom,pcie-sm8450-pcie0", .data =3D &cfg_1_9_0 }, { .compatible =3D "qcom,pcie-sm8450-pcie1", .data =3D &cfg_1_9_0 }, { .compatible =3D "qcom,pcie-sm8550", .data =3D &cfg_1_9_0 }, - { .compatible =3D "qcom,pcie-x1e80100", .data =3D &cfg_sc8280xp }, + { .compatible =3D "qcom,pcie-x1e80100", .data =3D &cfg_x1e80100 }, { } }; =20 --=20 2.34.1