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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bea917318esm10435555ad.5.2026.05.21.05.16.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 05:16:43 -0700 (PDT) From: Yingchao Deng Date: Thu, 21 May 2026 20:16:27 +0800 Subject: [PATCH v9 1/4] coresight: cti: Convert trigger usage fields to dynamic Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-extended_cti-v9-1-d21f4f92c51e@oss.qualcomm.com> References: <20260521-extended_cti-v9-0-d21f4f92c51e@oss.qualcomm.com> In-Reply-To: <20260521-extended_cti-v9-0-d21f4f92c51e@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, jinlong.mao@oss.qualcomm.com, quic_yingdeng@quicinc.com, tingwei.zhang@oss.qualcomm.com, jie.gan@oss.qualcomm.com, Yingchao Deng X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779365796; l=11942; i=yingchao.deng@oss.qualcomm.com; s=20260521; h=from:subject:message-id; bh=ASJNP5SBvgtIXKX3zaln4ApjABeRa1GyYs6c5sAJhcY=; b=pqvzih8zamQbzAQAKdKnL2RCyGJYp0rit2wZng6X5zLXerX6fP2V5OpirF0l5r6U65tKsiSlm xqXocWuyu9VBXnfrgHbSDlUrJ3nnXWmSPVfX0RqCAZaTXe1Di4dhYvC X-Developer-Key: i=yingchao.deng@oss.qualcomm.com; a=ed25519; pk=YbHeeX0Qzqo7voZLva784lFhVChB9yF3a4sceW95ljA= X-Authority-Analysis: v=2.4 cv=c/ibhx9l c=1 sm=1 tr=0 ts=6a0ef7ad cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=7_BDbhMBoegF64a6bMcA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: PwHEYarhbsPsHzsFZreQUvYP4UHxVReQ X-Proofpoint-ORIG-GUID: PwHEYarhbsPsHzsFZreQUvYP4UHxVReQ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIxMDEyMyBTYWx0ZWRfXxQ2e1VWmatCW oTv/lbXAjOjkbfYULeNPOGF1E4bz3flLXzonGxwMnM8GVKSCjHUArRkf3IQLiz47Hj4EaeofU2a An2f55tGaRXo7rKyvled6j1eZ4uA3RH0GCY/MnyFtqpQXpNzJ8LW6n5pwNZGbI2OWiUin5qA+tA amEyBzdYAywvCDZTCOWLM0NcGu9543x8D+Mg251AZWQkwmfD5AaECcN7MUGaW+QZ8RXLEeJg4NM wm6S4jvkYhq3zpbvXpkwZ8xrQcn7wN0jOxNu8KRa23GVCWm0vvCVkCOi7GXvDGVYZCOeT9rxhRK kBGyz0xwJhtJ8UiLbr/Y7hiU3DFePIB8eearmgWYpsKJgsbveHsBaGFnZQ1DJZFbwmZlGWQBHJc HnK1SBVB3WyAXN9G3VUYI9uPTWiFQyepOO3gChUQCB8+by+HgC3q/HzyT9gEq2SWOWBYrsXObYL WnS8TWCVUiZtWjfqCLA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-21_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 priorityscore=1501 phishscore=0 bulkscore=0 clxscore=1015 malwarescore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605210123 Replace the fixed-size u32 fields in the cti_config and cti_trig_grp structure with dynamically allocated bitmaps and arrays. This allows memory to be allocated based on the actual number of triggers during probe time, reducing memory footprint and improving scalability for platforms with varying trigger counts. Signed-off-by: Yingchao Deng --- drivers/hwtracing/coresight/coresight-cti-core.c | 59 +++++++++++++++++-= ---- .../hwtracing/coresight/coresight-cti-platform.c | 26 +++++++--- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 14 ++--- drivers/hwtracing/coresight/coresight-cti.h | 12 ++--- 4 files changed, 76 insertions(+), 35 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwt= racing/coresight/coresight-cti-core.c index 2f4c9362709a..4e7d12bd2d3e 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -161,8 +161,8 @@ void cti_write_intack(struct device *dev, u32 ackval) /* DEVID[19:16] - number of CTM channels */ #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19)) =20 -static void cti_set_default_config(struct device *dev, - struct cti_drvdata *drvdata) +static int cti_set_default_config(struct device *dev, + struct cti_drvdata *drvdata) { struct cti_config *config =3D &drvdata->config; u32 devid; @@ -181,6 +181,26 @@ static void cti_set_default_config(struct device *dev, config->nr_trig_max =3D CTIINOUTEN_MAX; } =20 + config->trig_in_use =3D devm_bitmap_zalloc(dev, config->nr_trig_max, GFP_= KERNEL); + if (!config->trig_in_use) + return -ENOMEM; + + config->trig_out_use =3D devm_bitmap_zalloc(dev, config->nr_trig_max, GFP= _KERNEL); + if (!config->trig_out_use) + return -ENOMEM; + + config->trig_out_filter =3D devm_bitmap_zalloc(dev, config->nr_trig_max, = GFP_KERNEL); + if (!config->trig_out_filter) + return -ENOMEM; + + config->ctiinen =3D devm_kcalloc(dev, config->nr_trig_max, sizeof(u32), G= FP_KERNEL); + if (!config->ctiinen) + return -ENOMEM; + + config->ctiouten =3D devm_kcalloc(dev, config->nr_trig_max, sizeof(u32), = GFP_KERNEL); + if (!config->ctiouten) + return -ENOMEM; + config->nr_ctm_channels =3D CTI_DEVID_CTMCHANNELS(devid); =20 /* Most regs default to 0 as zalloc'ed except...*/ @@ -189,6 +209,7 @@ static void cti_set_default_config(struct device *dev, config->enable_req_count =3D 0; =20 config->asicctl_impl =3D !!FIELD_GET(GENMASK(4, 0), devid); + return 0; } =20 /* @@ -219,8 +240,10 @@ int cti_add_connection_entry(struct device *dev, struc= t cti_drvdata *drvdata, cti_dev->nr_trig_con++; =20 /* add connection usage bit info to overall info */ - drvdata->config.trig_in_use |=3D tc->con_in->used_mask; - drvdata->config.trig_out_use |=3D tc->con_out->used_mask; + bitmap_or(drvdata->config.trig_in_use, drvdata->config.trig_in_use, + tc->con_in->used_mask, drvdata->config.nr_trig_max); + bitmap_or(drvdata->config.trig_out_use, drvdata->config.trig_out_use, + tc->con_out->used_mask, drvdata->config.nr_trig_max); =20 return 0; } @@ -231,6 +254,8 @@ struct cti_trig_con *cti_allocate_trig_con(struct devic= e *dev, int in_sigs, { struct cti_trig_con *tc =3D NULL; struct cti_trig_grp *in =3D NULL, *out =3D NULL; + struct cti_drvdata *drvdata =3D dev_get_drvdata(dev); + int n_trigs =3D drvdata->config.nr_trig_max; =20 tc =3D devm_kzalloc(dev, sizeof(struct cti_trig_con), GFP_KERNEL); if (!tc) @@ -242,12 +267,20 @@ struct cti_trig_con *cti_allocate_trig_con(struct dev= ice *dev, int in_sigs, if (!in) return NULL; =20 + in->used_mask =3D devm_bitmap_zalloc(dev, n_trigs, GFP_KERNEL); + if (!in->used_mask) + return NULL; + out =3D devm_kzalloc(dev, offsetof(struct cti_trig_grp, sig_types[out_sigs]), GFP_KERNEL); if (!out) return NULL; =20 + out->used_mask =3D devm_bitmap_zalloc(dev, n_trigs, GFP_KERNEL); + if (!out->used_mask) + return NULL; + tc->con_in =3D in; tc->con_out =3D out; tc->con_in->nr_sigs =3D in_sigs; @@ -263,7 +296,6 @@ int cti_add_default_connection(struct device *dev, stru= ct cti_drvdata *drvdata) { int ret =3D 0; int n_trigs =3D drvdata->config.nr_trig_max; - u32 n_trig_mask =3D GENMASK(n_trigs - 1, 0); struct cti_trig_con *tc =3D NULL; =20 /* @@ -274,8 +306,8 @@ int cti_add_default_connection(struct device *dev, stru= ct cti_drvdata *drvdata) if (!tc) return -ENOMEM; =20 - tc->con_in->used_mask =3D n_trig_mask; - tc->con_out->used_mask =3D n_trig_mask; + bitmap_fill(tc->con_in->used_mask, n_trigs); + bitmap_fill(tc->con_out->used_mask, n_trigs); ret =3D cti_add_connection_entry(dev, drvdata, tc, NULL, "default"); return ret; } @@ -288,7 +320,6 @@ int cti_channel_trig_op(struct device *dev, enum cti_ch= an_op op, { struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *config =3D &drvdata->config; - u32 trig_bitmask; u32 chan_bitmask; u32 reg_value; int reg_offset; @@ -298,18 +329,16 @@ int cti_channel_trig_op(struct device *dev, enum cti_= chan_op op, (trigger_idx >=3D config->nr_trig_max)) return -EINVAL; =20 - trig_bitmask =3D BIT(trigger_idx); - /* ensure registered triggers and not out filtered */ if (direction =3D=3D CTI_TRIG_IN) { - if (!(trig_bitmask & config->trig_in_use)) + if (!(test_bit(trigger_idx, config->trig_in_use))) return -EINVAL; } else { - if (!(trig_bitmask & config->trig_out_use)) + if (!(test_bit(trigger_idx, config->trig_out_use))) return -EINVAL; =20 if ((config->trig_filter_enable) && - (config->trig_out_filter & trig_bitmask)) + test_bit(trigger_idx, config->trig_out_filter)) return -EINVAL; } =20 @@ -687,7 +716,9 @@ static int cti_probe(struct amba_device *adev, const st= ruct amba_id *id) raw_spin_lock_init(&drvdata->spinlock); =20 /* initialise CTI driver config values */ - cti_set_default_config(dev, drvdata); + ret =3D cti_set_default_config(dev, drvdata); + if (ret) + return ret; =20 pdata =3D coresight_cti_get_platform_data(dev); if (IS_ERR(pdata)) { diff --git a/drivers/hwtracing/coresight/coresight-cti-platform.c b/drivers= /hwtracing/coresight/coresight-cti-platform.c index d6d5388705c3..ba5a7e4b6bff 100644 --- a/drivers/hwtracing/coresight/coresight-cti-platform.c +++ b/drivers/hwtracing/coresight/coresight-cti-platform.c @@ -136,8 +136,8 @@ static int cti_plat_create_v8_etm_connection(struct dev= ice *dev, goto create_v8_etm_out; =20 /* build connection data */ - tc->con_in->used_mask =3D 0xF0; /* sigs <4,5,6,7> */ - tc->con_out->used_mask =3D 0xF0; /* sigs <4,5,6,7> */ + bitmap_set(tc->con_in->used_mask, 4, 4); /* sigs <4,5,6,7> */ + bitmap_set(tc->con_out->used_mask, 4, 4); /* sigs <4,5,6,7> */ =20 /* * The EXTOUT type signals from the ETM are connected to a set of input @@ -194,10 +194,10 @@ static int cti_plat_create_v8_connections(struct devi= ce *dev, goto of_create_v8_out; =20 /* Set the v8 PE CTI connection data */ - tc->con_in->used_mask =3D 0x3; /* sigs <0 1> */ + bitmap_set(tc->con_in->used_mask, 0, 2); /* sigs <0 1> */ tc->con_in->sig_types[0] =3D PE_DBGTRIGGER; tc->con_in->sig_types[1] =3D PE_PMUIRQ; - tc->con_out->used_mask =3D 0x7; /* sigs <0 1 2 > */ + bitmap_set(tc->con_out->used_mask, 0, 3); /* sigs <0 1 2 > */ tc->con_out->sig_types[0] =3D PE_EDBGREQ; tc->con_out->sig_types[1] =3D PE_DBGRESTART; tc->con_out->sig_types[2] =3D PE_CTIIRQ; @@ -213,7 +213,7 @@ static int cti_plat_create_v8_connections(struct device= *dev, goto of_create_v8_out; =20 /* filter pe_edbgreq - PE trigout sig <0> */ - drvdata->config.trig_out_filter |=3D 0x1; + set_bit(0, drvdata->config.trig_out_filter); =20 of_create_v8_out: return ret; @@ -257,7 +257,7 @@ static int cti_plat_read_trig_group(struct cti_trig_grp= *tgrp, if (!err) { /* set the signal usage mask */ for (idx =3D 0; idx < tgrp->nr_sigs; idx++) - tgrp->used_mask |=3D BIT(values[idx]); + set_bit(values[idx], tgrp->used_mask); } =20 kfree(values); @@ -316,24 +316,34 @@ static int cti_plat_process_filter_sigs(struct cti_dr= vdata *drvdata, { struct cti_trig_grp *tg =3D NULL; int err =3D 0, nr_filter_sigs; + int nr_trigs =3D drvdata->config.nr_trig_max; =20 nr_filter_sigs =3D cti_plat_count_sig_elements(fwnode, CTI_DT_FILTER_OUT_SIGS); if (nr_filter_sigs =3D=3D 0) return 0; =20 - if (nr_filter_sigs > drvdata->config.nr_trig_max) + if (nr_filter_sigs > nr_trigs) return -EINVAL; =20 tg =3D kzalloc_obj(*tg); if (!tg) return -ENOMEM; =20 + tg->used_mask =3D bitmap_zalloc(nr_trigs, GFP_KERNEL); + if (!tg->used_mask) { + kfree(tg); + return -ENOMEM; + } + tg->nr_sigs =3D nr_filter_sigs; err =3D cti_plat_read_trig_group(tg, fwnode, CTI_DT_FILTER_OUT_SIGS); if (!err) - drvdata->config.trig_out_filter |=3D tg->used_mask; + bitmap_or(drvdata->config.trig_out_filter, + drvdata->config.trig_out_filter, + tg->used_mask, nr_trigs); =20 + bitmap_free(tg->used_mask); kfree(tg); return err; } diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hw= tracing/coresight/coresight-cti-sysfs.c index 3fe2c916d228..2bbfa405cb6b 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -719,12 +719,12 @@ static ssize_t trigout_filtered_show(struct device *d= ev, struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *cfg =3D &drvdata->config; int nr_trig_max =3D cfg->nr_trig_max; - unsigned long mask =3D cfg->trig_out_filter; + unsigned long *mask =3D cfg->trig_out_filter; =20 - if (mask =3D=3D 0) + if (bitmap_empty(mask, nr_trig_max)) return 0; =20 - return sysfs_emit(buf, "%*pbl\n", nr_trig_max, &mask); + return sysfs_emit(buf, "%*pbl\n", nr_trig_max, mask); } static DEVICE_ATTR_RO(trigout_filtered); =20 @@ -931,9 +931,9 @@ static ssize_t trigin_sig_show(struct device *dev, struct cti_trig_con *con =3D (struct cti_trig_con *)ext_attr->var; struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *cfg =3D &drvdata->config; - unsigned long mask =3D con->con_in->used_mask; + unsigned long *mask =3D con->con_in->used_mask; =20 - return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, &mask); + return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, mask); } =20 static ssize_t trigout_sig_show(struct device *dev, @@ -945,9 +945,9 @@ static ssize_t trigout_sig_show(struct device *dev, struct cti_trig_con *con =3D (struct cti_trig_con *)ext_attr->var; struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *cfg =3D &drvdata->config; - unsigned long mask =3D con->con_out->used_mask; + unsigned long *mask =3D con->con_out->used_mask; =20 - return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, &mask); + return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, mask); } =20 /* convert a sig type id to a name */ diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracin= g/coresight/coresight-cti.h index c5f9e79fabc6..ef079fc18b72 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -68,7 +68,7 @@ struct fwnode_handle; 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Add reg_addr and reg_index_addr convenience macros for zero-index and indexed access respectively. Extend cs_off_attribute with a u32 index field and update cti_read_single_reg() and cti_write_single_reg() to accept separate offset and index parameters, allowing sysfs show/store handlers to use the attribute's index field directly. Signed-off-by: Yingchao Deng --- drivers/hwtracing/coresight/coresight-cti-core.c | 45 ++++++++++++++-----= ---- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 25 +++++++------ drivers/hwtracing/coresight/coresight-cti.h | 9 +++-- drivers/hwtracing/coresight/coresight-priv.h | 4 +- 4 files changed, 50 insertions(+), 33 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwt= racing/coresight/coresight-cti-core.c index 4e7d12bd2d3e..c5cc2706e241 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -42,6 +42,15 @@ static DEFINE_MUTEX(ect_mutex); #define csdev_to_cti_drvdata(csdev) \ dev_get_drvdata(csdev->dev.parent) =20 +static void __iomem *__reg_addr(struct cti_drvdata *drvdata, u32 off, + u32 index) +{ + return drvdata->base + off + sizeof(u32) * index; +} + +#define reg_addr(drvdata, off) __reg_addr((drvdata), (off), 0) +#define reg_index_addr(drvdata, off, i) __reg_addr((drvdata), (off), (i)) + /* write set of regs to hardware - call with spinlock claimed */ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) { @@ -55,16 +64,17 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) =20 /* write the CTI trigger registers */ for (i =3D 0; i < config->nr_trig_max; i++) { - writel_relaxed(config->ctiinen[i], drvdata->base + CTIINEN(i)); + writel_relaxed(config->ctiinen[i], + reg_index_addr(drvdata, CTIINEN, i)); writel_relaxed(config->ctiouten[i], - drvdata->base + CTIOUTEN(i)); + reg_index_addr(drvdata, CTIOUTEN, i)); } =20 /* other regs */ - writel_relaxed(config->ctigate, drvdata->base + CTIGATE); + writel_relaxed(config->ctigate, reg_addr(drvdata, CTIGATE)); if (config->asicctl_impl) - writel_relaxed(config->asicctl, drvdata->base + ASICCTL); - writel_relaxed(config->ctiappset, drvdata->base + CTIAPPSET); + writel_relaxed(config->asicctl, reg_addr(drvdata, ASICCTL)); + writel_relaxed(config->ctiappset, reg_addr(drvdata, CTIAPPSET)); =20 /* re-enable CTI */ writel_relaxed(1, drvdata->base + CTICONTROL); @@ -122,21 +132,22 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) return 0; } =20 -u32 cti_read_single_reg(struct cti_drvdata *drvdata, int offset) +u32 cti_read_single_reg(struct cti_drvdata *drvdata, u32 off, u32 index) { - int val; + u32 val; =20 CS_UNLOCK(drvdata->base); - val =3D readl_relaxed(drvdata->base + offset); + val =3D readl_relaxed(reg_index_addr(drvdata, off, index)); CS_LOCK(drvdata->base); =20 return val; } =20 -void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 val= ue) +void cti_write_single_reg(struct cti_drvdata *drvdata, u32 off, u32 index, + u32 value) { CS_UNLOCK(drvdata->base); - writel_relaxed(value, drvdata->base + offset); + writel_relaxed(value, reg_index_addr(drvdata, off, index)); CS_LOCK(drvdata->base); } =20 @@ -149,7 +160,7 @@ void cti_write_intack(struct device *dev, u32 ackval) =20 /* write if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, CTIINTACK, ackval); + cti_write_single_reg(drvdata, CTIINTACK, 0, ackval); } =20 /* @@ -322,7 +333,7 @@ int cti_channel_trig_op(struct device *dev, enum cti_ch= an_op op, struct cti_config *config =3D &drvdata->config; u32 chan_bitmask; u32 reg_value; - int reg_offset; + u32 reg_offset; =20 /* ensure indexes in range */ if ((channel_idx >=3D config->nr_ctm_channels) || @@ -344,8 +355,7 @@ int cti_channel_trig_op(struct device *dev, enum cti_ch= an_op op, =20 /* update the local register values */ chan_bitmask =3D BIT(channel_idx); - reg_offset =3D (direction =3D=3D CTI_TRIG_IN ? CTIINEN(trigger_idx) : - CTIOUTEN(trigger_idx)); + reg_offset =3D (direction =3D=3D CTI_TRIG_IN ? CTIINEN : CTIOUTEN); =20 guard(raw_spinlock_irqsave)(&drvdata->spinlock); =20 @@ -365,7 +375,8 @@ int cti_channel_trig_op(struct device *dev, enum cti_ch= an_op op, =20 /* write through if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, reg_offset, reg_value); + cti_write_single_reg(drvdata, reg_offset, trigger_idx, + reg_value); =20 return 0; } @@ -403,7 +414,7 @@ int cti_channel_gate_op(struct device *dev, enum cti_ch= an_gate_op op, if (err =3D=3D 0) { config->ctigate =3D reg_value; if (cti_is_active(config)) - cti_write_single_reg(drvdata, CTIGATE, reg_value); + cti_write_single_reg(drvdata, CTIGATE, 0, reg_value); } =20 return err; @@ -452,7 +463,7 @@ int cti_channel_setop(struct device *dev, enum cti_chan= _set_op op, } =20 if ((err =3D=3D 0) && cti_is_active(config)) - cti_write_single_reg(drvdata, reg_offset, reg_value); + cti_write_single_reg(drvdata, reg_offset, 0, reg_value); =20 return err; } diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hw= tracing/coresight/coresight-cti-sysfs.c index 2bbfa405cb6b..7191a478b2da 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -171,7 +171,7 @@ static ssize_t coresight_cti_reg_show(struct device *de= v, pm_runtime_get_sync(dev->parent); =20 scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) - val =3D cti_read_single_reg(drvdata, cti_attr->off); + val =3D cti_read_single_reg(drvdata, cti_attr->off, cti_attr->index); =20 pm_runtime_put_sync(dev->parent); return sysfs_emit(buf, "0x%x\n", val); @@ -192,7 +192,7 @@ static __maybe_unused ssize_t coresight_cti_reg_store(s= truct device *dev, pm_runtime_get_sync(dev->parent); =20 scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) - cti_write_single_reg(drvdata, cti_attr->off, val); + cti_write_single_reg(drvdata, cti_attr->off, cti_attr->index, val); =20 pm_runtime_put_sync(dev->parent); return size; @@ -202,7 +202,8 @@ static __maybe_unused ssize_t coresight_cti_reg_store(s= truct device *dev, (&((struct cs_off_attribute[]) { \ { \ __ATTR(name, 0444, coresight_cti_reg_show, NULL), \ - offset \ + offset, \ + 0 \ } \ })[0].attr.attr) =20 @@ -211,7 +212,8 @@ static __maybe_unused ssize_t coresight_cti_reg_store(s= truct device *dev, { \ __ATTR(name, 0644, coresight_cti_reg_show, \ coresight_cti_reg_store), \ - offset \ + offset, \ + 0 \ } \ })[0].attr.attr) =20 @@ -219,7 +221,8 @@ static __maybe_unused ssize_t coresight_cti_reg_store(s= truct device *dev, (&((struct cs_off_attribute[]) { \ { \ __ATTR(name, 0200, NULL, coresight_cti_reg_store), \ - offset \ + offset, \ + 0 \ } \ })[0].attr.attr) =20 @@ -257,7 +260,7 @@ static ssize_t cti_reg32_show(struct device *dev, char = *buf, =20 scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) { if (cti_is_active(config)) { - val =3D cti_read_single_reg(drvdata, reg_offset); + val =3D cti_read_single_reg(drvdata, reg_offset, 0); if (pcached_val) *pcached_val =3D val; } else if (pcached_val) { @@ -293,7 +296,7 @@ static ssize_t cti_reg32_store(struct device *dev, cons= t char *buf, =20 /* write through if offset and enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, reg_offset, val); + cti_write_single_reg(drvdata, reg_offset, 0, val); } =20 return size; @@ -386,7 +389,7 @@ static ssize_t inen_store(struct device *dev, =20 /* write through if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, CTIINEN(index), val); + cti_write_single_reg(drvdata, CTIINEN, index, val); =20 return size; } @@ -427,7 +430,7 @@ static ssize_t outen_store(struct device *dev, =20 /* write through if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, CTIOUTEN(index), val); + cti_write_single_reg(drvdata, CTIOUTEN, index, val); =20 return size; } @@ -469,7 +472,7 @@ static ssize_t appclear_store(struct device *dev, =20 /* write through if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, CTIAPPCLEAR, val); + cti_write_single_reg(drvdata, CTIAPPCLEAR, 0, val); =20 return size; } @@ -490,7 +493,7 @@ static ssize_t apppulse_store(struct device *dev, =20 /* write through if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, CTIAPPPULSE, val); + cti_write_single_reg(drvdata, CTIAPPPULSE, 0, val); =20 return size; } diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracin= g/coresight/coresight-cti.h index ef079fc18b72..98b8de8a3687 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -30,8 +30,8 @@ struct fwnode_handle; #define CTIAPPSET 0x014 #define CTIAPPCLEAR 0x018 #define CTIAPPPULSE 0x01C -#define CTIINEN(n) (0x020 + (4 * n)) -#define CTIOUTEN(n) (0x0A0 + (4 * n)) +#define CTIINEN 0x020 +#define CTIOUTEN 0x0A0 #define CTITRIGINSTATUS 0x130 #define CTITRIGOUTSTATUS 0x134 #define CTICHINSTATUS 0x138 @@ -217,8 +217,9 @@ int cti_enable(struct coresight_device *csdev, enum cs_= mode mode, int cti_disable(struct coresight_device *csdev, struct coresight_path *pat= h); void cti_write_all_hw_regs(struct cti_drvdata *drvdata); void cti_write_intack(struct device *dev, u32 ackval); -void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 val= ue); -u32 cti_read_single_reg(struct cti_drvdata *drvdata, int offset); +void cti_write_single_reg(struct cti_drvdata *drvdata, u32 off, u32 index, + u32 value); +u32 cti_read_single_reg(struct cti_drvdata *drvdata, u32 off, u32 index); int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, enum cti_trig_dir direction, u32 channel_idx, u32 trigger_idx); diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtraci= ng/coresight/coresight-priv.h index 770a8dc881b3..4aa25dda856c 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -68,6 +68,7 @@ struct cs_pair_attribute { struct cs_off_attribute { struct device_attribute attr; u32 off; + u32 index; }; =20 ssize_t coresight_simple_show32(struct device *_dev, struct device_attribu= te *attr, char *buf); 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bea917318esm10435555ad.5.2026.05.21.05.16.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 05:16:51 -0700 (PDT) From: Yingchao Deng Date: Thu, 21 May 2026 20:16:29 +0800 Subject: [PATCH v9 3/4] coresight: cti: add Qualcomm extended CTI identification and quirks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-extended_cti-v9-3-d21f4f92c51e@oss.qualcomm.com> References: <20260521-extended_cti-v9-0-d21f4f92c51e@oss.qualcomm.com> In-Reply-To: <20260521-extended_cti-v9-0-d21f4f92c51e@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, jinlong.mao@oss.qualcomm.com, quic_yingdeng@quicinc.com, tingwei.zhang@oss.qualcomm.com, jie.gan@oss.qualcomm.com, Yingchao Deng X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779365796; l=7584; i=yingchao.deng@oss.qualcomm.com; s=20260521; h=from:subject:message-id; bh=9c3KkSTH9SNVjrN4djhgLnzm9UPZeM+m23N8Q7Og1Fk=; b=/W594KJ7Xc/7Ks61Cx8t6vxrj4Nq9aero4Jl+y3o9rkDDSgmPvVccZDPgqKD1KKcJXlJmz17p KeXqG+OCY/JAUw4y0F80ueg2V2inSchEFctQAGJp6mj1Ky0cVHcmiJs X-Developer-Key: i=yingchao.deng@oss.qualcomm.com; a=ed25519; pk=YbHeeX0Qzqo7voZLva784lFhVChB9yF3a4sceW95ljA= X-Proofpoint-ORIG-GUID: UrOvmc1nrpeUXv2Pn8NyelUcAbjd3Lvg X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIxMDEyMyBTYWx0ZWRfXzy7DqHthiYOT QF5oDhEcAtbgYURL7GY7MHkUydyf8w58JSzbrZhosroHbZfmEZV9qmIYit+kvLeMyBswX/N1qqc dF4ZBvP9vVRhB49hMJjVn4a4y/gZRmm63FOdYqmuARKegXEh5PUglad6P9FQZkb6VEtJW3tAbSS cEwhJJ9N1EfaFMGz8e48ccY8OvScKFWkBSrJyj4OcdOuq8MH3GKRfPV9pNvIpO4l1+ZBMO6q7J8 vMr9IMlNEHndiZDXZ+p7R0PxGOl6qOGtNRAgpqlnZpvydKbsaSww4CEWrMX/ggor23TzHK9iCTD 2vAh5p+2bxroKAzWcYqalzFkmrsHyTpHb8P8iE0sjYWuwRBJkQ6hFUdkTVJF7MARBvDI3XoGbfq 3fJjQt0gdnBgI8+OhPqFcCiEgj6JWUVCpkp1Hax83wUZD9cPGqFCpRAuP2ZPD3lRMXWE8s9UXPl kB3huFgvi8qOcXNh08A== X-Authority-Analysis: v=2.4 cv=YfyNIQRf c=1 sm=1 tr=0 ts=6a0ef7b5 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=yjDJaKUznl4u3GwUnvUA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: UrOvmc1nrpeUXv2Pn8NyelUcAbjd3Lvg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-21_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 suspectscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605210123 Qualcomm implements an extended variant of the ARM CoreSight CTI with a different register layout and vendor-specific behavior. While the programming model remains largely compatible, the register offsets differ from the standard ARM CTI and require explicit handling. Detect Qualcomm CTIs via the DEVARCH register and record this in the CTI driver data. Introduce a small mapping layer to translate standard CTI register offsets to Qualcomm-specific offsets, allowing the rest of the driver to use a common register access path. Additionally, handle a Qualcomm-specific quirk where the CLAIMSET register is incorrectly initialized to a non-zero value, which can cause tools or drivers to assume the component is already claimed. Clear the register during probe to reflect the actual unclaimed state. No functional change is intended for standard ARM CTI devices. Co-developed-by: Jinlong Mao Signed-off-by: Jinlong Mao Signed-off-by: Yingchao Deng --- drivers/hwtracing/coresight/coresight-cti-core.c | 27 +++++++++- drivers/hwtracing/coresight/coresight-cti.h | 7 ++- drivers/hwtracing/coresight/qcom-cti.h | 65 ++++++++++++++++++++= ++++ 3 files changed, 97 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwt= racing/coresight/coresight-cti-core.c index c5cc2706e241..2dac5eb4ecca 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -21,6 +21,7 @@ =20 #include "coresight-priv.h" #include "coresight-cti.h" +#include "qcom-cti.h" =20 /* * CTI devices can be associated with a PE, or be connected to CoreSight @@ -45,6 +46,9 @@ static DEFINE_MUTEX(ect_mutex); static void __iomem *__reg_addr(struct cti_drvdata *drvdata, u32 off, u32 index) { + if (unlikely(rvdata->is_qcom_cti)) + off =3D cti_qcom_reg_off(off); + return drvdata->base + off + sizeof(u32) * index; } =20 @@ -172,6 +176,9 @@ void cti_write_intack(struct device *dev, u32 ackval) /* DEVID[19:16] - number of CTM channels */ #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19)) =20 +/* DEVARCH[31:21] - ARCHITECT */ +#define CTI_DEVARCH_ARCHITECT(devarch_val) ((int)BMVAL(devarch_val, 21, 31= )) + static int cti_set_default_config(struct device *dev, struct cti_drvdata *drvdata) { @@ -702,6 +709,7 @@ static int cti_probe(struct amba_device *adev, const st= ruct amba_id *id) struct coresight_desc cti_desc; struct coresight_platform_data *pdata =3D NULL; struct resource *res =3D &adev->res; + u32 devarch; =20 /* driver data*/ drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); @@ -726,6 +734,22 @@ static int cti_probe(struct amba_device *adev, const s= truct amba_id *id) =20 raw_spin_lock_init(&drvdata->spinlock); =20 + devarch =3D readl_relaxed(drvdata->base + CORESIGHT_DEVARCH); + if (CTI_DEVARCH_ARCHITECT(devarch) =3D=3D ARCHITECT_QCOM) { + drvdata->is_qcom_cti =3D true; + /* + * QCOM CTI does not implement Claimtag functionality as + * per CoreSight specification, but its CLAIMSET register + * is incorrectly initialized to 0xF. This can mislead + * tools or drivers into thinking the component is claimed. + * + * Reset CLAIMSET to 0 to reflect that no claims are active. + */ + CS_UNLOCK(drvdata->base); + writel_relaxed(0, drvdata->base + CORESIGHT_CLAIMSET); + CS_LOCK(drvdata->base); + } + /* initialise CTI driver config values */ ret =3D cti_set_default_config(dev, drvdata); if (ret) @@ -782,7 +806,8 @@ static int cti_probe(struct amba_device *adev, const st= ruct amba_id *id) =20 /* all done - dec pm refcount */ pm_runtime_put(&adev->dev); - dev_info(&drvdata->csdev->dev, "CTI initialized\n"); + dev_info(&drvdata->csdev->dev, + "%sCTI initialized\n", drvdata->is_qcom_cti ? "QCOM " : ""); return 0; } =20 diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracin= g/coresight/coresight-cti.h index 98b8de8a3687..08ea6daf5b3c 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -54,10 +54,11 @@ struct fwnode_handle; /* * CTI CSSoc 600 has a max of 32 trigger signals per direction. * CTI CSSoc 400 has 8 IO triggers - other CTIs can be impl def. + * QCOM CTI supports up to 128 trigger signals per direction. * Max of in and out defined in the DEVID register. * - pick up actual number used from .dts parameters if present. */ -#define CTIINOUTEN_MAX 32 +#define CTIINOUTEN_MAX 128 =20 /** * Group of related trigger signals @@ -168,6 +169,9 @@ struct cti_config { * @spinlock: Control data access to one at a time. * @config: Configuration data for this CTI device. * @node: List entry of this device in the list of CTI devices. + * @is_qcom_cti: True if this CTI is a Qualcomm vendor-specific + * variant that requires register offset translation + * via cti_qcom_reg_off(). */ struct cti_drvdata { void __iomem *base; @@ -176,6 +180,7 @@ struct cti_drvdata { raw_spinlock_t spinlock; struct cti_config config; struct list_head node; + bool is_qcom_cti; }; =20 /* diff --git a/drivers/hwtracing/coresight/qcom-cti.h b/drivers/hwtracing/cor= esight/qcom-cti.h new file mode 100644 index 000000000000..d3846613a0de --- /dev/null +++ b/drivers/hwtracing/coresight/qcom-cti.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _CORESIGHT_QCOM_CTI_H +#define _CORESIGHT_QCOM_CTI_H + +#include "coresight-cti.h" + +#define ARCHITECT_QCOM 0x477 + +/* CTI programming registers */ +#define QCOM_CTIINTACK 0x020 +#define QCOM_CTIAPPSET 0x004 +#define QCOM_CTIAPPCLEAR 0x008 +#define QCOM_CTIAPPPULSE 0x00C +#define QCOM_CTIINEN 0x400 +#define QCOM_CTIOUTEN 0x800 +#define QCOM_CTITRIGINSTATUS 0x040 +#define QCOM_CTITRIGOUTSTATUS 0x060 +#define QCOM_CTICHINSTATUS 0x080 +#define QCOM_CTICHOUTSTATUS 0x084 +#define QCOM_CTIGATE 0x088 +#define QCOM_ASICCTL 0x08C +/* Integration test registers */ +#define QCOM_ITCHINACK 0xE70 +#define QCOM_ITTRIGINACK 0xE80 +#define QCOM_ITCHOUT 0xE74 +#define QCOM_ITTRIGOUT 0xEA0 +#define QCOM_ITCHOUTACK 0xE78 +#define QCOM_ITTRIGOUTACK 0xEC0 +#define QCOM_ITCHIN 0xE7C +#define QCOM_ITTRIGIN 0xEE0 + +static inline u32 cti_qcom_reg_off(u32 offset) +{ + switch (offset) { + case CTIINTACK: return QCOM_CTIINTACK; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bea917318esm10435555ad.5.2026.05.21.05.16.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 05:16:54 -0700 (PDT) From: Yingchao Deng Date: Thu, 21 May 2026 20:16:30 +0800 Subject: [PATCH v9 4/4] coresight: cti: expose banked sysfs registers for Qualcomm extended CTI Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-extended_cti-v9-4-d21f4f92c51e@oss.qualcomm.com> References: <20260521-extended_cti-v9-0-d21f4f92c51e@oss.qualcomm.com> In-Reply-To: <20260521-extended_cti-v9-0-d21f4f92c51e@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, jinlong.mao@oss.qualcomm.com, quic_yingdeng@quicinc.com, tingwei.zhang@oss.qualcomm.com, jie.gan@oss.qualcomm.com, Yingchao Deng X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779365796; l=5578; i=yingchao.deng@oss.qualcomm.com; s=20260521; h=from:subject:message-id; bh=FM2YtHpM4OM2HUWr2MmK4EhxL38NMpDBKrZYgHLhkWw=; b=Ds114TPyMEar/y2iZD9LJeZrXlieJ7ZuzRXSPr95QRLqTkOMZ8bTcznAP6UxlyPYeoEw/Q4j9 PpmiG0bii0BDjzLh/r6KKKYrUT7RdWxuz6oDifB+u0XaZyDhkyR1SmU X-Developer-Key: i=yingchao.deng@oss.qualcomm.com; a=ed25519; pk=YbHeeX0Qzqo7voZLva784lFhVChB9yF3a4sceW95ljA= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIxMDEyMyBTYWx0ZWRfX1X3C/h4pEozr rMdv+eddRsMNfpi4ZU/1IXAZSwpp22qZrxAQ034B5eQZiNEyEan+uzfdWxgO3Nvc0RYi4SMYIlu Z3R314XZ4Am4ajGmzUnZhTu7+JqxA8V3eoZMSUWnmq6KFOvZGuvE6Sb96XsPVKiGD7ZSdhcuvVx hQ1D+Wv4rKQsZNPY/L/Jl2Ru9khlgwSo/fo1gflIXe2jPye+fvLqK36gMrxF0edBPdbGMz+ZmZ+ c6Hmwc2Qo/D/az4/vJ4ERsAJAwivEeT1VjyR2DTh6Qfc+6uNEnsDeHSaR8Gh2pyBHGYqD2mc5Tc W6Zmx2+u0g8rL24Yiw48dYS47ApnmTbT7DsOxymlTVWNQMAW8gzcx232DsFYmrHyjnfe8Fq7ehq El+iIWHTYUqbSwwr/Usq0YKIU80qUBOnSvkI3NgV8CBANWPKdWkVP/VpK3i88jA2Wa69Mh9YnAo RJz6dBxCgZxttu0zFyg== X-Authority-Analysis: v=2.4 cv=GYAnWwXL c=1 sm=1 tr=0 ts=6a0ef7b8 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=yoa6GI8vE20v00mW0vsA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: 9cfxFNHAlRoPO43Sjo90tRrQ8bAR1qCo X-Proofpoint-ORIG-GUID: 9cfxFNHAlRoPO43Sjo90tRrQ8bAR1qCo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-21_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 spamscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 phishscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605210123 Qualcomm extended CTI implements banked trigger status and integration registers, where each bank covers 32 triggers. Multiple instances of these registers are required to expose the full trigger space. Add coresight_cti_reg_index(), coresight_cti_reg_rw_index(), and coresight_cti_reg_wo_index() macros that carry the bank index in the cs_off_attribute.index field, keeping the base offset and index separate rather than encoding them together. Add static sysfs entries for the banked CTI registers and control their visibility based on the underlying hardware configuration. Visibility is determined by comparing the attribute's index against the number of banks implied by nr_trig_max (32 triggers per bank). Registers beyond the hardware capacity are hidden, preserving the existing ABI on standard ARM CTIs while exposing the full register set on Qualcomm CTIs. Signed-off-by: Yingchao Deng --- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 58 +++++++++++++++++++= ++++ 1 file changed, 58 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hw= tracing/coresight/coresight-cti-sysfs.c index 7191a478b2da..feecc9d6563f 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -207,6 +207,15 @@ static __maybe_unused ssize_t coresight_cti_reg_store(= struct device *dev, } \ })[0].attr.attr) =20 +#define coresight_cti_reg_index(name, offset, idx) \ + (&((struct cs_off_attribute[]) { \ + { \ + __ATTR(name, 0444, coresight_cti_reg_show, NULL), \ + offset, \ + idx \ + } \ + })[0].attr.attr) + #define coresight_cti_reg_rw(name, offset) \ (&((struct cs_off_attribute[]) { \ { \ @@ -217,6 +226,16 @@ static __maybe_unused ssize_t coresight_cti_reg_store(= struct device *dev, } \ })[0].attr.attr) =20 +#define coresight_cti_reg_rw_index(name, offset, idx) \ + (&((struct cs_off_attribute[]) { \ + { \ + __ATTR(name, 0644, coresight_cti_reg_show, \ + coresight_cti_reg_store), \ + offset, \ + idx \ + } \ + })[0].attr.attr) + #define coresight_cti_reg_wo(name, offset) \ (&((struct cs_off_attribute[]) { \ { \ @@ -226,6 +245,15 @@ static __maybe_unused ssize_t coresight_cti_reg_store(= struct device *dev, } \ })[0].attr.attr) =20 +#define coresight_cti_reg_wo_index(name, offset, idx) \ + (&((struct cs_off_attribute[]) { \ + { \ + __ATTR(name, 0200, NULL, coresight_cti_reg_store), \ + offset, \ + idx \ + } \ + })[0].attr.attr) + /* coresight management registers */ static struct attribute *coresight_cti_mgmt_attrs[] =3D { coresight_cti_reg(devaff0, CTIDEVAFF0), @@ -515,18 +543,36 @@ static struct attribute *coresight_cti_regs_attrs[] = =3D { &dev_attr_appclear.attr, &dev_attr_apppulse.attr, coresight_cti_reg(triginstatus, CTITRIGINSTATUS), + coresight_cti_reg_index(triginstatus1, CTITRIGINSTATUS, 1), + coresight_cti_reg_index(triginstatus2, CTITRIGINSTATUS, 2), + coresight_cti_reg_index(triginstatus3, CTITRIGINSTATUS, 3), coresight_cti_reg(trigoutstatus, CTITRIGOUTSTATUS), + coresight_cti_reg_index(trigoutstatus1, CTITRIGOUTSTATUS, 1), + coresight_cti_reg_index(trigoutstatus2, CTITRIGOUTSTATUS, 2), + coresight_cti_reg_index(trigoutstatus3, CTITRIGOUTSTATUS, 3), coresight_cti_reg(chinstatus, CTICHINSTATUS), coresight_cti_reg(choutstatus, CTICHOUTSTATUS), #ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS coresight_cti_reg_rw(itctrl, CORESIGHT_ITCTRL), coresight_cti_reg(ittrigin, ITTRIGIN), + coresight_cti_reg_index(ittrigin1, ITTRIGIN, 1), + coresight_cti_reg_index(ittrigin2, ITTRIGIN, 2), + coresight_cti_reg_index(ittrigin3, ITTRIGIN, 3), coresight_cti_reg(itchin, ITCHIN), coresight_cti_reg_rw(ittrigout, ITTRIGOUT), + coresight_cti_reg_rw_index(ittrigout1, ITTRIGOUT, 1), + coresight_cti_reg_rw_index(ittrigout2, ITTRIGOUT, 2), + coresight_cti_reg_rw_index(ittrigout3, ITTRIGOUT, 3), coresight_cti_reg_rw(itchout, ITCHOUT), coresight_cti_reg(itchoutack, ITCHOUTACK), coresight_cti_reg(ittrigoutack, ITTRIGOUTACK), + coresight_cti_reg_index(ittrigoutack1, ITTRIGOUTACK, 1), + coresight_cti_reg_index(ittrigoutack2, ITTRIGOUTACK, 2), + coresight_cti_reg_index(ittrigoutack3, ITTRIGOUTACK, 3), coresight_cti_reg_wo(ittriginack, ITTRIGINACK), + coresight_cti_reg_wo_index(ittriginack1, ITTRIGINACK, 1), + coresight_cti_reg_wo_index(ittriginack2, ITTRIGINACK, 2), + coresight_cti_reg_wo_index(ittriginack3, ITTRIGINACK, 3), coresight_cti_reg_wo(itchinack, ITCHINACK), #endif NULL, @@ -537,10 +583,22 @@ static umode_t coresight_cti_regs_is_visible(struct k= object *kobj, { struct device *dev =3D kobj_to_dev(kobj); struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + struct device_attribute *dev_attr; + struct cs_off_attribute *cti_attr; + int max_bank; =20 if (attr =3D=3D &dev_attr_asicctl.attr && !drvdata->config.asicctl_impl) return 0; =20 + dev_attr =3D container_of(attr, struct device_attribute, attr); + if (dev_attr->show =3D=3D coresight_cti_reg_show || + dev_attr->store =3D=3D coresight_cti_reg_store) { + cti_attr =3D container_of(dev_attr, struct cs_off_attribute, attr); + max_bank =3D DIV_ROUND_UP(drvdata->config.nr_trig_max, 32); + if (cti_attr->index >=3D max_bank) + return 0; + } + return attr->mode; } =20 --=20 2.43.0