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charset="utf-8" pm_runtime_put() may trigger the idle check after pm_runtime_disable() is run as part of devm_pm_runtime_enable()'s cleanup action, leaving runtime PM active. Use pm_runtime_put_sync() to ensure the idle check runs synchronously. Fixes: 13e7b3305b64 ("irqchip: Add RZ/{T2H,N2H} Interrupt Controller (ICU) = driver") Signed-off-by: Cosmin Tanislav --- drivers/irqchip/irq-renesas-rzt2h.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-renesas-rzt2h.c b/drivers/irqchip/irq-rene= sas-rzt2h.c index 53cf80e1155a..ecb69da55508 100644 --- a/drivers/irqchip/irq-renesas-rzt2h.c +++ b/drivers/irqchip/irq-renesas-rzt2h.c @@ -265,7 +265,7 @@ static int rzt2h_icu_init(struct platform_device *pdev,= struct device_node *pare irq_domain =3D irq_domain_create_hierarchy(parent_domain, 0, RZT2H_ICU_NU= M_IRQ, dev_fwnode(dev), &rzt2h_icu_domain_ops, priv); if (!irq_domain) { - pm_runtime_put(dev); + pm_runtime_put_sync(dev); return -ENOMEM; } =20 --=20 2.54.0 From nobody Sun May 24 22:43:28 2026 Received: from OS0P286CU010.outbound.protection.outlook.com (mail-japanwestazon11011044.outbound.protection.outlook.com [40.107.74.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A9AD370D75 for ; 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Thu, 21 May 2026 05:32:07 +0900 (JST) From: Cosmin Tanislav To: Thomas Gleixner Cc: Cosmin Tanislav , linux-kernel@vger.kernel.org Subject: [PATCH 2/3] irqchip/renesas-rzt2h: add software-triggered interrupts support Date: Wed, 20 May 2026 23:31:16 +0300 Message-ID: <20260520203117.1516442-3-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260520203117.1516442-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20260520203117.1516442-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYO1EPF00005026:EE_|OS7PR01MB11441:EE_ X-MS-Office365-Filtering-Correlation-Id: 48d73003-44ce-4939-b989-08deb6aedd39 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|82310400026|1800799024|18002099003|22082099003|56012099003|11063799006|6133799003; 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charset="utf-8" The Renesas RZ/T2H ICU supports software-triggerable interrupts. Add a dedicated rzt2h_icu_intcpu_chip irq_chip which implements rzt2h_icu_intcpu_set_irqchip_state() to allow injecting these interrupts. Request the INTCPU IRQs when IRQ injection is enabled to report them when they occur. Signed-off-by: Cosmin Tanislav --- drivers/irqchip/irq-renesas-rzt2h.c | 133 +++++++++++++++++++++++++++- 1 file changed, 130 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzt2h.c b/drivers/irqchip/irq-rene= sas-rzt2h.c index ecb69da55508..3fd0381efa32 100644 --- a/drivers/irqchip/irq-renesas-rzt2h.c +++ b/drivers/irqchip/irq-renesas-rzt2h.c @@ -2,6 +2,7 @@ =20 #include #include +#include #include #include #include @@ -40,6 +41,9 @@ ((n) >=3D RZT2H_ICU_##type##_START && \ (n) < RZT2H_ICU_##type##_START + RZT2H_ICU_##type##_COUNT) =20 +#define RZT2H_ICU_SWINT 0x0 +#define RZT2H_ICU_SWINT_IC_MASK(i) BIT(i) + #define RZT2H_ICU_PORTNF_MD 0xc #define RZT2H_ICU_PORTNF_MDi_MASK(i) (GENMASK(1, 0) << ((i) * 2)) #define RZT2H_ICU_PORTNF_MDi_PREP(i, val) (FIELD_PREP(GENMASK(1, 0), val) = << ((i) * 2)) @@ -99,6 +103,12 @@ static inline int rzt2h_icu_irq_to_offset(struct irq_da= ta *d, void __iomem **bas } else if (RZT2H_ICU_IRQ_IN_RANGE(hwirq, IRQ_S) || RZT2H_ICU_IRQ_IN_RANGE= (hwirq, SEI)) { *offset =3D hwirq - RZT2H_ICU_IRQ_S_START; *base =3D priv->base_s; + } else if (RZT2H_ICU_IRQ_IN_RANGE(hwirq, INTCPU_NS)) { + *offset =3D hwirq - RZT2H_ICU_INTCPU_NS_START; + *base =3D priv->base_ns; + } else if (RZT2H_ICU_IRQ_IN_RANGE(hwirq, INTCPU_S)) { + *offset =3D hwirq - RZT2H_ICU_INTCPU_S_START; + *base =3D priv->base_s; } else { return -EINVAL; } @@ -164,6 +174,28 @@ static int rzt2h_icu_set_type(struct irq_data *d, unsi= gned int type) return irq_chip_set_type_parent(d, IRQ_TYPE_EDGE_RISING); } =20 +static int rzt2h_icu_intcpu_set_irqchip_state(struct irq_data *d, enum irq= chip_irq_state which, + bool state) +{ + unsigned int offset; + void __iomem *base; + int ret; + + if (which !=3D IRQCHIP_STATE_PENDING) + return irq_chip_set_parent_state(d, which, state); + + if (!state) + return 0; + + ret =3D rzt2h_icu_irq_to_offset(d, &base, &offset); + if (ret) + return ret; + + writel_relaxed(RZT2H_ICU_SWINT_IC_MASK(offset), base + RZT2H_ICU_SWINT); + + return 0; +} + static const struct irq_chip rzt2h_icu_chip =3D { .name =3D "rzt2h-icu", .irq_mask =3D irq_chip_mask_parent, @@ -180,10 +212,27 @@ static const struct irq_chip rzt2h_icu_chip =3D { IRQCHIP_SKIP_SET_WAKE, }; =20 +static const struct irq_chip rzt2h_icu_intcpu_chip =3D { + .name =3D "rzt2h-icu", + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_eoi =3D irq_chip_eoi_parent, + .irq_set_type =3D irq_chip_set_type_parent, + .irq_set_wake =3D irq_chip_set_wake_parent, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D rzt2h_icu_intcpu_set_irqchip_state, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + static int rzt2h_icu_alloc(struct irq_domain *domain, unsigned int virq, u= nsigned int nr_irqs, void *arg) { struct rzt2h_icu_priv *priv =3D domain->host_data; + const struct irq_chip *chip; irq_hw_number_t hwirq; unsigned int type; int ret; @@ -192,7 +241,13 @@ static int rzt2h_icu_alloc(struct irq_domain *domain, = unsigned int virq, unsigne if (ret) return ret; =20 - ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &rzt2h_icu_chi= p, NULL); + if (RZT2H_ICU_IRQ_IN_RANGE(hwirq, INTCPU_NS) || + RZT2H_ICU_IRQ_IN_RANGE(hwirq, INTCPU_S)) + chip =3D &rzt2h_icu_intcpu_chip; + else + chip =3D &rzt2h_icu_chip; + + ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip, NULL); if (ret) return ret; =20 @@ -222,6 +277,68 @@ static int rzt2h_icu_parse_interrupts(struct rzt2h_icu= _priv *priv, struct device return 0; } =20 +static irqreturn_t rzt2h_icu_intcpu_irq(int irq, void *data) +{ + unsigned int intcpu =3D (uintptr_t)data; + + pr_info("INTCPU%u software interrupt\n", intcpu); + + return IRQ_HANDLED; +} + +static int rzt2h_icu_request_irqs(struct platform_device *pdev, struct irq= _domain *irq_domain, + unsigned int start, unsigned int count, irq_handler_t handler, + void *data) +{ + struct device *dev =3D &pdev->dev; + unsigned int offset, virq; + struct irq_fwspec fwspec; + int ret; + + for (offset =3D start; offset < start + count; offset++) { + fwspec.fwnode =3D irq_domain->fwnode; + fwspec.param_count =3D 2; + fwspec.param[0] =3D offset; + fwspec.param[1] =3D IRQ_TYPE_EDGE_RISING; + + virq =3D irq_create_fwspec_mapping(&fwspec); + if (!virq) { + return dev_err_probe(dev, -EINVAL, + "Failed to create IRQ %u mapping\n", offset); + } + + ret =3D devm_request_irq(dev, virq, handler, 0, dev_name(dev), + data ?: (void *)(uintptr_t)offset); + if (ret) + return dev_err_probe(dev, ret, "Failed to request IRQ %u\n", offset); + } + + return 0; +} + +static int rzt2h_icu_setup_irqs(struct platform_device *pdev, struct irq_d= omain *irq_domain) +{ + int ret; + + if (IS_ENABLED(CONFIG_GENERIC_IRQ_INJECTION)) { + ret =3D rzt2h_icu_request_irqs(pdev, irq_domain, + RZT2H_ICU_INTCPU_NS_START, + RZT2H_ICU_INTCPU_NS_COUNT, + rzt2h_icu_intcpu_irq, NULL); + if (ret) + return ret; + + ret =3D rzt2h_icu_request_irqs(pdev, irq_domain, + RZT2H_ICU_INTCPU_S_START, + RZT2H_ICU_INTCPU_S_COUNT, + rzt2h_icu_intcpu_irq, NULL); + if (ret) + return ret; + } + + return 0; +} + static int rzt2h_icu_init(struct platform_device *pdev, struct device_node= *parent) { struct irq_domain *irq_domain, *parent_domain; @@ -265,11 +382,21 @@ static int rzt2h_icu_init(struct platform_device *pde= v, struct device_node *pare irq_domain =3D irq_domain_create_hierarchy(parent_domain, 0, RZT2H_ICU_NU= M_IRQ, dev_fwnode(dev), &rzt2h_icu_domain_ops, priv); if (!irq_domain) { - pm_runtime_put_sync(dev); - return -ENOMEM; + ret =3D -ENOMEM; + goto err_pm_put; } =20 + ret =3D rzt2h_icu_setup_irqs(pdev, irq_domain); + if (ret) + goto err_irq_domain_free; + return 0; + +err_irq_domain_free: + irq_domain_remove(irq_domain); +err_pm_put: + pm_runtime_put_sync(dev); + return ret; } =20 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzt2h_icu) --=20 2.54.0 From nobody Sun May 24 22:43:28 2026 Received: from TY3P286CU002.outbound.protection.outlook.com (mail-japaneastazon11010038.outbound.protection.outlook.com [52.101.229.38]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7956E37267E for ; Wed, 20 May 2026 20:32:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 21 May 2026 05:32:09 +0900 (JST) From: Cosmin Tanislav To: Thomas Gleixner Cc: Cosmin Tanislav , linux-kernel@vger.kernel.org Subject: [PATCH 3/3] irqchip/renesas-rzt2h: add error interrupts support Date: Wed, 20 May 2026 23:31:17 +0300 Message-ID: <20260520203117.1516442-4-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260520203117.1516442-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20260520203117.1516442-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OS1PEPF0000D216:EE_|TY4PR01MB12606:EE_ X-MS-Office365-Filtering-Correlation-Id: a015f496-ba03-4568-20ba-08deb6aede8f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|82310400026|376014|18002099003|11063799006|56012099003|22082099003; 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charset="utf-8" The Renesas RZ/T2H ICU is able to report errors for CA55, GIC, and various IPs. Unmask these errors, request the IRQs and report them when they occur. Signed-off-by: Cosmin Tanislav --- drivers/irqchip/irq-renesas-rzt2h.c | 146 +++++++++++++++++++++++++++- 1 file changed, 145 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-renesas-rzt2h.c b/drivers/irqchip/irq-rene= sas-rzt2h.c index 3fd0381efa32..b04ea7a00b2c 100644 --- a/drivers/irqchip/irq-renesas-rzt2h.c +++ b/drivers/irqchip/irq-renesas-rzt2h.c @@ -31,11 +31,36 @@ RZT2H_ICU_IRQ_S_COUNT) #define RZT2H_ICU_SEI_COUNT 1 =20 +#define RZT2H_ICU_CA55_ERR_START (RZT2H_ICU_SEI_START + \ + RZT2H_ICU_SEI_COUNT) +#define RZT2H_ICU_CA55_ERR_COUNT 2 + +#define RZT2H_ICU_CR52_ERR_START (RZT2H_ICU_CA55_ERR_START + \ + RZT2H_ICU_CA55_ERR_COUNT) +#define RZT2H_ICU_CR52_ERR_COUNT 4 + +#define RZT2H_ICU_PERI_ERR_START (RZT2H_ICU_CR52_ERR_START + \ + RZT2H_ICU_CR52_ERR_COUNT) +#define RZT2H_ICU_PERI_ERR_COUNT 2 + +#define RZT2H_ICU_DSMIF_ERR_START (RZT2H_ICU_PERI_ERR_START + \ + RZT2H_ICU_PERI_ERR_COUNT) +#define RZT2H_ICU_DSMIF_ERR_COUNT 2 + +#define RZT2H_ICU_ENCIF_ERR_START (RZT2H_ICU_DSMIF_ERR_START + \ + RZT2H_ICU_DSMIF_ERR_COUNT) +#define RZT2H_ICU_ENCIF_ERR_COUNT 2 + #define RZT2H_ICU_NUM_IRQ (RZT2H_ICU_INTCPU_NS_COUNT + \ RZT2H_ICU_INTCPU_S_COUNT + \ RZT2H_ICU_IRQ_NS_COUNT + \ RZT2H_ICU_IRQ_S_COUNT + \ - RZT2H_ICU_SEI_COUNT) + RZT2H_ICU_SEI_COUNT + \ + RZT2H_ICU_CA55_ERR_COUNT + \ + RZT2H_ICU_CR52_ERR_COUNT + \ + RZT2H_ICU_PERI_ERR_COUNT + \ + RZT2H_ICU_DSMIF_ERR_COUNT + \ + RZT2H_ICU_ENCIF_ERR_COUNT) =20 #define RZT2H_ICU_IRQ_IN_RANGE(n, type) \ ((n) >=3D RZT2H_ICU_##type##_START && \ @@ -53,6 +78,29 @@ #define RZT2H_ICU_MD_RISING_EDGE 0b10 #define RZT2H_ICU_MD_BOTH_EDGES 0b11 =20 +#define RZT2H_ICU_CA55ERR_E0MSK 0x50 +#define RZT2H_ICU_CA55ERR_CLR 0x60 +#define RZT2H_ICU_CA55ERR_STAT 0x64 +#define RZT2H_ICU_CA55ERR_MASK GENMASK(12, 0) + +#define RZT2H_ICU_PERIERR_E0MSKn(n) (0x98 + 0x4 * (n)) +#define RZT2H_ICU_PERIERR_CLRn(n) (0xc8 + 0x4 * (n)) +#define RZT2H_ICU_PERIERR_STAT 0xd4 +#define RZT2H_ICU_PERIERR_NUM 3 +#define RZT2H_ICU_PERIERR_MASK GENMASK(31, 0) + +#define RZT2H_ICU_DSMIFERR_E0MSKn(n) (0xe0 + 0x4 * (n)) +#define RZT2H_ICU_DSMIFERR_CLRn(n) (0x1a0 + 0x4 * (n)) +#define RZT2H_ICU_DSMIFERR_STAT 0x1d0 +#define RZT2H_ICU_DSMIFERR_NUM 12 +#define RZT2H_ICU_DSMIFERR_MASK GENMASK(31, 0) + +#define RZT2H_ICU_ENCIFERR_E0MSKn(n) (0x200 + 0x4 * (n)) +#define RZT2H_ICU_ENCIFERR_CLRn(n) (0x250 + 0x4 * (n)) +#define RZT2H_ICU_ENCIFERR_STAT 0x264 +#define RZT2H_ICU_ENCIFERR_NUM 5 +#define RZT2H_ICU_ENCIFERR_MASK GENMASK(31, 0) + #define RZT2H_ICU_DMACn_RSSELi(n, i) (0x7d0 + 0x18 * (n) + 0x4 * (i)) #define RZT2H_ICU_DMAC_REQ_SELx_MASK(x) (GENMASK(9, 0) << ((x) * 10)) #define RZT2H_ICU_DMAC_REQ_SELx_PREP(x, val) (FIELD_PREP(GENMASK(9, 0), va= l) << ((x) * 10)) @@ -286,6 +334,52 @@ static irqreturn_t rzt2h_icu_intcpu_irq(int irq, void = *data) return IRQ_HANDLED; } =20 +static irqreturn_t rzt2h_icu_err_irq(struct rzt2h_icu_priv *priv, const ch= ar *name, + unsigned int num, u32 stat_base, u32 clr_base) +{ + bool handled =3D false; + + for (unsigned int n =3D 0; n < num; n++) { + u32 stat =3D readl(priv->base_ns + stat_base + n * 0x4); + + if (!stat) + continue; + + handled =3D true; + + pr_err("rzt2h-icu: %s error n=3D%u status=3D0x%08x\n", + name, n, stat); + + writel_relaxed(stat, priv->base_ns + clr_base + n * 0x4); + } + + return handled ? IRQ_HANDLED : IRQ_NONE; +} + +static irqreturn_t rzt2h_icu_ca55_err_irq(int irq, void *data) +{ + return rzt2h_icu_err_irq(data, "CA55", 1, + RZT2H_ICU_CA55ERR_STAT, RZT2H_ICU_CA55ERR_CLR); +} + +static irqreturn_t rzt2h_icu_peri_err_irq(int irq, void *data) +{ + return rzt2h_icu_err_irq(data, "peripheral", RZT2H_ICU_PERIERR_NUM, + RZT2H_ICU_PERIERR_STAT, RZT2H_ICU_PERIERR_CLRn(0)); +} + +static irqreturn_t rzt2h_icu_dsmif_err_irq(int irq, void *data) +{ + return rzt2h_icu_err_irq(data, "DSMIF", RZT2H_ICU_DSMIFERR_NUM, + RZT2H_ICU_DSMIFERR_STAT, RZT2H_ICU_DSMIFERR_CLRn(0)); +} + +static irqreturn_t rzt2h_icu_encif_err_irq(int irq, void *data) +{ + return rzt2h_icu_err_irq(data, "ENCIF", RZT2H_ICU_ENCIFERR_NUM, + RZT2H_ICU_ENCIFERR_STAT, RZT2H_ICU_ENCIFERR_CLRn(0)); +} + static int rzt2h_icu_request_irqs(struct platform_device *pdev, struct irq= _domain *irq_domain, unsigned int start, unsigned int count, irq_handler_t handler, void *data) @@ -318,6 +412,8 @@ static int rzt2h_icu_request_irqs(struct platform_devic= e *pdev, struct irq_domai =20 static int rzt2h_icu_setup_irqs(struct platform_device *pdev, struct irq_d= omain *irq_domain) { + struct rzt2h_icu_priv *priv =3D platform_get_drvdata(pdev); + unsigned int n; int ret; =20 if (IS_ENABLED(CONFIG_GENERIC_IRQ_INJECTION)) { @@ -336,6 +432,54 @@ static int rzt2h_icu_setup_irqs(struct platform_device= *pdev, struct irq_domain return ret; } =20 + /* + * There are two error interrupts and two error masks that can be used + * separately for each error type. It would not be very useful to + * receive two interrupts for the same error, so use only the first one. + */ + + ret =3D rzt2h_icu_request_irqs(pdev, irq_domain, RZT2H_ICU_CA55_ERR_START= , 1, + rzt2h_icu_ca55_err_irq, priv); + if (ret) + return ret; + + ret =3D rzt2h_icu_request_irqs(pdev, irq_domain, RZT2H_ICU_PERI_ERR_START= , 1, + rzt2h_icu_peri_err_irq, priv); + if (ret) + return ret; + + ret =3D rzt2h_icu_request_irqs(pdev, irq_domain, RZT2H_ICU_DSMIF_ERR_STAR= T, 1, + rzt2h_icu_dsmif_err_irq, priv); + if (ret) + return ret; + + ret =3D rzt2h_icu_request_irqs(pdev, irq_domain, RZT2H_ICU_ENCIF_ERR_STAR= T, 1, + rzt2h_icu_encif_err_irq, priv); + if (ret) + return ret; + + /* Clear and unmask CA55 error events */ + writel_relaxed(RZT2H_ICU_CA55ERR_MASK, priv->base_ns + RZT2H_ICU_CA55ERR_= CLR); + writel_relaxed(0, priv->base_ns + RZT2H_ICU_CA55ERR_E0MSK); + + /* Clear and unmask peripheral error events */ + for (n =3D 0; n < RZT2H_ICU_PERIERR_NUM; n++) { + writel_relaxed(RZT2H_ICU_PERIERR_MASK, priv->base_ns + RZT2H_ICU_PERIERR= _CLRn(n)); + writel_relaxed(0, priv->base_ns + RZT2H_ICU_PERIERR_E0MSKn(n)); + } + + /* Clear and unmask DSMIF error events */ + for (n =3D 0; n < RZT2H_ICU_DSMIFERR_NUM; n++) { + writel_relaxed(RZT2H_ICU_DSMIFERR_MASK, priv->base_ns + RZT2H_ICU_DSMIFE= RR_CLRn(n)); + writel_relaxed(0, priv->base_ns + RZT2H_ICU_DSMIFERR_E0MSKn(n)); + } + + /* Clear and unmask ENCIF error events */ + for (n =3D 0; n < RZT2H_ICU_ENCIFERR_NUM; n++) { + writel_relaxed(RZT2H_ICU_ENCIFERR_MASK, priv->base_ns + RZT2H_ICU_ENCIFE= RR_CLRn(n)); + writel_relaxed(0, priv->base_ns + RZT2H_ICU_ENCIFERR_E0MSKn(n)); + } + return 0; } =20 --=20 2.54.0