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[79.22.5.99]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-48fed253f93sm132123215e9.16.2026.05.20.08.55.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2026 08:55:48 -0700 (PDT) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Christian Marangi , Lorenzo Bianconi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v5 1/7] thermal/drivers: airoha: fix copy paste error on clamp_t low temp Date: Wed, 20 May 2026 17:55:14 +0200 Message-ID: <20260520155525.22239-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520155525.22239-1-ansuelsmth@gmail.com> References: <20260520155525.22239-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In airoha_thermal_set_trips, there is a copy paste error on clamping the value for the low trip temp point. Fix it to the correct value and actually clamp for the low variable. Fixes: 42de37f40e1b ("thermal/drivers: Add support for Airoha EN7581 therma= l sensor") Signed-off-by: Christian Marangi --- drivers/thermal/airoha_thermal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thermal/airoha_thermal.c b/drivers/thermal/airoha_ther= mal.c index b9fd6bfc88e5..439aa011b75c 100644 --- a/drivers/thermal/airoha_thermal.c +++ b/drivers/thermal/airoha_thermal.c @@ -273,7 +273,7 @@ static int airoha_thermal_set_trips(struct thermal_zone= _device *tz, int low, =20 if (low !=3D -INT_MAX) { /* Validate low and clamp it to a supported value */ - low =3D clamp_t(int, high, RAW_TO_TEMP(priv, 0), + low =3D clamp_t(int, low, RAW_TO_TEMP(priv, 0), RAW_TO_TEMP(priv, FIELD_MAX(EN7581_DOUT_TADC_MASK))); =20 /* We offset the low temp of 1=C2=B0C to trigger correct event */ --=20 2.53.0 From nobody Sun May 24 22:35:48 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBAEC340413 for ; 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[79.22.5.99]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-48fed253f93sm132123215e9.16.2026.05.20.08.55.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2026 08:55:50 -0700 (PDT) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Christian Marangi , Lorenzo Bianconi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v5 2/7] thermal/drivers: airoha: fix copy paste error for sen internal Date: Wed, 20 May 2026 17:55:15 +0200 Message-ID: <20260520155525.22239-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520155525.22239-1-ansuelsmth@gmail.com> References: <20260520155525.22239-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In airoha_thermal_setup_monitor there is a copy paste error on configuring the internval for temp monitor. Fix the error and use the correct mask for the sen interval for the EN7581_TEMPMONCTL2 register. Fixes: 42de37f40e1b ("thermal/drivers: Add support for Airoha EN7581 therma= l sensor") Signed-off-by: Christian Marangi --- drivers/thermal/airoha_thermal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thermal/airoha_thermal.c b/drivers/thermal/airoha_ther= mal.c index 439aa011b75c..829a7327fc40 100644 --- a/drivers/thermal/airoha_thermal.c +++ b/drivers/thermal/airoha_thermal.c @@ -403,7 +403,7 @@ static void airoha_thermal_setup_monitor(struct airoha_= thermal_priv *priv) * sen interval is 379 * 52.715us =3D 19.97ms */ writel(FIELD_PREP(EN7581_FILT_INTERVAL, 1) | - FIELD_PREP(EN7581_FILT_INTERVAL, 379), + FIELD_PREP(EN7581_SEN_INTERVAL, 379), priv->base + EN7581_TEMPMONCTL2); =20 /* AHB poll is set to 146 * 68.64 =3D 10.02us */ --=20 2.53.0 From nobody Sun May 24 22:35:48 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12745345CBE for ; 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[79.22.5.99]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-48fed253f93sm132123215e9.16.2026.05.20.08.55.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2026 08:55:51 -0700 (PDT) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Christian Marangi , Lorenzo Bianconi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v5 3/7] thermal/drivers: airoha: Convert to regmap API Date: Wed, 20 May 2026 17:55:16 +0200 Message-ID: <20260520155525.22239-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520155525.22239-1-ansuelsmth@gmail.com> References: <20260520155525.22239-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In preparation for support of Airoha AN7583, convert the driver to regmap API. This is needed as Airoha AN7583 will be based on syscon regmap. Signed-off-by: Christian Marangi --- drivers/thermal/airoha_thermal.c | 77 +++++++++++++++++++------------- 1 file changed, 45 insertions(+), 32 deletions(-) diff --git a/drivers/thermal/airoha_thermal.c b/drivers/thermal/airoha_ther= mal.c index 829a7327fc40..b63893a8997a 100644 --- a/drivers/thermal/airoha_thermal.c +++ b/drivers/thermal/airoha_thermal.c @@ -194,7 +194,7 @@ #define AIROHA_MAX_SAMPLES 6 =20 struct airoha_thermal_priv { - void __iomem *base; + struct regmap *map; struct regmap *chip_scu; struct resource scu_adc_res; =20 @@ -265,8 +265,8 @@ static int airoha_thermal_set_trips(struct thermal_zone= _device *tz, int low, RAW_TO_TEMP(priv, FIELD_MAX(EN7581_DOUT_TADC_MASK))); =20 /* We offset the high temp of 1=C2=B0C to trigger correct event */ - writel(TEMP_TO_RAW(priv, high) >> 4, - priv->base + EN7581_TEMPOFFSETH); + regmap_write(priv->map, EN7581_TEMPOFFSETH, + TEMP_TO_RAW(priv, high) >> 4); =20 enable_monitor =3D true; } @@ -277,15 +277,15 @@ static int airoha_thermal_set_trips(struct thermal_zo= ne_device *tz, int low, RAW_TO_TEMP(priv, FIELD_MAX(EN7581_DOUT_TADC_MASK))); =20 /* We offset the low temp of 1=C2=B0C to trigger correct event */ - writel(TEMP_TO_RAW(priv, low) >> 4, - priv->base + EN7581_TEMPOFFSETL); + regmap_write(priv->map, EN7581_TEMPOFFSETL, + TEMP_TO_RAW(priv, low) >> 4); =20 enable_monitor =3D true; } =20 /* Enable sensor 0 monitor after trip are set */ if (enable_monitor) - writel(EN7581_SENSE0_EN, priv->base + EN7581_TEMPMONCTL0); + regmap_write(priv->map, EN7581_TEMPMONCTL0, EN7581_SENSE0_EN); =20 return 0; } @@ -300,9 +300,9 @@ static irqreturn_t airoha_thermal_irq(int irq, void *da= ta) struct airoha_thermal_priv *priv =3D data; enum thermal_notify_event event; bool update =3D false; - u32 status; + u32 status =3D 0; =20 - status =3D readl(priv->base + EN7581_TEMPMONINTSTS); + regmap_read(priv->map, EN7581_TEMPMONINTSTS, &status); switch (status & (EN7581_HOFSINTSTS0 | EN7581_LOFSINTSTS0)) { case EN7581_HOFSINTSTS0: event =3D THERMAL_TRIP_VIOLATED; @@ -318,7 +318,7 @@ static irqreturn_t airoha_thermal_irq(int irq, void *da= ta) } =20 /* Reset Interrupt */ - writel(status, priv->base + EN7581_TEMPMONINTSTS); + regmap_write(priv->map, EN7581_TEMPMONINTSTS, status); =20 if (update) thermal_zone_device_update(priv->tz, event); @@ -329,18 +329,19 @@ static irqreturn_t airoha_thermal_irq(int irq, void *= data) static void airoha_thermal_setup_adc_val(struct device *dev, struct airoha_thermal_priv *priv) { - u32 efuse_calib_info, cpu_sensor; + u32 efuse_calib_info =3D 0; + u32 cpu_sensor =3D 0; =20 /* Setup thermal sensor to ADC mode and setup the mux to DIODE1 */ airoha_init_thermal_ADC_mode(priv); /* sleep 10 ms for ADC to enable */ usleep_range(10 * USEC_PER_MSEC, 11 * USEC_PER_MSEC); =20 - efuse_calib_info =3D readl(priv->base + EN7581_EFUSE_TEMP_OFFSET_REG); + regmap_read(priv->map, EN7581_EFUSE_TEMP_OFFSET_REG, &efuse_calib_info); if (efuse_calib_info) { priv->default_offset =3D FIELD_GET(EN7581_EFUSE_TEMP_OFFSET, efuse_calib= _info); /* Different slope are applied if the sensor is used for CPU or for pack= age */ - cpu_sensor =3D readl(priv->base + EN7581_EFUSE_TEMP_CPU_SENSOR_REG); + regmap_read(priv->map, EN7581_EFUSE_TEMP_CPU_SENSOR_REG, &cpu_sensor); if (cpu_sensor) { priv->default_slope =3D EN7581_SLOPE_X100_DIO_DEFAULT; priv->init_temp =3D EN7581_INIT_TEMP_FTK_X10; @@ -359,8 +360,8 @@ static void airoha_thermal_setup_adc_val(struct device = *dev, static void airoha_thermal_setup_monitor(struct airoha_thermal_priv *priv) { /* Set measure mode */ - writel(FIELD_PREP(EN7581_MSRCTL0, EN7581_MSRCTL_6SAMPLE_MAX_MIX_AVG4), - priv->base + EN7581_TEMPMSRCTL0); + regmap_write(priv->map, EN7581_TEMPMSRCTL0, + FIELD_PREP(EN7581_MSRCTL0, EN7581_MSRCTL_6SAMPLE_MAX_MIX_AVG4)); =20 /* * Configure ADC valid reading addr @@ -375,15 +376,15 @@ static void airoha_thermal_setup_monitor(struct airoh= a_thermal_priv *priv) * We set valid instead of volt as we don't enable valid/volt * split reading and AHB read valid addr in such case. */ - writel(priv->scu_adc_res.start + EN7581_DOUT_TADC, - priv->base + EN7581_TEMPADCVALIDADDR); + regmap_write(priv->map, EN7581_TEMPADCVALIDADDR, + priv->scu_adc_res.start + EN7581_DOUT_TADC); =20 /* * Configure valid bit on a fake value of bit 16. The ADC outputs * max of 2 bytes for voltage. */ - writel(FIELD_PREP(EN7581_ADV_RD_VALID_POS, 16), - priv->base + EN7581_TEMPADCVALIDMASK); + regmap_write(priv->map, EN7581_TEMPADCVALIDMASK, + FIELD_PREP(EN7581_ADV_RD_VALID_POS, 16)); =20 /* * AHB supports max 12 bytes for ADC voltage. Shift the read @@ -391,40 +392,52 @@ static void airoha_thermal_setup_monitor(struct airoh= a_thermal_priv *priv) * in the order of half a =C2=B0C and is acceptable in the context * of triggering interrupt in critical condition. */ - writel(FIELD_PREP(EN7581_ADC_VOLTAGE_SHIFT, 4), - priv->base + EN7581_TEMPADCVOLTAGESHIFT); + regmap_write(priv->map, EN7581_TEMPADCVOLTAGESHIFT, + FIELD_PREP(EN7581_ADC_VOLTAGE_SHIFT, 4)); =20 /* BUS clock is 300MHz counting unit is 3 * 68.64 * 256 =3D 52.715us */ - writel(FIELD_PREP(EN7581_PERIOD_UNIT, 3), - priv->base + EN7581_TEMPMONCTL1); + regmap_write(priv->map, EN7581_TEMPMONCTL1, + FIELD_PREP(EN7581_PERIOD_UNIT, 3)); =20 /* * filt interval is 1 * 52.715us =3D 52.715us, * sen interval is 379 * 52.715us =3D 19.97ms */ - writel(FIELD_PREP(EN7581_FILT_INTERVAL, 1) | - FIELD_PREP(EN7581_SEN_INTERVAL, 379), - priv->base + EN7581_TEMPMONCTL2); + regmap_write(priv->map, EN7581_TEMPMONCTL2, + FIELD_PREP(EN7581_FILT_INTERVAL, 1) | + FIELD_PREP(EN7581_SEN_INTERVAL, 379)); =20 /* AHB poll is set to 146 * 68.64 =3D 10.02us */ - writel(FIELD_PREP(EN7581_ADC_POLL_INTVL, 146), - priv->base + EN7581_TEMPAHBPOLL); + regmap_write(priv->map, EN7581_TEMPAHBPOLL, + FIELD_PREP(EN7581_ADC_POLL_INTVL, 146)); } =20 +static const struct regmap_config airoha_thermal_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, +}; + static int airoha_thermal_probe(struct platform_device *pdev) { struct airoha_thermal_priv *priv; struct device_node *chip_scu_np; struct device *dev =3D &pdev->dev; + void __iomem *base; int irq, ret; =20 priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; =20 - priv->base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + priv->map =3D devm_regmap_init_mmio(dev, base, + &airoha_thermal_regmap_config); + if (IS_ERR(priv->map)) + return PTR_ERR(priv->map); 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[79.22.5.99]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-48fed253f93sm132123215e9.16.2026.05.20.08.55.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2026 08:55:53 -0700 (PDT) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Christian Marangi , Lorenzo Bianconi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v5 4/7] thermal/drivers: airoha: Generalize probe function Date: Wed, 20 May 2026 17:55:17 +0200 Message-ID: <20260520155525.22239-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520155525.22239-1-ansuelsmth@gmail.com> References: <20260520155525.22239-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for support of Airoha AN7583, generalize the probe function to address for the 2 SoC differece. Implement a match_data struct where it's possible to define a more specific probe and post_probe function and specific thermal ops and pllrg protect value. Signed-off-by: Christian Marangi --- drivers/thermal/airoha_thermal.c | 102 +++++++++++++++++++++++-------- 1 file changed, 75 insertions(+), 27 deletions(-) diff --git a/drivers/thermal/airoha_thermal.c b/drivers/thermal/airoha_ther= mal.c index b63893a8997a..ebb47ae5f2ce 100644 --- a/drivers/thermal/airoha_thermal.c +++ b/drivers/thermal/airoha_thermal.c @@ -198,12 +198,23 @@ struct airoha_thermal_priv { struct regmap *chip_scu; struct resource scu_adc_res; =20 + u32 pllrg_protect; + struct thermal_zone_device *tz; int init_temp; int default_slope; int default_offset; }; =20 +struct airoha_thermal_soc_data { + u32 pllrg_protect; + + const struct thermal_zone_device_ops *thdev_ops; + int (*probe)(struct platform_device *pdev, + struct airoha_thermal_priv *priv); + int (*post_probe)(struct platform_device *pdev); +}; + static int airoha_get_thermal_ADC(struct airoha_thermal_priv *priv) { u32 val; @@ -220,7 +231,8 @@ static void airoha_init_thermal_ADC_mode(struct airoha_= thermal_priv *priv) regmap_read(priv->chip_scu, EN7581_PLLRG_PROTECT, &pllrg); =20 /* Give access to thermal regs */ - regmap_write(priv->chip_scu, EN7581_PLLRG_PROTECT, EN7581_SCU_THERMAL_PRO= TECT_KEY); + regmap_write(priv->chip_scu, EN7581_PLLRG_PROTECT, + priv->pllrg_protect); adc_mux =3D FIELD_PREP(EN7581_MUX_TADC, EN7581_SCU_THERMAL_MUX_DIODE1); regmap_write(priv->chip_scu, EN7581_PWD_TADC, adc_mux); =20 @@ -228,7 +240,7 @@ static void airoha_init_thermal_ADC_mode(struct airoha_= thermal_priv *priv) regmap_write(priv->chip_scu, EN7581_PLLRG_PROTECT, pllrg); } =20 -static int airoha_thermal_get_temp(struct thermal_zone_device *tz, int *te= mp) +static int en7581_thermal_get_temp(struct thermal_zone_device *tz, int *te= mp) { struct airoha_thermal_priv *priv =3D thermal_zone_device_priv(tz); int min_value, max_value, avg_value, value; @@ -253,7 +265,7 @@ static int airoha_thermal_get_temp(struct thermal_zone_= device *tz, int *temp) return 0; } =20 -static int airoha_thermal_set_trips(struct thermal_zone_device *tz, int lo= w, +static int en7581_thermal_set_trips(struct thermal_zone_device *tz, int lo= w, int high) { struct airoha_thermal_priv *priv =3D thermal_zone_device_priv(tz); @@ -290,12 +302,12 @@ static int airoha_thermal_set_trips(struct thermal_zo= ne_device *tz, int low, return 0; } =20 -static const struct thermal_zone_device_ops thdev_ops =3D { - .get_temp =3D airoha_thermal_get_temp, - .set_trips =3D airoha_thermal_set_trips, +static const struct thermal_zone_device_ops en7581_thdev_ops =3D { + .get_temp =3D en7581_thermal_get_temp, + .set_trips =3D en7581_thermal_set_trips, }; =20 -static irqreturn_t airoha_thermal_irq(int irq, void *data) +static irqreturn_t en7581_thermal_irq(int irq, void *data) { struct airoha_thermal_priv *priv =3D data; enum thermal_notify_event event; @@ -326,7 +338,7 @@ static irqreturn_t airoha_thermal_irq(int irq, void *da= ta) return IRQ_HANDLED; } =20 -static void airoha_thermal_setup_adc_val(struct device *dev, +static void en7581_thermal_setup_adc_val(struct device *dev, struct airoha_thermal_priv *priv) { u32 efuse_calib_info =3D 0; @@ -357,7 +369,7 @@ static void airoha_thermal_setup_adc_val(struct device = *dev, } } =20 -static void airoha_thermal_setup_monitor(struct airoha_thermal_priv *priv) +static void en7581_thermal_setup_monitor(struct airoha_thermal_priv *priv) { /* Set measure mode */ regmap_write(priv->map, EN7581_TEMPMSRCTL0, @@ -412,30 +424,26 @@ static void airoha_thermal_setup_monitor(struct airoh= a_thermal_priv *priv) FIELD_PREP(EN7581_ADC_POLL_INTVL, 146)); } =20 -static const struct regmap_config airoha_thermal_regmap_config =3D { +static const struct regmap_config en7581_thermal_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, .val_bits =3D 32, }; =20 -static int airoha_thermal_probe(struct platform_device *pdev) +static int en7581_thermal_probe(struct platform_device *pdev, + struct airoha_thermal_priv *priv) { - struct airoha_thermal_priv *priv; struct device_node *chip_scu_np; struct device *dev =3D &pdev->dev; void __iomem *base; int irq, ret; =20 - priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); =20 priv->map =3D devm_regmap_init_mmio(dev, base, - &airoha_thermal_regmap_config); + &en7581_thermal_regmap_config); if (IS_ERR(priv->map)) return PTR_ERR(priv->map); =20 @@ -455,18 +463,55 @@ static int airoha_thermal_probe(struct platform_devic= e *pdev) return irq; =20 ret =3D devm_request_threaded_irq(&pdev->dev, irq, NULL, - airoha_thermal_irq, IRQF_ONESHOT, + en7581_thermal_irq, IRQF_ONESHOT, pdev->name, priv); if (ret) { dev_err(dev, "Can't get interrupt working.\n"); return ret; } =20 - airoha_thermal_setup_monitor(priv); - airoha_thermal_setup_adc_val(dev, priv); + en7581_thermal_setup_monitor(priv); + en7581_thermal_setup_adc_val(dev, priv); + + return 0; +} + +static int en7581_thermal_post_probe(struct platform_device *pdev) +{ + struct airoha_thermal_priv *priv =3D platform_get_drvdata(pdev); + + /* Enable LOW and HIGH interrupt (if supported) */ + regmap_write(priv->map, EN7581_TEMPMONINT, + EN7581_HOFSINTEN0 | EN7581_LOFSINTEN0); + + return 0; +} + +static int airoha_thermal_probe(struct platform_device *pdev) +{ + const struct airoha_thermal_soc_data *soc_data; + struct airoha_thermal_priv *priv; + struct device *dev =3D &pdev->dev; + int ret; + + soc_data =3D device_get_match_data(dev); + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->pllrg_protect =3D soc_data->pllrg_protect; + + if (!soc_data->probe) + return -EINVAL; + + ret =3D soc_data->probe(pdev, priv); + if (ret) + return ret; =20 /* register of thermal sensor and get info from DT */ - priv->tz =3D devm_thermal_of_zone_register(dev, 0, priv, &thdev_ops); + priv->tz =3D devm_thermal_of_zone_register(dev, 0, priv, + soc_data->thdev_ops); if (IS_ERR(priv->tz)) { dev_err(dev, "register thermal zone sensor failed\n"); return PTR_ERR(priv->tz); @@ -474,15 +519,18 @@ static int airoha_thermal_probe(struct platform_devic= e *pdev) =20 platform_set_drvdata(pdev, priv); =20 - /* Enable LOW and HIGH interrupt */ - regmap_write(priv->map, EN7581_TEMPMONINT, - EN7581_HOFSINTEN0 | EN7581_LOFSINTEN0); - - return 0; + return soc_data->post_probe ? soc_data->post_probe(pdev) : 0; } =20 +static const struct airoha_thermal_soc_data en7581_data =3D { + .pllrg_protect =3D EN7581_SCU_THERMAL_PROTECT_KEY, + .thdev_ops =3D &en7581_thdev_ops, + .probe =3D &en7581_thermal_probe, + .post_probe =3D &en7581_thermal_post_probe, +}; + static const struct of_device_id airoha_thermal_match[] =3D { - { .compatible =3D "airoha,en7581-thermal" }, + { .compatible =3D "airoha,en7581-thermal", .data =3D &en7581_data }, {}, }; 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[79.22.5.99]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-48fed253f93sm132123215e9.16.2026.05.20.08.55.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2026 08:55:54 -0700 (PDT) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Christian Marangi , Lorenzo Bianconi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v5 5/7] thermal/drivers: airoha: Generalize get_thermal_ADC and set_mux function Date: Wed, 20 May 2026 17:55:18 +0200 Message-ID: <20260520155525.22239-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520155525.22239-1-ansuelsmth@gmail.com> References: <20260520155525.22239-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for support of Airoha AN7583, generalize get_thermal_ADC() and set_thermal_mux() with the use of reg_field API. This is to account the same logic between the current supported SoC and the new one but with different register address. While at it also further improve some comments and move sleep inside the set_thermal_mux function. Signed-off-by: Christian Marangi --- drivers/thermal/airoha_thermal.c | 56 +++++++++++++++++++++++++------- 1 file changed, 44 insertions(+), 12 deletions(-) diff --git a/drivers/thermal/airoha_thermal.c b/drivers/thermal/airoha_ther= mal.c index ebb47ae5f2ce..249abbbd46bc 100644 --- a/drivers/thermal/airoha_thermal.c +++ b/drivers/thermal/airoha_thermal.c @@ -193,9 +193,18 @@ =20 #define AIROHA_MAX_SAMPLES 6 =20 +enum airoha_thermal_chip_scu_field { + AIROHA_THERMAL_DOUT_TADC, + AIROHA_THERMAL_MUX_TADC, + + /* keep last */ + AIROHA_THERMAL_FIELD_MAX, +}; + struct airoha_thermal_priv { struct regmap *map; struct regmap *chip_scu; + struct regmap_field *chip_scu_fields[AIROHA_THERMAL_FIELD_MAX]; struct resource scu_adc_res; =20 u32 pllrg_protect; @@ -219,25 +228,32 @@ static int airoha_get_thermal_ADC(struct airoha_therm= al_priv *priv) { u32 val; =20 - regmap_read(priv->chip_scu, EN7581_DOUT_TADC, &val); - return FIELD_GET(EN7581_DOUT_TADC_MASK, val); + regmap_field_read(priv->chip_scu_fields[AIROHA_THERMAL_DOUT_TADC], + &val); + return val; } =20 -static void airoha_init_thermal_ADC_mode(struct airoha_thermal_priv *priv) +static void airoha_set_thermal_mux(struct airoha_thermal_priv *priv, + int tdac_idx) { - u32 adc_mux, pllrg; + u32 pllrg; =20 /* Save PLLRG current value */ regmap_read(priv->chip_scu, EN7581_PLLRG_PROTECT, &pllrg); =20 - /* Give access to thermal regs */ + /* Give access to Thermal regs */ regmap_write(priv->chip_scu, EN7581_PLLRG_PROTECT, priv->pllrg_protect); - adc_mux =3D FIELD_PREP(EN7581_MUX_TADC, EN7581_SCU_THERMAL_MUX_DIODE1); - regmap_write(priv->chip_scu, EN7581_PWD_TADC, adc_mux); + + /* Configure Thermal ADC mux to tdac_idx */ + regmap_field_write(priv->chip_scu_fields[AIROHA_THERMAL_MUX_TADC], + tdac_idx); =20 /* Restore PLLRG value on exit */ regmap_write(priv->chip_scu, EN7581_PLLRG_PROTECT, pllrg); + + /* Sleep 10 ms for Thermal ADC to enable */ + usleep_range(10 * USEC_PER_MSEC, 11 * USEC_PER_MSEC); } =20 static int en7581_thermal_get_temp(struct thermal_zone_device *tz, int *te= mp) @@ -344,10 +360,8 @@ static void en7581_thermal_setup_adc_val(struct device= *dev, u32 efuse_calib_info =3D 0; u32 cpu_sensor =3D 0; =20 - /* Setup thermal sensor to ADC mode and setup the mux to DIODE1 */ - airoha_init_thermal_ADC_mode(priv); - /* sleep 10 ms for ADC to enable */ - usleep_range(10 * USEC_PER_MSEC, 11 * USEC_PER_MSEC); + /* Setup Thermal Sensor to ADC mode and setup the mux to DIODE1 */ + airoha_set_thermal_mux(priv, EN7581_SCU_THERMAL_MUX_DIODE1); =20 regmap_read(priv->map, EN7581_EFUSE_TEMP_OFFSET_REG, &efuse_calib_info); if (efuse_calib_info) { @@ -430,13 +444,18 @@ static const struct regmap_config en7581_thermal_regm= ap_config =3D { .val_bits =3D 32, }; =20 +static const struct reg_field en7581_chip_scu_fields[AIROHA_THERMAL_FIELD_= MAX] =3D { + [AIROHA_THERMAL_DOUT_TADC] =3D REG_FIELD(EN7581_DOUT_TADC, 0, 15), + [AIROHA_THERMAL_MUX_TADC] =3D REG_FIELD(EN7581_PWD_TADC, 1, 3), +}; + static int en7581_thermal_probe(struct platform_device *pdev, struct airoha_thermal_priv *priv) { struct device_node *chip_scu_np; struct device *dev =3D &pdev->dev; void __iomem *base; - int irq, ret; + int i, irq, ret; =20 base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) @@ -455,6 +474,19 @@ static int en7581_thermal_probe(struct platform_device= *pdev, if (IS_ERR(priv->chip_scu)) return PTR_ERR(priv->chip_scu); =20 + for (i =3D 0; i < AIROHA_THERMAL_FIELD_MAX; i++) { + struct regmap_field *field; + + field =3D devm_regmap_field_alloc(dev, priv->chip_scu, + en7581_chip_scu_fields[i]); + if (IS_ERR(field)) { + of_node_put(chip_scu_np); + return PTR_ERR(field); + } + + priv->chip_scu_fields[i] =3D field; + } + of_address_to_resource(chip_scu_np, 0, &priv->scu_adc_res); of_node_put(chip_scu_np); =20 --=20 2.53.0 From nobody Sun May 24 22:35:48 2026 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5D16352024 for ; Wed, 20 May 2026 15:55:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[79.22.5.99]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-48fed253f93sm132123215e9.16.2026.05.20.08.55.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2026 08:55:56 -0700 (PDT) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Christian Marangi , Lorenzo Bianconi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v5 6/7] dt-bindings: arm: airoha: Add the chip-scu node for AN7583 SoC Date: Wed, 20 May 2026 17:55:19 +0200 Message-ID: <20260520155525.22239-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520155525.22239-1-ansuelsmth@gmail.com> References: <20260520155525.22239-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document support for Airoha AN7583 chip-scu node. This is similar to Airoha EN7581 with the addition of the presence of thermal sensor in addition to controlling HW PIN and other miscellaneous pheriperals. Signed-off-by: Christian Marangi Reviewed-by: Krzysztof Kozlowski --- .../bindings/arm/airoha,en7581-chip-scu.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/airoha,en7581-chip-scu.y= aml b/Documentation/devicetree/bindings/arm/airoha,en7581-chip-scu.yaml index 67c449d804c2..cc564dc7b414 100644 --- a/Documentation/devicetree/bindings/arm/airoha,en7581-chip-scu.yaml +++ b/Documentation/devicetree/bindings/arm/airoha,en7581-chip-scu.yaml @@ -19,15 +19,29 @@ properties: items: - enum: - airoha,en7581-chip-scu + - airoha,an7583-chip-scu - const: syscon =20 reg: maxItems: 1 =20 + '#thermal-sensor-cells': + const: 0 + required: - compatible - reg =20 +if: + properties: + compatible: + contains: + const: airoha,en7581-chip-scu + +then: + properties: + '#thermal-sensor-cells': false + additionalProperties: false =20 examples: --=20 2.53.0 From nobody Sun May 24 22:35:48 2026 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B9F63546CA for ; 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[79.22.5.99]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-48fed253f93sm132123215e9.16.2026.05.20.08.55.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2026 08:55:57 -0700 (PDT) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Christian Marangi , Lorenzo Bianconi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v5 7/7] thermal/drivers: airoha: Add support for AN7583 Thermal Sensor Date: Wed, 20 May 2026 17:55:20 +0200 Message-ID: <20260520155525.22239-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520155525.22239-1-ansuelsmth@gmail.com> References: <20260520155525.22239-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for Airoha AN7583 Thermal driver. This apply similar logic on how to read the temperature but totally drop support for the PTP_THERMAL subsystem. PTP_THERMAL subsystem was a way to trigger trip point from hardware by configuring how to read the temperature internally. This subsystem has been totally removed from Airoha AN7583 permitting only to read the temperature. The SoC support up to 3 sensor but the original driver always read the BGA sensor hence it's currently implemented reading only this specific sensor. Reference and values for the other 2 sensor are defined for further implementation if confirmed working. set_thermal_mux() is extended to also address muxing the sensor as AN7583 use a different way to read the temperature from 3 different diode. The EN7581 code is updated to account for these changes. Signed-off-by: Christian Marangi --- drivers/thermal/airoha_thermal.c | 161 ++++++++++++++++++++++++++++++- 1 file changed, 157 insertions(+), 4 deletions(-) diff --git a/drivers/thermal/airoha_thermal.c b/drivers/thermal/airoha_ther= mal.c index 249abbbd46bc..c84b5c36e880 100644 --- a/drivers/thermal/airoha_thermal.c +++ b/drivers/thermal/airoha_thermal.c @@ -18,6 +18,12 @@ #define EN7581_DOUT_TADC 0x2f8 #define EN7581_DOUT_TADC_MASK GENMASK(15, 0) =20 +#define AN7583_MUX_SENSOR 0x2a0 +#define AN7583_LOAD_ADJ GENMASK(3, 2) +#define AN7583_MUX_TADC 0x2e4 +#define AN7583_MUX_TADC_MASK GENMASK(3, 1) +#define AN7583_DOUT_TADC 0x2f0 + /* PTP_THERMAL regs */ #define EN7581_TEMPMONCTL0 0x800 #define EN7581_SENSE3_EN BIT(3) @@ -181,6 +187,11 @@ #define EN7581_SCU_THERMAL_PROTECT_KEY 0x12 #define EN7581_SCU_THERMAL_MUX_DIODE1 0x7 =20 +#define AN7583_SCU_THERMAL_PROTECT_KEY 0x80 +#define AN7583_NUM_SENSOR 3 + +#define AIROHA_THERMAL_NO_MUX_SENSOR -1 + /* Convert temp to raw value as read from ADC ((((temp / 100) - init) * sl= ope) / 1000) + offset */ #define TEMP_TO_RAW(priv, temp) ((((((temp) / 100) - (priv)->init_temp) = * \ (priv)->default_slope) / 1000) + \ @@ -193,8 +204,39 @@ =20 #define AIROHA_MAX_SAMPLES 6 =20 +/* + * AN7583 supports all these ADC mux but the original driver + * always checked temp with the AN7583_BGP_TEMP_SENSOR. + * Assume using the other sensor temperature is invalid and + * always read from AN7583_BGP_TEMP_SENSOR. + * + * On top of this it's defined that AN7583 supports 3 + * sensor: AN7583_BGP_TEMP_SENSOR, AN7583_GBE_TEMP_SENSOR, + * AN7583_CPU_TEMP_SENSOR. + * + * Provide the ADC mux for reference. + */ +enum an7583_thermal_adc_mux { + AN7583_BGP_TEMP_SENSOR, + AN7583_PAD_AVS, + AN7583_CORE_POWER, + AN7583_AVSDAC_OUT, + AN7583_VCM, + AN7583_GBE_TEMP_SENSOR, + AN7583_CPU_TEMP_SENSOR, + + AN7583_ADC_MUX_MAX, +}; + +enum an7583_thermal_diode_mux { + AN7583_D0_TADC, + AN7583_ZERO_TADC, + AN7583_D1_TADC, +}; + enum airoha_thermal_chip_scu_field { AIROHA_THERMAL_DOUT_TADC, + AIROHA_THERMAL_MUX_SENSOR, AIROHA_THERMAL_MUX_TADC, =20 /* keep last */ @@ -208,6 +250,7 @@ struct airoha_thermal_priv { struct resource scu_adc_res; =20 u32 pllrg_protect; + int current_adc; =20 struct thermal_zone_device *tz; int init_temp; @@ -224,6 +267,24 @@ struct airoha_thermal_soc_data { int (*post_probe)(struct platform_device *pdev); }; =20 +static const unsigned int an7583_thermal_coeff[AN7583_ADC_MUX_MAX] =3D { + [AN7583_BGP_TEMP_SENSOR] =3D 973, + [AN7583_GBE_TEMP_SENSOR] =3D 995, + [AN7583_CPU_TEMP_SENSOR] =3D 1035, +}; + +static const unsigned int an7583_thermal_slope[AN7583_ADC_MUX_MAX] =3D { + [AN7583_BGP_TEMP_SENSOR] =3D 7440, + [AN7583_GBE_TEMP_SENSOR] =3D 7620, + [AN7583_CPU_TEMP_SENSOR] =3D 8390, +}; + +static const unsigned int an7583_thermal_offset[AN7583_ADC_MUX_MAX] =3D { + [AN7583_BGP_TEMP_SENSOR] =3D 294, + [AN7583_GBE_TEMP_SENSOR] =3D 298, + [AN7583_CPU_TEMP_SENSOR] =3D 344, +}; + static int airoha_get_thermal_ADC(struct airoha_thermal_priv *priv) { u32 val; @@ -234,7 +295,7 @@ static int airoha_get_thermal_ADC(struct airoha_thermal= _priv *priv) } =20 static void airoha_set_thermal_mux(struct airoha_thermal_priv *priv, - int tdac_idx) + int tdac_idx, int sensor_idx) { u32 pllrg; =20 @@ -245,9 +306,20 @@ static void airoha_set_thermal_mux(struct airoha_therm= al_priv *priv, regmap_write(priv->chip_scu, EN7581_PLLRG_PROTECT, priv->pllrg_protect); =20 + /* + * Configure Thermal Sensor mux to sensor_idx. + * (if not supported, sensor_idx is AIROHA_THERMAL_NO_MUX_SENSOR) + */ + if (sensor_idx !=3D AIROHA_THERMAL_NO_MUX_SENSOR) + regmap_field_write(priv->chip_scu_fields[AIROHA_THERMAL_MUX_SENSOR], + sensor_idx); + /* Configure Thermal ADC mux to tdac_idx */ - regmap_field_write(priv->chip_scu_fields[AIROHA_THERMAL_MUX_TADC], - tdac_idx); + if (priv->current_adc !=3D tdac_idx) { + regmap_field_write(priv->chip_scu_fields[AIROHA_THERMAL_MUX_TADC], + tdac_idx); + priv->current_adc =3D tdac_idx; + } =20 /* Restore PLLRG value on exit */ regmap_write(priv->chip_scu, EN7581_PLLRG_PROTECT, pllrg); @@ -361,7 +433,8 @@ static void en7581_thermal_setup_adc_val(struct device = *dev, u32 cpu_sensor =3D 0; =20 /* Setup Thermal Sensor to ADC mode and setup the mux to DIODE1 */ - airoha_set_thermal_mux(priv, EN7581_SCU_THERMAL_MUX_DIODE1); + airoha_set_thermal_mux(priv, EN7581_SCU_THERMAL_MUX_DIODE1, + AIROHA_THERMAL_NO_MUX_SENSOR); =20 regmap_read(priv->map, EN7581_EFUSE_TEMP_OFFSET_REG, &efuse_calib_info); if (efuse_calib_info) { @@ -477,6 +550,10 @@ static int en7581_thermal_probe(struct platform_device= *pdev, for (i =3D 0; i < AIROHA_THERMAL_FIELD_MAX; i++) { struct regmap_field *field; =20 + /* Skip registering MUX_SENSOR field as not supported */ + if (i =3D=3D AIROHA_THERMAL_MUX_SENSOR) + continue; + field =3D devm_regmap_field_alloc(dev, priv->chip_scu, en7581_chip_scu_fields[i]); if (IS_ERR(field)) { @@ -519,6 +596,74 @@ static int en7581_thermal_post_probe(struct platform_d= evice *pdev) return 0; } =20 +static int an7583_thermal_get_temp(struct thermal_zone_device *tz, int *te= mp) +{ + struct airoha_thermal_priv *priv =3D thermal_zone_device_priv(tz); + int sensor_idx; + int delta_diode, delta_gain; + int coeff, slope, offset; + + int diode_zero, diode_d0, diode_d1; + + /* Always read sensor AN7583_BGP_TEMP_SENSOR */ + sensor_idx =3D AN7583_BGP_TEMP_SENSOR; + + coeff =3D an7583_thermal_coeff[sensor_idx]; + slope =3D an7583_thermal_slope[sensor_idx]; + offset =3D an7583_thermal_offset[sensor_idx]; + + airoha_set_thermal_mux(priv, AN7583_ZERO_TADC, sensor_idx); + diode_zero =3D airoha_get_thermal_ADC(priv); + airoha_set_thermal_mux(priv, AN7583_D0_TADC, sensor_idx); + diode_d0 =3D airoha_get_thermal_ADC(priv); + airoha_set_thermal_mux(priv, AN7583_D1_TADC, sensor_idx); + diode_d1 =3D airoha_get_thermal_ADC(priv); + + delta_diode =3D diode_d1 - diode_d0; + delta_gain =3D (delta_diode * coeff) / 100 + (diode_zero - diode_d1); + if (!delta_gain) + return -EINVAL; + + *temp =3D (slope * delta_diode * 10) / delta_gain - offset * 10; + *temp *=3D 100; + + return 0; +} + +static const struct thermal_zone_device_ops an7583_tz_ops =3D { + .get_temp =3D an7583_thermal_get_temp, +}; + +static const struct reg_field an7583_chip_scu_fields[AIROHA_THERMAL_FIELD_= MAX] =3D { + [AIROHA_THERMAL_DOUT_TADC] =3D REG_FIELD(AN7583_DOUT_TADC, 0, 31), + [AIROHA_THERMAL_MUX_TADC] =3D REG_FIELD(AN7583_MUX_TADC, 1, 3), + [AIROHA_THERMAL_MUX_SENSOR] =3D REG_FIELD(AN7583_MUX_SENSOR, 2, 3), +}; + +static int an7583_thermal_probe(struct platform_device *pdev, + struct airoha_thermal_priv *priv) +{ + struct device *dev =3D &pdev->dev; + int i; + + priv->chip_scu =3D device_node_to_regmap(dev->of_node); + if (IS_ERR(priv->chip_scu)) + return PTR_ERR(priv->chip_scu); + + for (i =3D 0; i < AIROHA_THERMAL_FIELD_MAX; i++) { + struct regmap_field *field; + + field =3D devm_regmap_field_alloc(dev, priv->chip_scu, + an7583_chip_scu_fields[i]); + if (IS_ERR(field)) + return PTR_ERR(field); + + priv->chip_scu_fields[i] =3D field; + } + + return 0; +} + static int airoha_thermal_probe(struct platform_device *pdev) { const struct airoha_thermal_soc_data *soc_data; @@ -533,6 +678,7 @@ static int airoha_thermal_probe(struct platform_device = *pdev) return -ENOMEM; =20 priv->pllrg_protect =3D soc_data->pllrg_protect; + priv->current_adc =3D -1; =20 if (!soc_data->probe) return -EINVAL; @@ -561,8 +707,15 @@ static const struct airoha_thermal_soc_data en7581_dat= a =3D { .post_probe =3D &en7581_thermal_post_probe, }; =20 +static const struct airoha_thermal_soc_data an7583_data =3D { + .pllrg_protect =3D AN7583_SCU_THERMAL_PROTECT_KEY, + .thdev_ops =3D &an7583_tz_ops, + .probe =3D &an7583_thermal_probe, +}; + static const struct of_device_id airoha_thermal_match[] =3D { { .compatible =3D "airoha,en7581-thermal", .data =3D &en7581_data }, + { .compatible =3D "airoha,an7583-chip-scu", .data =3D &an7583_data }, {}, }; MODULE_DEVICE_TABLE(of, airoha_thermal_match); --=20 2.53.0