From nobody Mon May 25 00:08:41 2026 Received: from BN8PR05CU002.outbound.protection.outlook.com (mail-eastus2azon11011065.outbound.protection.outlook.com [52.101.57.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3FAD3B3890 for ; Wed, 20 May 2026 09:37:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.57.65 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779269827; cv=fail; b=WAHwkcI4PoYSV4nmop7jbEA1mW/uACK0YqhWoQfHbv3nGJ+5LptRSWO79BodM+afkfJ2mjRr+V2dqv3asNPnEa98hpw4TP6/0hWf8bf7mwIeXagwmw1g0Thovf/IxixvoH2s/UzMqldZW+6qxpDuHyef/kcFH04TW1e6MrB9GR4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779269827; c=relaxed/simple; bh=t5ZKMXc0u/XSVbBoXrkdQVrPufs0oXXuV9f1m+Pv1xY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LysxXVphHEukpdzqM4uvIzT8FuGs/jqw6tSBYfQAOqYwAQqR9+CIewiNB5sCXmzLHCTfdHrIS9Ez3k97DiTzUcr8Ld2DhnQRt1yVBJV7Q5t/A6yvLpKG3aVOktzW77QbPddPOWZylZxc89k0hOubm/YSbe4MKjYusYkjCw6gYew= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=ad/4D0Di; arc=fail smtp.client-ip=52.101.57.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="ad/4D0Di" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=gcXIQ/sgVZALmYo8POO04sD70lqGDOU/qnR2rAnKVa850deZ9/DjGNZY5yplbtw40rpoeJIE6J9IYrAuZf121nUFkvm6p+uxn5D5LC06Qddy5XmUfuxDbqeSWuBpk2/PdwOvT4SV+0KPQlD956xWMj2veFm9TWIW83pXbEb2+d1HlunqbuhLzQB8PO/913UrnrydlM3PvA+QAHF8rhDoMU7dKaxRMyg5bao6l6alISaub9wEzv7FTgpa6isgPm9WwaopyKNzbgNHiHdLh0dQnYu7t+bRbAgomjCFniWv6dfa1AP9isJUy618qr1hGJ9/S/zuODY8kJ04mS9tEFYb3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=qcUCfWOb7E/MCTe0mysr/KonOU+PtVIQA29jn5U8pCE=; b=M5WHOV+LUFrV9kI/V/UOgvehRcAhbjTxvE4C656wYJ/nejbsAnzII4PGnrgvF2LP9a5wbre/3JiF82Mnknt+eH+NLiTmpH78LAmBJhdLEgWwTz0StXWScFQtQiF9HiTUTK3xBeNqsLUGl/Jb7egQd3ogGt1leue8HO3UToXK+aeSEF4lR/WdMct1GPBc0KKfSEWSG8TX/1k+DJ0tnyBoG07ojG8XTEEhfe2ifonxTR20J7DYK/JJDgmKZyPIL3tkIWEsdIPeudjmELWsQNiMgJR4vkGcKAvzoktEvKGIlDyeTg7XHnMdx2Bl/8mjzFueZJmBtjPCPS7Na/Vgoc3pgg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qcUCfWOb7E/MCTe0mysr/KonOU+PtVIQA29jn5U8pCE=; b=ad/4D0Di+o2kyszELhJjUtsnw5uf5WDXLlFI7rQx9mcO7wGUG+R/EuRQ3O8dwoyudEY0EbdU0gLcqVy1+mb3CKSoGW1zc9ECigN+hNgyGOe/qzv2CbCI1wEcj36J3PrLUy2jWDyUzV7ifPYmz03VmB88JiGAK85DC0uSAKlh/9s= Received: from SJ0PR05CA0070.namprd05.prod.outlook.com (2603:10b6:a03:332::15) by SA0PR12MB4365.namprd12.prod.outlook.com (2603:10b6:806:96::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.14; Wed, 20 May 2026 09:37:02 +0000 Received: from CO1PEPF000075ED.namprd03.prod.outlook.com (2603:10b6:a03:332:cafe::2e) by SJ0PR05CA0070.outlook.office365.com (2603:10b6:a03:332::15) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.13 via Frontend Transport; Wed, 20 May 2026 09:37:02 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by CO1PEPF000075ED.mail.protection.outlook.com (10.167.249.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Wed, 20 May 2026 09:37:02 +0000 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Wed, 20 May 2026 04:37:00 -0500 Received: from xsjarunbala52.xilinx.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Wed, 20 May 2026 04:37:00 -0500 From: Ronak Jain To: , CC: , , Subject: [PATCH v2 1/2] Documentation: ABI: add sysfs interface for ZynqMP CSU registers Date: Wed, 20 May 2026 02:36:53 -0700 Message-ID: <20260520093654.3303917-2-ronak.jain@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260520093654.3303917-1-ronak.jain@amd.com> References: <20260520093654.3303917-1-ronak.jain@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075ED:EE_|SA0PR12MB4365:EE_ X-MS-Office365-Filtering-Correlation-Id: 56578010-c72c-4ccc-6b03-08deb65358f5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700016|376014|22082099003|18002099003|56012099003|11063799006|3023799007; X-Microsoft-Antispam-Message-Info: lthNOzwkbAWIBo+u7pWyq3LYLu/sDE/aEYRlCZvB9zArgChEXFa11TMwYLiJCkF25eZGsruH7v920wPZZA3td6033OCW/kAy1bp2pK+77DobUJaFKRRP7WcXETrPSlQPqm+JRbbHfEKHOG4y3SADGD3/gZWBd/kclVwwR1OIUWqjDzC26aYiNfYvsn9QNqswFgKjc3n3Sh5kqyf0LDtOQ3Czu7/sbubydM5swuG6VfE6RxXUk8bsMPBnyoLk2hYvywkrkp2MTXNcC08fFMNshg3d8PuCg7uS84dSBSMA9IBuiyd9p8eBC6WP04Sv3NQk+dKubLdfH+7IAwpSRtoTSwEp7D1I6v1EBGZlSM2vgJ/HCq4QVbNGFHw8MkFsUn6XwApPk6uncN9Rm6lyuyR/o+hyx1Ve6HpGcjB0VRIvgpP8tUwuhSfp2cax8ckvkrFWGWGrs2T170YRcRDigbuOBHZnLbbsDB4aMSytaB0WMlLaglXdUoXCLCn5+XtsNvBCol064ciA7izigSdSOKfbM0YJ1Jy/1IB0spzB6Oh5GO2WKK1EL5xBooYvD7g+2MTcn/Zh50LAAwJ0t32lX9lOBZnxBdSPVnOU0aQsGlqBMoG3QBdtl8b6CNrpqc+xAMP4KBvm/E5PvtXAVR5sY09vOfSubPAW6mime5xYW7fMf04MwaRbQRaOXJDt3Cs/ULuLRqpkIKocB5ZmghgqBIJPe/WH5LkaZQ4mlA8XwJkU5Yk= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700016)(376014)(22082099003)(18002099003)(56012099003)(11063799006)(3023799007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /o3H4G2Nvs7guqwZTZa/I/x+3w8MTQqgtpSjpigbqLwLghXOPK2ywbz0ssDfzT+zh+0vFk5bihn2HHZF/jeAHP25gyd67Ca+zYYBJaTOsCZsO/heg2osS7DXUeKMPxPWOLMX/by7WNDYndsHkCJSSCGy5iJrtBiV6Fbe8bb6y3uDQiOPvsMlQuW9TdqQG48Gr18yuFsKkX3n2SIKAqprEb6xtX2qGlMELtT5UQnBOllAYPZJgwQ+dQEsq/Lr85QIxdTh/JcMuFXR3XXBoJyASedMhWysmMMTlhpEZjFxY6/tD6Djj145l/hAF5ysXJg31a2Y43rUqIMyBm9U6vkmtteLhoD8puVwtHCcGJJqAhgvHq2Q2sAHxQwRTdyGYBV9s+zpfwSmHoCxPec+aPJ9nVVw826ZgNTap7YdcKhMun6cJ9EehNLdKwegyyTp3qGI X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 May 2026 09:37:02.2866 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 56578010-c72c-4ccc-6b03-08deb65358f5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075ED.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4365 Content-Type: text/plain; charset="utf-8" Document the new sysfs interface that exposes Configuration Security Unit (CSU) registers through the zynqmp-firmware driver. The interface is available under: /sys/devices/platform/firmware:zynqmp-firmware/csu_registers/ The CSU registers are discovered at boot time using the PM_QUERY_DATA firmware API. The following registers are currently supported: - multiboot (CSU_MULTI_BOOT) - idcode (CSU_IDCODE, read-only) - pcap-status (CSU_PCAP_STATUS, read-only) Read operations use the existing IOCTL_READ_REG firmware interface, while write operations use IOCTL_MASK_WRITE_REG. Access control is enforced by the firmware. Write attempts to read-only registers are rejected by firmware even though the sysfs file permissions allow writes. Document the ABI entry accordingly. Signed-off-by: Ronak Jain --- .../ABI/stable/sysfs-driver-firmware-zynqmp | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/Documentation/ABI/stable/sysfs-driver-firmware-zynqmp b/Docume= ntation/ABI/stable/sysfs-driver-firmware-zynqmp index c3fec3c835af..f9b004e33696 100644 --- a/Documentation/ABI/stable/sysfs-driver-firmware-zynqmp +++ b/Documentation/ABI/stable/sysfs-driver-firmware-zynqmp @@ -254,3 +254,36 @@ Description: The expected result is 500. =20 Users: Xilinx + +What: /sys/devices/platform/firmware\:zynqmp-firmware/csu_registers/* +Date: May 2026 +KernelVersion: 7.1 +Contact: "Ronak Jain" +Description: + Read/Write CSU (Configuration Security Unit) registers. + + This interface provides dynamic access to CSU registers that are + discovered from the firmware at boot time using PM_QUERY_DATA API. + + The supported registers are: + + - multiboot: CSU_MULTI_BOOT register + - idcode: CSU_IDCODE register (read-only) + - pcap-status: CSU_PCAP_STATUS register (read-only) + + Read operations use the existing IOCTL_READ_REG API. + Write operations use the existing IOCTL_MASK_WRITE_REG API. + + The firmware enforces access control - read-only registers will reject + write attempts even though the sysfs permissions show write access. + + Usage for reading:: + + # cat /sys/devices/platform/firmware\:zynqmp-firmware/csu_registers/= multiboot + # cat /sys/devices/platform/firmware\:zynqmp-firmware/csu_registers/= idcode + + Usage for writing (mask and value are in hexadecimal):: + + # echo 0xFFFFFFF 0x0 > /sys/devices/platform/firmware\:zynqmp-firmwa= re/csu_registers/multiboot + +Users: Xilinx/AMD --=20 2.34.1 From nobody Mon May 25 00:08:41 2026 Received: from CO1PR03CU002.outbound.protection.outlook.com (mail-westus2azon11010008.outbound.protection.outlook.com [52.101.46.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3C0C3C945B for ; Wed, 20 May 2026 09:37:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.46.8 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779269832; cv=fail; b=hi4D9KmqjXHla9nbG0RuWArbyXDS9okp0tO6qsvvAOyQnw+axg2E01dW8gfSIXtuKTzKX+e9mRIp1VBb+jObB9NR6dsTUG4XNgOS22BsHTFe/UXkcAOU3Q4n9XJazKqUxGSIv9pGaqmGcJgIw5DYf4bkcKwCoh4Z6rmk0JiJU7w= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779269832; c=relaxed/simple; bh=UIQI/c3fj2f9unCbRFfYzw3xPp92415OkSamhmrwsxA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=m9/oxXl/xPnwNtSg7Qy5wEpmDRd5J0izmNOk28OYe07zOFZx9sVaFFpwTbFlEJUMZkBpzZ5k+7brRFfA6vHOBP5yFnBnpv78E84LJCzEh+6eQV3ipCQWBPcIg/JPz1AORQ6RfXsBy4doTupN9Ig3Y0Oe9zpXrpQnGV6VZnXCjPw= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=ofc0cg3B; arc=fail smtp.client-ip=52.101.46.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="ofc0cg3B" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=OWsBofw7pPVhJ14u3PrUPrUqmvds56rI23toIai8MmQiawAadrv2Xv/uovquhFvUKGA9JRsOPNVnLLi6wzU1fAIntmev0QTKTGJ4wCAoWdt7v2iGjff8HEtqGAtmJbnVGlxxJT1f1tmhJ3XE/MROLW+OfDgX9MHTwfRlJ+Xzs5y3ymCUAGAWQEcfAhz6Tnbd3F1xGeKtTFMDXHuwngXhyKJXmbfJ+xLrVaNHW3iGdaOkIaV7pGMmxXkuc+819yYrYLZMCl7UwUDVLnfuctxHDxidzYKtn0FWMR5au1pcM/R0HYj/gu6CEqU1i5tPFKbJ/1LUrEOrE65YONSftW4EJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=mlXK/G8Cuw0mLf6f4UHL+RTO0u0J0ylbIiUnxWGvwRM=; b=Vrxa+DlbKADYpDLyuccqODK+v8Xzwwmbvhik1SAr2JGuXIFN4AYm+BnK81neFz/JgHUEeklWWMyUr2OrIiGa57sZTJDaGVWbYi+Q3sQso6DQJr4eCl32PLRkkzx2dvRhUvU7hHk76ZO5QB4n9EUStrOy8CjB1Z2XA/Chlrpxn+tLAMRg7FeVnqYloJGzSlC2d9N0eQFXCbPhBcI2pXZJxtquPdAz7qL90bmynmZ4+PJLS4VxZQGzDXHDZG69quMN8r6LrHjirKfJ+PeMyjbTFyM2h/H1h8a3hHu09HMfgcbH1rUZ046CVbjIQj3hsmxQRTPQis575QO+1bn1w8Tb6Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=mlXK/G8Cuw0mLf6f4UHL+RTO0u0J0ylbIiUnxWGvwRM=; b=ofc0cg3BFe1pF6By4+49gWw9uUSOIIjKIFTMovMgTOjlgI3aZSd7MjdOAFjBaUkkbWGYq6ruJeWDI39cPrU/JBzoYtgqQkB306NwxfThpTOqSjgJuCrchvB1LRoBS/O7tUVJgc08IYUQWPvHWadudGf/kKhTQzSxqtk/48jYWwE= Received: from SJ0PR05CA0068.namprd05.prod.outlook.com (2603:10b6:a03:332::13) by PH7PR12MB8054.namprd12.prod.outlook.com (2603:10b6:510:27f::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.14; Wed, 20 May 2026 09:37:06 +0000 Received: from CO1PEPF000075ED.namprd03.prod.outlook.com (2603:10b6:a03:332:cafe::39) by SJ0PR05CA0068.outlook.office365.com (2603:10b6:a03:332::13) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.13 via Frontend Transport; Wed, 20 May 2026 09:37:04 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by CO1PEPF000075ED.mail.protection.outlook.com (10.167.249.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Wed, 20 May 2026 09:37:04 +0000 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Wed, 20 May 2026 04:37:01 -0500 Received: from xsjarunbala52.xilinx.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Wed, 20 May 2026 04:37:00 -0500 From: Ronak Jain To: , CC: , , Subject: [PATCH v2 2/2] firmware: zynqmp: Add dynamic CSU register discovery and sysfs interface Date: Wed, 20 May 2026 02:36:54 -0700 Message-ID: <20260520093654.3303917-3-ronak.jain@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260520093654.3303917-1-ronak.jain@amd.com> References: <20260520093654.3303917-1-ronak.jain@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075ED:EE_|PH7PR12MB8054:EE_ X-MS-Office365-Filtering-Correlation-Id: da0205b4-52b4-47d8-d0a4-08deb6535a22 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700016|82310400026|56012099003|18002099003|22082099003|3023799007|11063799006; X-Microsoft-Antispam-Message-Info: cdxKKP6Rn0xUdZBpZhMO80/Ul0yp20fbiKxAujqhu8dbEAArYFFT40jXTLqhKUZ1wr8pafEcvsrulpmplDfi8TT5Mgr7uP0pAvUxceLRAyJzaT4NqxZuwtcNW4blWY0AXdSoBcMrJZJMSX3mEwTrBrMUldNirywuV+aqeeEnqyhe4LLTbYzzNZe8P6njSdOFEwiEqApoaNXip1lY8yvN48auxt8TLId/vd70j/cEa3GZs5a8KMGspZtwYiBlSB304Ja08RO0rAJA54riliC4yWRfs7HpZgrSiBSsxPP4U6P6ohEUX00NdsSiXST22s4at8Z68QFHRWNBp2rOCNsuy1QDNQdf/RQFCoBzMwYmSaRGctTRnkD1IcooYH+wDDznpYq6J0LJcoDzCzw3jaiYiagjqTlS9H1WrrZrSl9iyriebExghpTVDaxFIeO6CXVujrGp/+6pmqK/B1rYyd+kP5RVLHbpmLiXy0AzBIFgFTeHuHN6SgrAP7G5Zrlz6GbvIHT9YVdnzoRZQTRGbPHcw/EuPL5QRDRrFLBxr6FoxifSJMow3BeFbBUrv0GBSAGtxL3UQ0JXFfp3f5U3h7LKBszDOBS83bOUxlCwQJ7J2wuZdJfCJpGCxIXXVhL5sKZEiT7SyV5ZrTQM5wCDUyJqndjEkshBYKUds/j+3zyHA8NoFl/EduPctdz7rrhPunxQjyxn5EtwGrLWQOHtGaLUHMwmvwawAgkZiWmLNpxU8kg= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700016)(82310400026)(56012099003)(18002099003)(22082099003)(3023799007)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: S8DUnKdf0wiRxQCAFIlTm+VTvjA2/10wtj1PP0jWiPNj96wQWbXEMCYiDX6jmMKevBzc84MJNdYGAYf92w5bBRHUmytl4zqDef80DqqbcKBd1UR2wtDKG5M3E9dVYMEt2J2kNwOUYRy6ykP4l4fMk3P3eXcbPXRH61V45Rdi0LpPZ/SCqoq/2rCtxiVKOPwjL+dAJjepOds692+DgN1rwX3AE/uURKmGZfqbmD+P/o/Lc/OHKPwWEJtfeLSl5kxS3GNZ2YFouqLD/LcfRKCh6xt8W56oM3cI/YwfB4/rYAoIO0BmOfVd+suM3LY7LQOOIn7cMsoyJH121LgJpTs992J7oxdfFYikYhra9wi5fbSHH4XbCzfSFJxL/MDbguzLhZ+opF2bW2aNs5J/O1EwHSefx61ddITb9s7Q4v/3+JDS/G32ecdR4lRy0jxCPnrT X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 May 2026 09:37:04.2617 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da0205b4-52b4-47d8-d0a4-08deb6535a22 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075ED.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8054 Content-Type: text/plain; charset="utf-8" Add support for dynamically discovering and exposing Configuration Security Unit (CSU) registers through sysfs. Leverage the existing PM_QUERY_DATA API to discover available registers at runtime, making the interface flexible and maintainable. Key features: - Dynamic register discovery using PM_QUERY_DATA API * PM_QID_GET_NODE_COUNT: Query number of available registers * PM_QID_GET_NODE_NAME: Query register names by index - Automatic sysfs attribute creation under csu_registers/ group - Read operations via existing IOCTL_READ_REG API - Write operations via existing IOCTL_MASK_WRITE_REG API The sysfs interface is created at: /sys/devices/platform/firmware:zynqmp-firmware/csu_registers/ Currently supported registers include: - multiboot (CSU_MULTI_BOOT) - idcode (CSU_IDCODE, read-only) - pcap-status (CSU_PCAP_STATUS, read-only) The dynamic discovery approach allows firmware to control which registers are exposed without requiring kernel changes, improving maintainability and security. The firmware does not currently expose per-register access mode information, so the kernel cannot distinguish read-only registers from read-write ones at discovery time. All discovered registers are therefore created with sysfs mode 0644, and the firmware is responsible for rejecting writes to registers it treats as read-only (for example idcode and pcap-status); that error is propagated back to userspace from the store callback. If a per-register access-mode query is added to the firmware in the future, sysfs permissions can be tightened to match. CSU register discovery is an optional feature: on firmware that lacks support for PM_QID_GET_NODE_COUNT or PM_QID_GET_NODE_NAME, the probe returns gracefully without exposing any sysfs entries. To keep the memory footprint minimal on that path, partial devm allocations made during discovery are explicitly released on failure so that no memory lingers until device unbind when the feature is unavailable. Signed-off-by: Ronak Jain --- MAINTAINERS | 10 + drivers/firmware/xilinx/Makefile | 2 +- drivers/firmware/xilinx/zynqmp-csu-reg.c | 258 +++++++++++++++++++++++ drivers/firmware/xilinx/zynqmp-csu-reg.h | 18 ++ drivers/firmware/xilinx/zynqmp.c | 6 + include/linux/firmware/xlnx-zynqmp.h | 4 +- 6 files changed, 296 insertions(+), 2 deletions(-) create mode 100644 drivers/firmware/xilinx/zynqmp-csu-reg.c create mode 100644 drivers/firmware/xilinx/zynqmp-csu-reg.h diff --git a/MAINTAINERS b/MAINTAINERS index b3e05a3186aa..f1b42935b40d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -29490,6 +29490,16 @@ F: drivers/dma/xilinx/xdma.c F: include/linux/dma/amd_xdma.h F: include/linux/platform_data/amd_xdma.h =20 +XILINX ZYNQMP CSU REGISTER DRIVER +M: Senthil Nathan Thangaraj +R: Michal Simek +R: Ronak Jain +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: Documentation/ABI/stable/sysfs-driver-firmware-zynqmp +F: drivers/firmware/xilinx/zynqmp-csu-reg.c +F: drivers/firmware/xilinx/zynqmp-csu-reg.h + XILINX ZYNQMP DPDMA DRIVER M: Laurent Pinchart L: dmaengine@vger.kernel.org diff --git a/drivers/firmware/xilinx/Makefile b/drivers/firmware/xilinx/Mak= efile index 8db0e66b6b7e..6203f41daaa6 100644 --- a/drivers/firmware/xilinx/Makefile +++ b/drivers/firmware/xilinx/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 # Makefile for Xilinx firmwares =20 -obj-$(CONFIG_ZYNQMP_FIRMWARE) +=3D zynqmp.o zynqmp-ufs.o zynqmp-crypto.o +obj-$(CONFIG_ZYNQMP_FIRMWARE) +=3D zynqmp.o zynqmp-ufs.o zynqmp-crypto.o z= ynqmp-csu-reg.o obj-$(CONFIG_ZYNQMP_FIRMWARE_DEBUG) +=3D zynqmp-debug.o diff --git a/drivers/firmware/xilinx/zynqmp-csu-reg.c b/drivers/firmware/xi= linx/zynqmp-csu-reg.c new file mode 100644 index 000000000000..6e11a9b019f7 --- /dev/null +++ b/drivers/firmware/xilinx/zynqmp-csu-reg.c @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Zynq MPSoC CSU Register Access + * + * Copyright (C) 2026 Advanced Micro Devices, Inc. + * + * Michal Simek + * Ronak Jain + */ + +#include +#include +#include +#include + +#include "zynqmp-csu-reg.h" + +/* Node ID for CSU module in firmware */ +#define CSU_NODE_ID 0 + +/* Maximum number of CSU registers supported */ +#define MAX_CSU_REGS 50 + +/* Size of register name returned by firmware (3 u32 words =3D 12 bytes) */ +#define CSU_REG_NAME_LEN 12 + +/** + * struct zynqmp_csu_reg - CSU register information + * @id: Register index from firmware + * @name: Register name + * @attr: Device attribute for sysfs + */ +struct zynqmp_csu_reg { + u32 id; + char name[CSU_REG_NAME_LEN]; + struct device_attribute attr; +}; + +/** + * struct zynqmp_csu_data - Per-device CSU data + * @csu_regs: Array of CSU registers + * @csu_attr_group: Attribute group for sysfs + */ +struct zynqmp_csu_data { + struct zynqmp_csu_reg *csu_regs; + struct attribute_group csu_attr_group; +}; + +/** + * zynqmp_pm_get_node_count() - Get number of supported nodes via QUERY_DA= TA + * + * Return: Number of nodes on success, or negative error code + */ +static int zynqmp_pm_get_node_count(void) +{ + struct zynqmp_pm_query_data qdata =3D {0}; + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + qdata.qid =3D PM_QID_GET_NODE_COUNT; + + ret =3D zynqmp_pm_query_data(qdata, ret_payload); + if (ret) + return ret; + + return ret_payload[1]; +} + +/** + * zynqmp_pm_get_node_name() - Get node name via QUERY_DATA + * @index: Register index + * @name: Buffer to store register name + * + * Return: 0 on success, error code otherwise + */ +static int zynqmp_pm_get_node_name(u32 index, char *name) +{ + struct zynqmp_pm_query_data qdata =3D {0}; + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + qdata.qid =3D PM_QID_GET_NODE_NAME; + qdata.arg1 =3D index; + + ret =3D zynqmp_pm_query_data(qdata, ret_payload); + if (ret) + return ret; + + memcpy(name, &ret_payload[1], CSU_REG_NAME_LEN); + name[CSU_REG_NAME_LEN - 1] =3D '\0'; + + return 0; +} + +/** + * zynqmp_csu_reg_show() - Generic show function for all registers + * @dev: Device pointer + * @attr: Device attribute + * @buf: Output buffer + * + * Return: Number of bytes written to buffer, or error code + */ +static ssize_t zynqmp_csu_reg_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct zynqmp_csu_reg *reg; + u32 value; + int ret; + + /* Use container_of to get register directly */ + reg =3D container_of(attr, struct zynqmp_csu_reg, attr); + + ret =3D zynqmp_pm_sec_read_reg(CSU_NODE_ID, reg->id, &value); + if (ret) + return ret; + + return sysfs_emit(buf, "0x%08x\n", value); +} + +/** + * zynqmp_csu_reg_store() - Generic store function for writable registers + * @dev: Device pointer + * @attr: Device attribute + * @buf: Input buffer + * @count: Buffer size + * + * Format: "mask value" - both mask and value required + * Example: echo "0xFFFFFFFF 0x12345678" > register + * + * Return: count on success, error code otherwise + */ +static ssize_t zynqmp_csu_reg_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct zynqmp_csu_reg *reg; + u32 mask, value; + int ret; + + reg =3D container_of(attr, struct zynqmp_csu_reg, attr); + + if (sscanf(buf, "%x %x", &mask, &value) !=3D 2) + return -EINVAL; + + ret =3D zynqmp_pm_sec_mask_write_reg(CSU_NODE_ID, reg->id, mask, value); + if (ret) + return ret; + + return count; +} + +/** + * zynqmp_csu_discover_registers() - Discover CSU registers from firmware + * @pdev: Platform device pointer + * + * This function uses PM_QUERY_DATA to discover all available CSU registers + * and creates sysfs group under /sys/devices/platform/firmware:zynqmp-fir= mware/ + * + * Return: 0 on success, error code otherwise + */ +int zynqmp_csu_discover_registers(struct platform_device *pdev) +{ + struct zynqmp_csu_data *csu_data; + struct attribute **attrs; + int count, ret, i; + + ret =3D zynqmp_pm_is_function_supported(PM_QUERY_DATA, PM_QID_GET_NODE_CO= UNT); + if (ret) { + dev_dbg(&pdev->dev, "CSU register discovery not supported by current fir= mware\n"); + return 0; + } + + ret =3D zynqmp_pm_is_function_supported(PM_QUERY_DATA, PM_QID_GET_NODE_NA= ME); + if (ret) { + dev_dbg(&pdev->dev, "CSU register name query not supported by current fi= rmware\n"); + return 0; + } + + count =3D zynqmp_pm_get_node_count(); + if (count < 0) + return count; + if (count =3D=3D 0) { + dev_dbg(&pdev->dev, "No nodes available from firmware\n"); + return 0; + } + + /* Validate count to prevent excessive memory allocation */ + if (count > MAX_CSU_REGS) { + dev_err(&pdev->dev, "Register count %d exceeds maximum %d\n", + count, MAX_CSU_REGS); + return -EINVAL; + } + + dev_dbg(&pdev->dev, "Discovered %d nodes from firmware\n", count); + + csu_data =3D devm_kzalloc(&pdev->dev, sizeof(*csu_data), GFP_KERNEL); + if (!csu_data) + return -ENOMEM; + + csu_data->csu_regs =3D devm_kcalloc(&pdev->dev, count, sizeof(*csu_data->= csu_regs), + GFP_KERNEL); + if (!csu_data->csu_regs) { + devm_kfree(&pdev->dev, csu_data); + return -ENOMEM; + } + + attrs =3D devm_kcalloc(&pdev->dev, count + 1, sizeof(*attrs), GFP_KERNEL); + if (!attrs) { + devm_kfree(&pdev->dev, csu_data->csu_regs); + devm_kfree(&pdev->dev, csu_data); + return -ENOMEM; + } + + for (i =3D 0; i < count; i++) { + struct zynqmp_csu_reg *reg =3D &csu_data->csu_regs[i]; + struct device_attribute *dev_attr =3D ®->attr; + + reg->id =3D i; + + ret =3D zynqmp_pm_get_node_name(i, reg->name); + if (ret) { + dev_warn(&pdev->dev, "Failed to get name for register %d\n", i); + snprintf(reg->name, sizeof(reg->name), "csu_reg_%d", i); + } + + /* + * The firmware does not expose per-register access mode via + * PM_QUERY_DATA today, so the kernel cannot tell read-only + * registers from read-write ones at discovery time. Expose + * every register as 0644 and rely on the firmware to reject + * IOCTL_MASK_WRITE_REG on read-only registers; the error is + * propagated back to userspace from the store callback. + */ + sysfs_attr_init(&dev_attr->attr); + dev_attr->attr.name =3D reg->name; + dev_attr->attr.mode =3D 0644; + dev_attr->show =3D zynqmp_csu_reg_show; + dev_attr->store =3D zynqmp_csu_reg_store; + + attrs[i] =3D &dev_attr->attr; + + dev_dbg(&pdev->dev, "Register %d: id=3D%d name=3D%s\n", i, reg->id, reg-= >name); + } + + csu_data->csu_attr_group.name =3D "csu_registers"; + csu_data->csu_attr_group.attrs =3D attrs; + + ret =3D devm_device_add_group(&pdev->dev, &csu_data->csu_attr_group); + if (ret) { + devm_kfree(&pdev->dev, attrs); + devm_kfree(&pdev->dev, csu_data->csu_regs); + devm_kfree(&pdev->dev, csu_data); + } + + return ret; +} +EXPORT_SYMBOL_GPL(zynqmp_csu_discover_registers); diff --git a/drivers/firmware/xilinx/zynqmp-csu-reg.h b/drivers/firmware/xi= linx/zynqmp-csu-reg.h new file mode 100644 index 000000000000..b12415db3496 --- /dev/null +++ b/drivers/firmware/xilinx/zynqmp-csu-reg.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Xilinx Zynq MPSoC CSU Register Access + * + * Copyright (C) 2026 Advanced Micro Devices, Inc. + * + * Michal Simek + * Ronak Jain + */ + +#ifndef __ZYNQMP_CSU_REG_H__ +#define __ZYNQMP_CSU_REG_H__ + +#include + +int zynqmp_csu_discover_registers(struct platform_device *pdev); + +#endif /* __ZYNQMP_CSU_REG_H__ */ diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zyn= qmp.c index af838b2dc327..155a7a9b3777 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -27,6 +27,7 @@ =20 #include #include +#include "zynqmp-csu-reg.h" #include "zynqmp-debug.h" =20 /* Max HashMap Order for PM API feature check (1<<7 =3D 128) */ @@ -2148,6 +2149,11 @@ static int zynqmp_firmware_probe(struct platform_dev= ice *pdev) dev_err_probe(&pdev->dev, PTR_ERR(em_dev), "EM register fail with error= \n"); } =20 + /* Discover CSU registers dynamically */ + ret =3D zynqmp_csu_discover_registers(pdev); + if (ret) + dev_warn(&pdev->dev, "CSU register discovery failed: %d\n", ret); + return of_platform_populate(dev->of_node, NULL, NULL, dev); } =20 diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/= xlnx-zynqmp.h index 7e27b0f7bf7e..a956e315be82 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -3,7 +3,7 @@ * Xilinx Zynq MPSoC Firmware layer * * Copyright (C) 2014-2021 Xilinx - * Copyright (C) 2022 - 2025 Advanced Micro Devices, Inc. + * Copyright (C) 2022 - 2026 Advanced Micro Devices, Inc. * * Michal Simek * Davorin Mista @@ -262,6 +262,8 @@ enum pm_query_id { PM_QID_CLOCK_GET_NUM_CLOCKS =3D 12, PM_QID_CLOCK_GET_MAX_DIVISOR =3D 13, PM_QID_PINCTRL_GET_ATTRIBUTES =3D 15, + PM_QID_GET_NODE_NAME =3D 16, + PM_QID_GET_NODE_COUNT =3D 17, }; =20 enum rpu_oper_mode { --=20 2.34.1