From nobody Mon May 25 01:14:41 2026 Received: from mail-pj1-f51.google.com (mail-pj1-f51.google.com [209.85.216.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CB8F301474 for ; Wed, 20 May 2026 02:51:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779245515; cv=none; b=jzGtN4GV4q/B5BjsD82yylW9xHQ8Do9fHQq0/qsm7gONGcJT0CvyCR+bUbePyVtqybBpWRaBOaaf9REuOSpg7UAa18BHh6r0NB2sIiiecSfb/f2Tnr67SOXk0RKfwLkS4b41Sued24Wfk0XefHn5zdi8PPDfLb7ZxtM/ZYgTppU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779245515; c=relaxed/simple; bh=IfW1mk1oO65qfqGh1XWmKHmZoIBL9vQ6FHuE2MESpaM=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=lfgRc9QiU5mRZV8brAmCZadQtbq98aDKL0fJifucIHhtTnmOmyosIgJ8JqM5iHLxJD8uL30XCeFUBktvTB8w3z2mzBl5Sozrw6pwFN75ob+N1fnZM/pXmHuk0MMUTijI7h4yjW73vJAmneZieRLEQpbdLWAiQWJxVVCiqNLXsPo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=HY4atRlT; arc=none smtp.client-ip=209.85.216.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="HY4atRlT" Received: by mail-pj1-f51.google.com with SMTP id 98e67ed59e1d1-365eecc5885so3963241a91.0 for ; Tue, 19 May 2026 19:51:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779245513; x=1779850313; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=Jx43HXyXFoFdaLMUvboXe6TnzGo/7OAUQHqaJ3dkRtk=; b=HY4atRlTShWO9Nn4DbMBDCbKUe/Dq7YugjKhWI9HrqZ1KkSo5PhuelF3ZoNMaVwjqp yiZwwqZ5kpUyk45a3IWvTpPUJk3IMZ4wd3RtzNZPAO0MKx2k0c8hc165mPvh3TMD56Z4 KUUaHvLnc3bPOHfiKIP2GMi+iodNt03NwFBcYe3KmaYSj5YrRTsBNFdaHa7ySLNmqnQQ uU3dy5KkAhJbcieBtuNyueXUrVCBDTASWSAIsZ7KWmV0XOtSY2BSvBHi0mjM8B0ibWJG fuph15BkPVrkCnQQScBCDYaJbK2ixrkAmq3N+NiwEnVjLmPwEhuBNLZRtAc4MFkF+9/P dlHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779245513; x=1779850313; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=Jx43HXyXFoFdaLMUvboXe6TnzGo/7OAUQHqaJ3dkRtk=; b=aNP8qu8PHrFnWfDwOGh5MZqMB7YuK8hS0xJsyHejjpT9VBfKfNTO7+39Ny7TJSOg0c kWqQy0Nax5xWOysUZaCcK93HRRvKEXlAXhQ/BzUGDIsnhbTo+WM8eA7YgsM1zCrhPoHP 6ojoyx7uYtGsopKkAXe0yucJzwck6yOQAwUmNWxyQF0DPWxUMA8NzQ10r7P/hEPiFyhQ H6NF5Hjly1dfZwypXuCMHYhQv+r/Xdg9ZsWNwQ7pA24FnZeoAAL2XKH3XAzc227cQCeM tjebIj30ntJB/4+ADC85GAEDl1Whjn/V8Y9GZ/GVyC8IloVUaC0COGqUcUuqxLxF3twZ NEoQ== X-Forwarded-Encrypted: i=1; AFNElJ98OY2rzhonRWN+wN6oqpgtTaOWPkLqUoz75nUJ6TM8gL5UDZzmGNQ3Dbn1hObqkwtsQEDQUG/uWqLKFLs=@vger.kernel.org X-Gm-Message-State: AOJu0Yyh59beJgbrDX29CgDNjI8D2lXdHPN6GRmkSSaClhZLFRMTT5zZ JfKv7OtnTzwevi2DHXmpL9S81rDMxOl0/dUmsdAMozBoCESp9VMW70D1 X-Gm-Gg: Acq92OHEtvvjqtb29NgpNLaOZuwFBEjxENckvfcryDP9OPKuu4YEHEnIFJlZBEx44mP ewLdnWtDkLvDn5EneAbmtB5I8HMrBNRvY4bEZZyHLnBOegxzzprx9CifGM6jjh473GvE//KzXfL c4N/vzLG++KYYzHURPh704W1UVY/0wwAlmb1c1cuZSs1Eq7rDYIwM1cwaHQMih6GtHoEEYjz+sL PANqGy7UwGAyRTg2huDFWKO5ek7IcBmE7q01wTLcdA9sB1lSZEYhrHF+PYBeQvnMsLcAedq8Xq1 Z0IGcNszpqrvNEcXEhQK6kb7K/452UUBWw9I0f1myofnb+EPr/mhYZ2uKRWBZdw/JFWvMJtmlUs BfQnbjw1v+WXPMBztsiFInqJaxePmjrkQx9a4FH1Z9EOYDVhqmFQKQHEnZHrsYX2yHJ9AYvUfMj R2CKBdlZ7M18q1MZSc5ltI8QnfhhBx/VzNUX7hio3rLZqj09IQ X-Received: by 2002:a17:903:1b4e:b0:2b0:c59f:3b58 with SMTP id d9443c01a7336-2bd7e7b58a8mr239228905ad.9.1779245513328; Tue, 19 May 2026 19:51:53 -0700 (PDT) Received: from ultimate.. ([58.84.62.111]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bd5cfe7270sm198267065ad.50.2026.05.19.19.51.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 May 2026 19:51:52 -0700 (PDT) From: Udaya Kiran Challa To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: skhan@linuxfoundation.org, me@brighamcampbell.com, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Udaya Kiran Challa Subject: [PATCH] dt-bindings: clock: via,vt8500: Convert to DT Schema Date: Wed, 20 May 2026 08:18:53 +0530 Message-ID: <20260520025131.17772-1-challauday369@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the VIA/Wondermedia VT8500 and Wondermedia WM8xxx series SoCs clock controller binding from the legacy text format to DT schema. Signed-off-by: Udaya Kiran Challa --- .../bindings/clock/via,vt8500-clock.yaml | 122 ++++++++++++++++++ .../devicetree/bindings/clock/vt8500.txt | 74 ----------- 2 files changed, 122 insertions(+), 74 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/via,vt8500-cloc= k.yaml delete mode 100644 Documentation/devicetree/bindings/clock/vt8500.txt diff --git a/Documentation/devicetree/bindings/clock/via,vt8500-clock.yaml = b/Documentation/devicetree/bindings/clock/via,vt8500-clock.yaml new file mode 100644 index 000000000000..9c312d11a6a7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/via,vt8500-clock.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/via,vt8500-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: VIA/Wondermedia VT8500 Clock Controller + +maintainers: + - Michael Turquette + - Stephen Boyd + +description: | + Clock controller bindings for VIA/Wondermedia VT8500 and Wondermedia WM8= xxx + series SoCs. + +properties: + compatible: + enum: + - via,vt8500-pll-clock + - wm,wm8650-pll-clock + - wm,wm8750-pll-clock + - wm,wm8850-pll-clock + - via,vt8500-device-clock + + reg: + maxItems: 1 + description: + Offset of the PLL register within the PMC register space. + + clocks: + maxItems: 1 + description: + Parent reference clock. + + "#clock-cells": + const: 0 + + enable-reg: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Offset of the clock enable register within the PMC register space. + + enable-bit: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 31 + description: + Bit index controlling clock enable. + + divisor-reg: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Offset of the clock divisor register within the PMC register space. + + divisor-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Bitmask describing the divisor field inside divisor-reg. + +required: + - compatible + - "#clock-cells" + +allOf: + - if: + properties: + compatible: + enum: + - via,vt8500-pll-clock + - wm,wm8650-pll-clock + - wm,wm8750-pll-clock + - wm,wm8850-pll-clock + then: + required: + - reg + - clocks + + - if: + properties: + compatible: + const: via,vt8500-device-clock + then: + required: + - clocks + anyOf: + - required: + - enable-reg + - enable-bit + - required: + - divisor-reg + +additionalProperties: false + +examples: + - | + / { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ref25: ref25M { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <25000000>; + }; + + plla: clock@200 { + compatible =3D "wm,wm8650-pll-clock"; + reg =3D <0x200>; + clocks =3D <&ref25>; + #clock-cells =3D <0>; + }; + + clksdhc: clock { + compatible =3D "via,vt8500-device-clock"; + clocks =3D <&plla>; + divisor-reg =3D <0x328>; + divisor-mask =3D <0x3f>; + enable-reg =3D <0x254>; + enable-bit =3D <18>; + #clock-cells =3D <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/vt8500.txt b/Documenta= tion/devicetree/bindings/clock/vt8500.txt deleted file mode 100644 index 91d71cc0314a..000000000000 --- a/Documentation/devicetree/bindings/clock/vt8500.txt +++ /dev/null @@ -1,74 +0,0 @@ -Device Tree Clock bindings for arch-vt8500 - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock - "wm,wm8650-pll-clock" - for a WM8650 PLL clock - "wm,wm8750-pll-clock" - for a WM8750 PLL clock - "wm,wm8850-pll-clock" - for a WM8850 PLL clock - "via,vt8500-device-clock" - for a VT/WM device clock - -Required properties for PLL clocks: -- reg : shall be the control register offset from PMC base for the pll clo= ck. -- clocks : shall be the input parent clock phandle for the clock. This sho= uld - be the reference clock. -- #clock-cells : from common clock binding; shall be set to 0. - -Required properties for device clocks: -- clocks : shall be the input parent clock phandle for the clock. This sho= uld - be a pll output. -- #clock-cells : from common clock binding; shall be set to 0. - - -Device Clocks - -Device clocks are required to have one or both of the following sets of -properties: - - -Gated device clocks: - -Required properties: -- enable-reg : shall be the register offset from PMC base for the enable - register. -- enable-bit : shall be the bit within enable-reg to enable/disable the cl= ock. - - -Divisor device clocks: - -Required property: -- divisor-reg : shall be the register offset from PMC base for the divisor - register. -Optional property: -- divisor-mask : shall be the mask for the divisor register. Defaults to 0= x1f - if not specified. - - -For example: - -ref25: ref25M { - #clock-cells =3D <0>; - compatible =3D "fixed-clock"; - clock-frequency =3D <25000000>; -}; - -plla: plla { - #clock-cells =3D <0>; - compatible =3D "wm,wm8650-pll-clock"; - clocks =3D <&ref25>; - reg =3D <0x200>; -}; - -sdhc: sdhc { - #clock-cells =3D <0>; - compatible =3D "via,vt8500-device-clock"; - clocks =3D <&pllb>; - divisor-reg =3D <0x328>; - divisor-mask =3D <0x3f>; - enable-reg =3D <0x254>; - enable-bit =3D <18>; -}; --=20 2.43.0