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Tue, 19 May 2026 09:08:43 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Biju Das , Laurent Pinchart , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Tommaso Merciai , Lad Prabhakar Subject: [PATCH v4 1/5] dt-bindings: display: renesas,rzg2l-du: Refuse port@1 for RZ/G2UL Date: Tue, 19 May 2026 17:08:21 +0100 Message-ID: <20260519160825.4082566-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260519160825.4082566-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260519160825.4082566-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tommaso Merciai The RZ/G2UL DU supports only a single port@0 DPI. Explicitly refuse port@1 in the ports node. Reviewed-by: Laurent Pinchart Acked-by: Rob Herring (Arm) Signed-off-by: Tommaso Merciai Signed-off-by: Lad Prabhakar --- v3->v4: - Added Acked-by tag from Rob. v3: - Was orignally part of separate series [0] [0] https://lore.kernel.org/all/d1e0d4e0fe74e60345a3d043fb4f9128c1057638.17= 78141145.git.tommaso.merciai.xr@bp.renesas.com/ --- Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yam= l b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml index 2cc66dcef870..5add3b832eab 100644 --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml @@ -102,6 +102,7 @@ allOf: properties: port@0: description: DPI + port@1: false =20 required: - port@0 --=20 2.54.0 From nobody Mon May 25 02:05:01 2026 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0C163FB042 for ; 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Tue, 19 May 2026 09:08:45 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:3f5e:825d:a98f:fd29]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48fe5ab527asm372645305e9.11.2026.05.19.09.08.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 May 2026 09:08:44 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Biju Das , Laurent Pinchart , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v4 2/5] dt-bindings: display: renesas,rzg2l-du: Add RZ/T2H and RZ/N2H support Date: Tue, 19 May 2026 17:08:22 +0100 Message-ID: <20260519160825.4082566-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260519160825.4082566-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260519160825.4082566-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Document the Display Unit (DU) support for the RZ/T2H and RZ/N2H SoCs. The DU block on RZ/T2H is functionally equivalent to the RZ/G2UL DU and supports the DPI interface, but includes SoC-specific register differences and has no reset control. Add a dedicated compatible string to represent this variant and update the allOf constraints accordingly. As the DU implementation on RZ/N2H matches RZ/T2H, describe it using an RZ/N2H specific compatible string with the RZ/T2H compatible as fallback. Signed-off-by: Lad Prabhakar Reviewed-by: Rob Herring (Arm) --- v3->v4: - Added RB tag from Rob. v2->v3: - No change v1->v2: - Dropped the "port" property in favor of "ports" with a single port@0 child, to align with the existing RZ/G2L bindings and simplify the device tree structure. - Updated the commit message to reflect the change from "port" to "ports". - Dropped RB tag from Rob due to above changes. --- .../bindings/display/renesas,rzg2l-du.yaml | 20 +++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yam= l b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml index 5add3b832eab..7c84a9ecc7a7 100644 --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml @@ -21,6 +21,7 @@ properties: - renesas,r9a07g043u-du # RZ/G2UL - renesas,r9a07g044-du # RZ/G2{L,LC} - renesas,r9a09g057-du # RZ/V2H(P) + - renesas,r9a09g077-du # RZ/T2H - items: - enum: - renesas,r9a07g054-du # RZ/V2L @@ -28,6 +29,9 @@ properties: - items: - const: renesas,r9a09g056-du # RZ/V2N - const: renesas,r9a09g057-du # RZ/V2H(P) fallback + - items: + - const: renesas,r9a09g087-du # RZ/N2H + - const: renesas,r9a09g077-du # RZ/T2H fallback =20 reg: maxItems: 1 @@ -83,7 +87,6 @@ required: - interrupts - clocks - clock-names - - resets - power-domains - ports - renesas,vsps @@ -95,7 +98,9 @@ allOf: properties: compatible: contains: - const: renesas,r9a07g043u-du + enum: + - renesas,r9a07g043u-du + - renesas,r9a09g077-du then: properties: ports: @@ -138,6 +143,17 @@ allOf: =20 required: - port@0 + - if: + properties: + compatible: + contains: + const: renesas,r9a09g077-du + then: + properties: + resets: false + else: + required: + - resets =20 examples: # RZ/G2L DU --=20 2.54.0 From nobody Mon May 25 02:05:01 2026 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E81D634040E for ; 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Tue, 19 May 2026 09:08:46 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:3f5e:825d:a98f:fd29]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48fe5ab527asm372645305e9.11.2026.05.19.09.08.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 May 2026 09:08:45 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Biju Das , Laurent Pinchart , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v4 3/5] drm: renesas: rz-du: Make DU reset control optional for RZ/T2H support Date: Tue, 19 May 2026 17:08:23 +0100 Message-ID: <20260519160825.4082566-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260519160825.4082566-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260519160825.4082566-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Update the DU CRTC initialisation to request the reset control using devm_reset_control_get_optional_shared(). On RZ/T2H SoCs the DU block does not expose a reset line, and treating the reset as mandatory prevents the driver from probing on those platforms. Signed-off-by: Lad Prabhakar Reviewed-by: Laurent Pinchart --- v2->v4: - No change v1->v2: - Added Reviewed-by tag from Laurent Pinchart. --- drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c b/drivers/gpu/dr= m/renesas/rz-du/rzg2l_du_crtc.c index 26b95153ce88..48065f4952a3 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c @@ -380,7 +380,7 @@ int rzg2l_du_crtc_create(struct rzg2l_du_device *rcdu) struct drm_plane *primary; int ret; =20 - rcrtc->rstc =3D devm_reset_control_get_shared(rcdu->dev, NULL); + rcrtc->rstc =3D devm_reset_control_get_optional_shared(rcdu->dev, NULL); if (IS_ERR(rcrtc->rstc)) { dev_err(rcdu->dev, "can't get cpg reset\n"); return PTR_ERR(rcrtc->rstc); --=20 2.54.0 From nobody Mon May 25 02:05:01 2026 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B28D403EA9 for ; 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Tue, 19 May 2026 09:08:47 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:3f5e:825d:a98f:fd29]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48fe5ab527asm372645305e9.11.2026.05.19.09.08.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 May 2026 09:08:46 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Biju Das , Laurent Pinchart , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v4 4/5] drm: renesas: rz-du: Move mode_valid logic to per-SoC clock limits Date: Tue, 19 May 2026 17:08:24 +0100 Message-ID: <20260519160825.4082566-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260519160825.4082566-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260519160825.4082566-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Move pixel clock validation from a fixed encoder check to per SoC constraints stored in rzg2l_du_device_info. Pixel clock limits differ across SoCs in the RZ DU family and cannot be expressed by a single shared rule. For example, RZ/G2UL and RZ/G2L limit the DPAD0 pixel clock to a narrow window, while other SoCs such as RZ/T2H require a wider operating range. Add mode_clock_min and mode_clock_max fields to rzg2l_du_device_info to describe the supported pixel clock range for each SoC. Update rzg2l_du_encoder_mode_valid() to check these bounds when evaluating DPAD0 outputs, returning MODE_CLOCK_LOW when the pixel clock falls below mode_clock_min and MODE_CLOCK_HIGH when it exceeds mode_clock_max. Populate the pixel clock limits for both the RZ/G2UL (R9A07G043U) and RZ/G2L (R9A07G044) variants to a minimum of 20875 kHz and a maximum of 83500 kHz. Signed-off-by: Lad Prabhakar --- v3->v4: - Dropped per pad limits - Updated commit message to reflect the change in approach. v2->v3: - Moved clock limits from device_info to output_routing to allow per-output constraints. - Updated commit message to reflect the change in approach. v1->v2: - Dropped storing info pointer in struct rzg2l_du_encoder as it's not neede= d. --- drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 6 +++++- drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h | 4 ++++ drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c | 9 ++++++++- 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/drm= /renesas/rz-du/rzg2l_du_drv.c index 0fef33a5a089..1e4b9f38c55b 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c @@ -35,6 +35,8 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g0= 43u_info =3D { .port =3D 0, }, }, + .mode_clock_min =3D 20875, + .mode_clock_max =3D 83500, }; =20 static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info =3D { @@ -48,7 +50,9 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g0= 44_info =3D { .possible_outputs =3D BIT(0), .port =3D 1, } - } + }, + .mode_clock_min =3D 20875, + .mode_clock_max =3D 83500, }; =20 static const struct rzg2l_du_device_info rzg2l_du_r9a09g057_info =3D { diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h b/drivers/gpu/drm= /renesas/rz-du/rzg2l_du_drv.h index 58806c2a8f2b..885558eb9547 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h @@ -44,10 +44,14 @@ struct rzg2l_du_output_routing { * struct rzg2l_du_device_info - DU model-specific information * @channels_mask: bit mask of available DU channels * @routes: array of CRTC to output routes, indexed by output (RZG2L_DU_OU= TPUT_*) + * @mode_clock_min: minimum pixel clock in kHz + * @mode_clock_max: maximum pixel clock in kHz */ struct rzg2l_du_device_info { unsigned int channels_mask; struct rzg2l_du_output_routing routes[RZG2L_DU_OUTPUT_MAX]; + u32 mode_clock_min; + u32 mode_clock_max; }; =20 #define RZG2L_DU_MAX_CRTCS 1 diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c b/drivers/gpu= /drm/renesas/rz-du/rzg2l_du_encoder.c index 0e567b57a408..56220139a149 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c @@ -50,8 +50,15 @@ rzg2l_du_encoder_mode_valid(struct drm_encoder *encoder, const struct drm_display_mode *mode) { struct rzg2l_du_encoder *renc =3D to_rzg2l_encoder(encoder); + struct rzg2l_du_device *rcdu =3D to_rzg2l_du_device(renc->base.dev); + const struct rzg2l_du_device_info *info =3D rcdu->info; =20 - if (renc->output =3D=3D RZG2L_DU_OUTPUT_DPAD0 && mode->clock > 83500) + if (renc->output !=3D RZG2L_DU_OUTPUT_DPAD0) + return MODE_OK; + + if (info->mode_clock_min && mode->clock < info->mode_clock_min) + return MODE_CLOCK_LOW; + if (info->mode_clock_max && mode->clock > info->mode_clock_max) return MODE_CLOCK_HIGH; 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Tue, 19 May 2026 09:08:47 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Biju Das , Laurent Pinchart , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v4 5/5] drm: renesas: rz-du: Add support for RZ/T2H SoC Date: Tue, 19 May 2026 17:08:25 +0100 Message-ID: <20260519160825.4082566-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260519160825.4082566-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260519160825.4082566-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar The RZ/T2H (R9A09G077) SoC includes a DU with a DPI interface, supporting resolutions up to WXGA with two RPFs for layer blending. Unlike earlier RZ/G2L SoCs, RZ/T2H requires explicit assertion of a DPI output-enable signal (DU_MCR0_DPI_EN) during CRTC startup. Signed-off-by: Lad Prabhakar Reviewed-by: Laurent Pinchart --- v3->v4: - Dropped per pad limits v2->v3: - Moved clock limits from device_info to output_routing to allow per-output constraints. v1->v2: - Added Reviewed-by tag from Laurent Pinchart. --- drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c | 7 ++++++- drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 14 ++++++++++++++ drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h | 10 ++++++++++ 3 files changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c b/drivers/gpu/dr= m/renesas/rz-du/rzg2l_du_crtc.c index 48065f4952a3..d0f01aa642a7 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c @@ -28,6 +28,7 @@ #include "rzg2l_du_vsp.h" =20 #define DU_MCR0 0x00 +#define DU_MCR0_DPI_EN BIT(0) #define DU_MCR0_DI_EN BIT(8) =20 #define DU_DITR0 0x10 @@ -217,8 +218,12 @@ static void rzg2l_du_crtc_put(struct rzg2l_du_crtc *rc= rtc) static void rzg2l_du_start_stop(struct rzg2l_du_crtc *rcrtc, bool start) { struct rzg2l_du_device *rcdu =3D rcrtc->dev; + u32 val =3D DU_MCR0_DI_EN; =20 - writel(start ? DU_MCR0_DI_EN : 0, rcdu->mmio + DU_MCR0); + if (start && rzg2l_du_has(rcdu, RZG2L_DU_FEATURE_DPIO_OE)) + val |=3D DU_MCR0_DPI_EN; + + writel(start ? val : 0, rcdu->mmio + DU_MCR0); } =20 static void rzg2l_du_crtc_start(struct rzg2l_du_crtc *rcrtc) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/drm= /renesas/rz-du/rzg2l_du_drv.c index 1e4b9f38c55b..3d13f61d3c97 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c @@ -65,10 +65,24 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a09= g057_info =3D { }, }; =20 +static const struct rzg2l_du_device_info rzg2l_du_r9a09g077_info =3D { + .channels_mask =3D BIT(0), + .routes =3D { + [RZG2L_DU_OUTPUT_DPAD0] =3D { + .possible_outputs =3D BIT(0), + .port =3D 0, + }, + }, + .features =3D RZG2L_DU_FEATURE_DPIO_OE, + .mode_clock_min =3D 5000, + .mode_clock_max =3D 100000, +}; + static const struct of_device_id rzg2l_du_of_table[] =3D { { .compatible =3D "renesas,r9a07g043u-du", .data =3D &rzg2l_du_r9a07g043u= _info }, { .compatible =3D "renesas,r9a07g044-du", .data =3D &rzg2l_du_r9a07g044_i= nfo }, { .compatible =3D "renesas,r9a09g057-du", .data =3D &rzg2l_du_r9a09g057_i= nfo }, + { .compatible =3D "renesas,r9a09g077-du", .data =3D &rzg2l_du_r9a09g077_i= nfo }, { /* sentinel */ } }; =20 diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h b/drivers/gpu/drm= /renesas/rz-du/rzg2l_du_drv.h index 885558eb9547..baf076d69cda 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h @@ -20,6 +20,8 @@ struct device; struct drm_property; =20 +#define RZG2L_DU_FEATURE_DPIO_OE BIT(0) /* Has DPIO output enable control = */ + enum rzg2l_du_output { RZG2L_DU_OUTPUT_DSI0, RZG2L_DU_OUTPUT_DPAD0, @@ -46,12 +48,14 @@ struct rzg2l_du_output_routing { * @routes: array of CRTC to output routes, indexed by output (RZG2L_DU_OU= TPUT_*) * @mode_clock_min: minimum pixel clock in kHz * @mode_clock_max: maximum pixel clock in kHz + * @features: device features (RZG2L_DU_FEATURE_*) */ struct rzg2l_du_device_info { unsigned int channels_mask; struct rzg2l_du_output_routing routes[RZG2L_DU_OUTPUT_MAX]; u32 mode_clock_min; u32 mode_clock_max; + unsigned int features; }; =20 #define RZG2L_DU_MAX_CRTCS 1 @@ -77,6 +81,12 @@ static inline struct rzg2l_du_device *to_rzg2l_du_device= (struct drm_device *dev) return container_of(dev, struct rzg2l_du_device, ddev); } =20 +static inline bool rzg2l_du_has(struct rzg2l_du_device *rcdu, + unsigned int feature) +{ + return rcdu->info->features & feature; +} + const char *rzg2l_du_output_name(enum rzg2l_du_output output); =20 #endif /* __RZG2L_DU_DRV_H__ */ --=20 2.54.0