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charset="utf-8" Threaded IRQ handlers suffer from scheduler latency on heavily loaded systems, causing false transfer timeouts. Convert to hard IRQ handler that schedules work on a high-priority unbound workqueue. The hard IRQ handler verifies the interrupt, caches FIFO status, clears and masks interrupts, then schedules bottom-half processing. The workqueue handler runs in process context (can sleep for DMA) and can execute on any CPU, avoiding CPU0 bottlenecks. Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra210-quad.c | 128 +++++++++++++++++++++----------- 1 file changed, 84 insertions(+), 44 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-qua= d.c index db28dd556484..17d0b511af1d 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -191,6 +191,8 @@ struct tegra_qspi { void __iomem *base; phys_addr_t phys; unsigned int irq; + struct work_struct irq_work; + struct workqueue_struct *wq; =20 u32 cur_speed; unsigned int cur_pos; @@ -1225,9 +1227,9 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_= qspi *tqspi, =20 if (ret =3D=3D 0) { /* - * Check if hardware completed the transfer - * even though interrupt was lost or delayed. - * If so, process the completion and continue. + * Check if hardware completed the transfer even though + * workqueue was delayed. If so, process completion and + * continue. */ ret =3D tegra_qspi_handle_timeout(tqspi); if (ret < 0) { @@ -1344,8 +1346,8 @@ static int tegra_qspi_non_combined_seq_xfer(struct te= gra_qspi *tqspi, if (ret =3D=3D 0) { /* * Check if hardware completed the transfer even though - * interrupt was lost or delayed. If so, process the - * completion and continue. + * workqueue was delayed. If so, process completion and + * continue. */ ret =3D tegra_qspi_handle_timeout(tqspi); if (ret < 0) { @@ -1574,46 +1576,40 @@ static irqreturn_t handle_dma_based_xfer(struct teg= ra_qspi *tqspi) return IRQ_HANDLED; } =20 -static irqreturn_t tegra_qspi_isr_thread(int irq, void *context_data) +/** + * tegra_qspi_work_handler - Workqueue handler for interrupt bottom-half + * @work: work_struct embedded in tegra_qspi + * + * Runs in process context and can sleep (needed for DMA completion waits). + * Can run on any available CPU, avoiding CPU0 bottleneck that occurs with + * threaded IRQ handlers which are pinned to the IRQ's CPU. + * + * The hard IRQ handler has already: + * - Verified this is our interrupt (QSPI_RDY was set) + * - Cached FIFO status in tqspi->status_reg + * - Parsed tx_status / rx_status from FIFO status + * - Masked further interrupts + */ +static void tegra_qspi_work_handler(struct work_struct *work) { - struct tegra_qspi *tqspi =3D context_data; + struct tegra_qspi *tqspi =3D container_of(work, struct tegra_qspi, irq_wo= rk); unsigned long flags; - u32 status; =20 - /* - * Read transfer status to check if interrupt was triggered by transfer - * completion - */ - status =3D tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS); + spin_lock_irqsave(&tqspi->lock, flags); =20 /* - * Occasionally the IRQ thread takes a long time to wake up (usually - * when the CPU that it's running on is excessively busy) and we have - * already reached the timeout before and cleaned up the timed out - * transfer. Avoid any processing in that case and bail out early. - * - * If no transfer is in progress, check if this was a real interrupt - * that the timeout handler already processed, or a spurious one. + * Check if timeout handler already processed this transfer. + * Can happen if work was delayed and timeout fired first. If + * so, we must unmask interrupts before returning, otherwise + * they remain masked from the hard IRQ handler and the next + * transfer will timeout. */ - spin_lock_irqsave(&tqspi->lock, flags); if (!tqspi->curr_xfer) { spin_unlock_irqrestore(&tqspi->lock, flags); - /* Spurious interrupt - transfer not ready */ - if (!(status & QSPI_RDY)) - return IRQ_NONE; - /* Real interrupt, already handled by timeout path */ - return IRQ_HANDLED; + tegra_qspi_unmask_irq(tqspi); + return; } =20 - tqspi->status_reg =3D tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS); - - if (tqspi->cur_direction & DATA_DIR_TX) - tqspi->tx_status =3D tqspi->status_reg & (QSPI_TX_FIFO_UNF | QSPI_TX_FIF= O_OVF); - - if (tqspi->cur_direction & DATA_DIR_RX) - tqspi->rx_status =3D tqspi->status_reg & (QSPI_RX_FIFO_OVF | QSPI_RX_FIF= O_UNF); - - tegra_qspi_mask_clear_irq(tqspi); spin_unlock_irqrestore(&tqspi->lock, flags); =20 /* @@ -1623,9 +1619,46 @@ static irqreturn_t tegra_qspi_isr_thread(int irq, vo= id *context_data) * cannot be done while holding spinlock. */ if (!tqspi->is_curr_dma_xfer) - return handle_cpu_based_xfer(tqspi); + handle_cpu_based_xfer(tqspi); + else + handle_dma_based_xfer(tqspi); +} + +/** + * tegra_qspi_isr - Hard IRQ handler + * @irq: IRQ number + * @context_data: QSPI controller instance + * + * Runs in hard IRQ context with minimal latency. Cannot sleep. + * + * Return: IRQ_NONE if not our interrupt, IRQ_HANDLED if handled + */ +static irqreturn_t tegra_qspi_isr(int irq, void *context_data) +{ + struct tegra_qspi *tqspi =3D context_data; + u32 status; + + status =3D tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS); + if (!(status & QSPI_RDY)) + return IRQ_NONE; + + spin_lock(&tqspi->lock); + tqspi->status_reg =3D tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS); + tegra_qspi_mask_clear_irq(tqspi); =20 - return handle_dma_based_xfer(tqspi); + if (tqspi->cur_direction & DATA_DIR_TX) + tqspi->tx_status =3D tqspi->status_reg & + (QSPI_TX_FIFO_UNF | QSPI_TX_FIFO_OVF); + + if (tqspi->cur_direction & DATA_DIR_RX) + tqspi->rx_status =3D tqspi->status_reg & + (QSPI_RX_FIFO_OVF | QSPI_RX_FIFO_UNF); + + spin_unlock(&tqspi->lock); + + queue_work(tqspi->wq, &tqspi->irq_work); + + return IRQ_HANDLED; } =20 static struct tegra_qspi_soc_data tegra210_qspi_soc_data =3D { @@ -1793,9 +1826,19 @@ static int tegra_qspi_probe(struct platform_device *= pdev) =20 pm_runtime_put_autosuspend(&pdev->dev); =20 - ret =3D request_threaded_irq(tqspi->irq, NULL, - tegra_qspi_isr_thread, IRQF_ONESHOT, - dev_name(&pdev->dev), tqspi); + tqspi->wq =3D devm_alloc_workqueue(&pdev->dev, "%s", + WQ_HIGHPRI | WQ_UNBOUND, 0, + dev_name(&pdev->dev)); + if (!tqspi->wq) { + dev_err(&pdev->dev, "failed to allocate workqueue\n"); + ret =3D -ENOMEM; + goto exit_pm_disable; + } + + INIT_WORK(&tqspi->irq_work, tegra_qspi_work_handler); + + ret =3D devm_request_irq(&pdev->dev, tqspi->irq, tegra_qspi_isr, + IRQF_SHARED, dev_name(&pdev->dev), tqspi); if (ret < 0) { dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", tqspi->irq, ret); goto exit_pm_disable; @@ -1804,13 +1847,11 @@ static int tegra_qspi_probe(struct platform_device = *pdev) ret =3D spi_register_controller(host); if (ret < 0) { dev_err(&pdev->dev, "failed to register host: %d\n", ret); - goto exit_free_irq; + goto exit_pm_disable; } =20 return 0; =20 -exit_free_irq: - free_irq(qspi_irq, tqspi); exit_pm_disable: pm_runtime_dont_use_autosuspend(&pdev->dev); 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charset="utf-8" The threaded IRQ handler reads QSPI_TRANS_STATUS to check for transfer completion, but on heavily loaded systems, the thread can be delayed long enough for wait_for_completion_timeout() to expire first. When the timeout handler then reads TRANS_STATUS directly from hardware, it may see a completed transfer but race with the (now-running) IRQ thread, leading to double completion or use-after-free on curr_xfer. With the conversion to hard IRQ + workqueue in the previous patch, this race still exists: the workqueue bottom-half can be delayed past the timeout, and the timeout handler reading hardware directly has no synchronization with the ISR's cached state. Cache QSPI_TRANS_STATUS in the ISR before clearing it, allowing the timeout handler to check the cached value under spinlock. Also guard against curr_xfer being NULLed by a concurrent workqueue completion. Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra210-quad.c | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-qua= d.c index 17d0b511af1d..72f66f2c6dab 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -214,6 +214,7 @@ struct tegra_qspi { u32 tx_status; u32 rx_status; u32 status_reg; + u32 trans_status; bool is_packed; bool use_dma; =20 @@ -854,6 +855,7 @@ static u32 tegra_qspi_setup_transfer_one(struct spi_dev= ice *spi, struct spi_tran tqspi->cur_rx_pos =3D 0; tqspi->cur_tx_pos =3D 0; tqspi->curr_xfer =3D t; + tqspi->trans_status =3D 0; spin_unlock_irqrestore(&tqspi->lock, flags); =20 if (is_first_of_msg) { @@ -1068,26 +1070,30 @@ static irqreturn_t handle_dma_based_xfer(struct teg= ra_qspi *tqspi); */ static int tegra_qspi_handle_timeout(struct tegra_qspi *tqspi) { + unsigned long flags; irqreturn_t ret; - u32 status; =20 - /* Check if hardware actually completed the transfer */ - status =3D tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS); - if (!(status & QSPI_RDY)) + spin_lock_irqsave(&tqspi->lock, flags); + + if (!(tqspi->trans_status & QSPI_RDY)) { + spin_unlock_irqrestore(&tqspi->lock, flags); return -ETIMEDOUT; + } =20 /* - * Hardware completed but interrupt was lost/delayed. Manually - * process the completion by calling the appropriate handler. + * ISR or workqueue may have already completed the transfer + * and NULLed curr_xfer between the completion timeout and now. */ + if (!tqspi->curr_xfer) { + spin_unlock_irqrestore(&tqspi->lock, flags); + return 0; + } + + spin_unlock_irqrestore(&tqspi->lock, flags); + dev_warn_ratelimited(tqspi->dev, "QSPI interrupt timeout, but transfer complete\n"); =20 - /* Clear the transfer status */ - status =3D tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS); - tegra_qspi_writel(tqspi, status, QSPI_TRANS_STATUS); - - /* Manually trigger completion handler */ if (!tqspi->is_curr_dma_xfer) ret =3D handle_cpu_based_xfer(tqspi); else @@ -1642,6 +1648,8 @@ static irqreturn_t tegra_qspi_isr(int irq, void *cont= ext_data) if (!(status & QSPI_RDY)) return IRQ_NONE; =20 + tqspi->trans_status =3D status; + spin_lock(&tqspi->lock); tqspi->status_reg =3D tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS); tegra_qspi_mask_clear_irq(tqspi); --=20 2.17.1 From nobody Mon May 25 02:41:46 2026 Received: from CH1PR05CU001.outbound.protection.outlook.com (mail-northcentralusazon11010004.outbound.protection.outlook.com [52.101.193.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44C97352020; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: wHXhc0GDbhz8txWY/8oXb3bgXe014OLfwlL1RIT3lOsHG0V8eVYMP64fd7ytBZ5adTHY/7ZEaajUqCFYx3aQYlPoP/lSlEJsVbfB8buc1E2tzg3dPlTdzdIRA5ijECIhdwBktRYNu1KremlS8ofttM0PB1DHv6pdjQBAHsNwzCg6sy8E44UQ1S+rtonsGRwUfzQ+rKA44svcjpaCM74dBMHc4HlO6hQH0olSIY+x+zjuo0zc8QBNZv53iCbNOHr6J+lk0f/yakRFDowT451QNLVK+NjRLNZVbwS1CJWz4zxKxdJ7PhooNrIgeyBDLgLqfa351rWmm0yjRAEPmq0KVlSxwsEVX/f8xRcVW+tbsuCNqySkcb8YPFDOUPDn65PM1Hoe5lIGy4mp5CKdT76+2wLoARBHnJxqYlsFfHR420kb/dASlfpiUAU1k1CnRzxc X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 15:51:35.1787 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83e935d4-5ebe-4a8a-ce7b-08deb5be816f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6191 On heavily loaded systems, workqueue scheduling delays can exceed transfer timeouts even for high-priority queues, causing false timeouts for latency-sensitive devices like TPM despite hardware completing in microseconds. Process small PIO transfers (=E2=89=A4256 bytes) directly in hard IRQ conte= xt instead of deferring to workqueue. This reduces completion latency from 1000ms+ to microseconds and matches the pattern used by other SPI drivers. The 256-byte threshold (FIFO depth) ensures small transfers for devices like TPMs use the fast path, while larger transfers continue using workqueue. Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra210-quad.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-qua= d.c index 72f66f2c6dab..bb3c51b3a57d 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -1664,6 +1664,15 @@ static irqreturn_t tegra_qspi_isr(int irq, void *con= text_data) =20 spin_unlock(&tqspi->lock); =20 + /* + * For small PIO transfers (e.g., TPM), process directly in hard IRQ + * context unless there was a FIFO error. Error recovery calls + * device_reset() which can sleep, so must be deferred to workqueue. + */ + if (!tqspi->is_curr_dma_xfer && tqspi->curr_dma_words <=3D QSPI_FIFO_DEPT= H && + !tqspi->tx_status && !tqspi->rx_status) + return handle_cpu_based_xfer(tqspi); + queue_work(tqspi->wq, &tqspi->irq_work); =20 return IRQ_HANDLED; --=20 2.17.1