From nobody Mon May 25 01:59:22 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DAC2739B97E; Tue, 19 May 2026 12:37:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779194225; cv=none; b=jJLJrC7u7Fdf/tiCz6F0l37Bs7aiE/CTiIMyMsFl5MiPP92vaAzrcfYZePbjdqo6au0WYb3Bcz4Zm4jZp/UjhqKa5NBQvQUUTWGGt3vEwwJzev9uYoZwKG55phM78M7jHMCaVZ+622ZbgrS4olNOV4WYd+i1Txvf51V2pdQviLs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779194225; c=relaxed/simple; bh=hmaITsv7VsqrKmGta0DpGeau4BtCtH5xIHUyEGnyzS4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FLqADxldWk+VN1ZiaQhiZ4pHIQjHKPZffRCESMeVW8ZTYXssEYSMAyvq5FRD01YkQIPPa64ifCv6G3AK3ZYgSDHohwvDIPkTAFtpdWvA4z5+M8Shu3fnhrra87GSKh83S9jZWfJQIhIj2JScF3XmhUw+dYf4LA/s12QKkSTZckA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=XMXuCEuQ; arc=none smtp.client-ip=117.135.210.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="XMXuCEuQ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=2j uabFZm9o6KU22SgTNYHRacHAJp/0HbANhOiPWCsZA=; b=XMXuCEuQ7K+uzeAhu1 vB+UlypeBQ1Ywfku5vOH2eqBmyNyqLYtV51on1uFA1IMOYtjbXFrmzrBVB+/zhlM b+fQoqsopGsXl/9BomgR2gEsgz31aQQW71AjKsfNEkyL82gFXBOXsuj/1ROeb6mP jjFTzxjt2wGpxcjtBWm1q1DFM= Received: from Precision-7960.. (unknown []) by gzsmtp4 (Coremail) with SMTP id PygvCgDX4hY8WQxqQIRSEQ--.27887S3; Tue, 19 May 2026 20:36:17 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org Cc: robh@kernel.org, mpillai@cadence.com, a-garg7@ti.com, s-vadapalli@ti.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v6 1/3] PCI: cadence: Add HPA architecture flag Date: Tue, 19 May 2026 20:36:07 +0800 Message-ID: <20260519123609.1595280-2-18255117159@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519123609.1595280-1-18255117159@163.com> References: <20260519123609.1595280-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PygvCgDX4hY8WQxqQIRSEQ--.27887S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7AFy3ArWfuw4Dtr4kXr4UXFb_yoW8Zr13pa yDGFyfC3WfXF45uan5Z3W5GF1a9FnxZasrKwsI9w1fuF13CrWUGFy2gFyrJF9xKrW7ur1I vF1DtasrJFsIyrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pR7EfrUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC6wIEp2oMWULBrQAA3b Content-Type: text/plain; charset="utf-8" Add a boolean flag 'is_hpa' to the cdns_pcie structure to indicate that the controller is part of a Heterogeneous Processor Architecture (HPA) system. This flag will be used by subsequent patches to handle HPA-specific register layouts and behaviors. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/cadence/pci-sky1.c | 1 + drivers/pci/controller/cadence/pcie-cadence.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/pci/controller/cadence/pci-sky1.c b/drivers/pci/contro= ller/cadence/pci-sky1.c index cd55c64e58a9..e1f4a98e2ab6 100644 --- a/drivers/pci/controller/cadence/pci-sky1.c +++ b/drivers/pci/controller/cadence/pci-sky1.c @@ -174,6 +174,7 @@ static int sky1_pcie_probe(struct platform_device *pdev) cdns_pcie->reg_base =3D pcie->reg_base; cdns_pcie->msg_res =3D pcie->msg_res; cdns_pcie->is_rc =3D true; + cdns_pcie->is_hpa =3D true; =20 reg_off =3D devm_kzalloc(dev, sizeof(*reg_off), GFP_KERNEL); if (!reg_off) { diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index 574e9cf4d003..9a464cbaf073 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -80,6 +80,7 @@ struct cdns_plat_pcie_of_data { * @msg_res: Region for send message to map PCI accesses * @dev: PCIe controller * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoi= nt. + * @is_hpa: indicates if the architecture is HPA * @phy_count: number of supported PHY devices * @phy: list of pointers to specific PHY control blocks * @link: list of pointers to corresponding device link representations @@ -93,6 +94,7 @@ struct cdns_pcie { struct resource *msg_res; struct device *dev; bool is_rc; + bool is_hpa; int phy_count; struct phy **phy; struct device_link **link; --=20 2.43.0 From nobody Mon May 25 01:59:22 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A82804DB56F; Tue, 19 May 2026 12:37:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779194228; cv=none; b=eMh9NnB5aXvs48hFHk+gOE4D+wll351m/H8oULkKK+QhMSDDe+lnfsYN/9PxZNyltmr7HdEtcKSPZvg1DvUGtAF2s1+H2iC6MpEBG83NA6R4xXcsCVKDu6zYmujj1L7CxlS8DgpjqyPAlAyYiuX3w4dQ4jf3Fb8AvqbQahbmZJY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779194228; c=relaxed/simple; bh=SJYxFYUYQ454Pw30LbsApzJcvxxUhX/kAMCtVHlr8rc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mI+mf4ndT16O7pMns4JqDfVd558fDBbXOC5cijSB6dgdo2y4OezGoRNDBwkeke1lMMI13hYIRPvAD23mkrVSOuPvVYu1z2SkAD9zJaoOV7O1+3xWUZ75E6WXNTEZ2vS+Zjfc9APepke9dm3Qsy8D732MqaUmpUvhneCPzt/gkt4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=D93PmAvN; arc=none smtp.client-ip=220.197.31.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="D93PmAvN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=L2 +m/F7XlwqLjWCqxytVjBYDagOHTgE+7wevqczbcMo=; b=D93PmAvNP6F05Taiuk CvqozPiY1EPN7o3aqHIf2TrhHD98oxPDuFCy4iZshf8xC7Sr4cgg8c2KGvr8i1Dy +ohaunAFzhWHpHfQdOoscuIQaPQ6XBwb1D+O1R/vzi2XYjdMG7u910bwiou0V1DG vsgcvx4T9x8z+88SFLUvLugAM= Received: from Precision-7960.. (unknown []) by gzsmtp4 (Coremail) with SMTP id PygvCgDX4hY8WQxqQIRSEQ--.27887S4; Tue, 19 May 2026 20:36:18 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org Cc: robh@kernel.org, mpillai@cadence.com, a-garg7@ti.com, s-vadapalli@ti.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v6 2/3] PCI: cadence: Add HPA IP debugfs for LTSSM status Date: Tue, 19 May 2026 20:36:08 +0800 Message-ID: <20260519123609.1595280-3-18255117159@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519123609.1595280-1-18255117159@163.com> References: <20260519123609.1595280-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PygvCgDX4hY8WQxqQIRSEQ--.27887S4 X-Coremail-Antispam: 1Uf129KBjvAXoWfXr43Jr43tFyxXr48WF1xKrg_yoW5GF4Uto ZxGrn3K3WxZ34qyas3J3ZrGF97Xr1S93W3tFy8Kr1rGFsIgFnrtrWUXr18ta1rW34DtrW3 AryDX3W2yr4xW39rn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UbIYCTnIWIevJa73UjIFyTuYvjTRXyCJUUUUU X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCwwIEp2oMWUICBwAA3a Content-Type: text/plain; charset="utf-8" Add debugfs support for HPA-based Cadence PCIe controllers. A new file 'ltssm_status' is created under debugfs, allowing users to read the current LTSSM state as a string and raw value. Signed-off-by: Hans Zhang <18255117159@163.com> --- Documentation/ABI/testing/debugfs-cdns-pcie | 5 + drivers/pci/controller/cadence/Kconfig | 9 + drivers/pci/controller/cadence/Makefile | 1 + drivers/pci/controller/cadence/pci-sky1.c | 4 + .../controller/cadence/pcie-cadence-debugfs.c | 208 ++++++++++++++++++ .../cadence/pcie-cadence-host-hpa.c | 19 +- drivers/pci/controller/cadence/pcie-cadence.h | 153 +++++++++++++ 7 files changed, 398 insertions(+), 1 deletion(-) create mode 100644 Documentation/ABI/testing/debugfs-cdns-pcie create mode 100644 drivers/pci/controller/cadence/pcie-cadence-debugfs.c diff --git a/Documentation/ABI/testing/debugfs-cdns-pcie b/Documentation/AB= I/testing/debugfs-cdns-pcie new file mode 100644 index 000000000000..c1104e28e4ee --- /dev/null +++ b/Documentation/ABI/testing/debugfs-cdns-pcie @@ -0,0 +1,5 @@ +What: /sys/kernel/debug/cdns_pcie_/ltssm_status +Date: March 2026 +Contact: Hans Zhang <18255117159@163.com> +Description: (RO) Read will return the current PCIe LTSSM state in both + string and raw value. \ No newline at end of file diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controlle= r/cadence/Kconfig index 9e651d545973..cb010bc97aad 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -6,6 +6,15 @@ menu "Cadence-based PCIe controllers" config PCIE_CADENCE tristate =20 +config PCIE_CADENCE_DEBUGFS + tristate "Cadence PCIe debugfs entries" + depends on DEBUG_FS + depends on PCIE_CADENCE_HOST || PCIE_CADENCE_EP + help + Say Y here to enable debugfs entries for the PCIe controller. These + entries provide various debug features related to the controller and + the LTSSM status of link can be displayed. + config PCIE_CADENCE_HOST tristate depends on OF diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index b8ec1cecfaa8..2cdc4617e0c2 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -4,6 +4,7 @@ pcie-cadence-host-mod-y :=3D pcie-cadence-host-common.o pci= e-cadence-host.o pcie-c pcie-cadence-ep-mod-y :=3D pcie-cadence-ep.o =20 obj-$(CONFIG_PCIE_CADENCE) =3D pcie-cadence-mod.o +obj-$(CONFIG_PCIE_CADENCE_DEBUGFS) +=3D pcie-cadence-debugfs.o obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host-mod.o obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep-mod.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o diff --git a/drivers/pci/controller/cadence/pci-sky1.c b/drivers/pci/contro= ller/cadence/pci-sky1.c index e1f4a98e2ab6..b8632f1d3156 100644 --- a/drivers/pci/controller/cadence/pci-sky1.c +++ b/drivers/pci/controller/cadence/pci-sky1.c @@ -221,6 +221,10 @@ MODULE_DEVICE_TABLE(of, of_sky1_pcie_match); static void sky1_pcie_remove(struct platform_device *pdev) { struct sky1_pcie *pcie =3D platform_get_drvdata(pdev); + struct cdns_pcie_rc *rc; + + rc =3D container_of(pcie->cdns_pcie, struct cdns_pcie_rc, pcie); + cdns_pcie_hpa_host_disable(rc); =20 pci_ecam_free(pcie->cfg); } diff --git a/drivers/pci/controller/cadence/pcie-cadence-debugfs.c b/driver= s/pci/controller/cadence/pcie-cadence-debugfs.c new file mode 100644 index 000000000000..97c5deef2b1a --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Cadence PCIe controller debugfs driver + * + * Copyright (C) 2026 Hans Zhang <18255117159@163.com> + */ + +#include +#include +#include + +#include "pcie-cadence.h" + +#define CDNS_DEBUGFS_BUF_MAX 128 + +static const char *cdns_pcie_hpa_ltssm_status_string(enum cdns_pcie_hpa_lt= ssm ltssm) +{ + const char *str; + + switch (ltssm) { +#define CDNS_PCIE_HPA_LTSSM_NAME(n) case n: str =3D #n; break + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DETECT_QUIET); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DETECT_QUIET_ENTRY); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE_2); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE_3); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RCVR_DETECTED_ST); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RCVR_DETECTED_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE_2); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE_3); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_CONFIG); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_CONFIG_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_CONFIG_2); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_RC); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_RC_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_RC_2); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_ACC_RC); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_RC); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_RC_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_ACC_RC); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_EP); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_EP_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_EP_2); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_ACC_EP); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_EP); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_EP_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_ACC_EP); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_ACC_EP_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_COMPLETE); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_COMPLETE_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_COMPLETE_2); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_IDLE); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_IDLE_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_2); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_3); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_4); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L0_STATE); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_LOCK); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_LOCK_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_CFG); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_CFG_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_IDLE); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_IDLE_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_2); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_3); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_4); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_5); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_6); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_7); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_HOT_RESET); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_HOT_RESET_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_HOT_RESET_2); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_HOT_RESET_3); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L0S_ENTRY); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L0S_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L0S_2); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L0S_3); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L0S_4); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L0S_5); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_WAIT_FOR_LINK_TX); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_TX_FTS_ENTRY); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_TX_FTS_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_TX_FTS_2); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_ST); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_2); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_3); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED_2); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED_3); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_2); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_3); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_4); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_5); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_6); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_7); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_8); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_ENTRY); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_ENTRY_FROM_RE= COVERY); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_EXIT_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_EXIT); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_2); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_3); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_4); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_5); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_ACTIVE); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L1_ENTRY); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L1_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L1_2); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L1_3); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L1_4); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L1_IDLE); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L1_EXIT); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L2_ENTRY); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L2_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L2_2); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L2_3); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L2_4); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L2_5); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L2_IDLE); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_2); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_3); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_4); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_5); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_FROM_R= ECOVERY); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ACTIVE); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_EXIT); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_EXIT_1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_EXIT_2); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE0= ); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE1= ); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE2= _1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE2= _2); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE3= _1); + CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE3= _2); + default: + str =3D "CDNS_PCIE_HPA_LTSSM_UNKNOWN"; + break; + } + + return str + strlen("CDNS_PCIE_HPA_LTSSM_"); +} + +static int ltssm_status_show(struct seq_file *s, void *v) +{ + struct cdns_pcie *pci =3D s->private; + enum cdns_pcie_hpa_ltssm hpa_ltssm; + const char *str_ltssm; + u32 val; + + if (pci->is_hpa) { + val =3D cdns_pcie_hpa_readl(pci, REG_BANK_IP_REG, + CDNS_PCIE_HPA_PHY_DBG_STS_REG0); + hpa_ltssm =3D FIELD_GET(CDNS_PCIE_HPA_LTSSM_STATUS_MASK, val); + str_ltssm =3D cdns_pcie_hpa_ltssm_status_string(hpa_ltssm); + } else { + /* TODO: LGA IP*/ + return 0; + } + + seq_printf(s, "%s (0x%02x)\n", str_ltssm, hpa_ltssm); + + return 0; +} + +DEFINE_SHOW_ATTRIBUTE(ltssm_status); + +static void cdns_pcie_ltssm_debugfs_init(struct cdns_pcie *pci, struct den= try *dir) +{ + debugfs_create_file("ltssm_status", 0444, dir, pci, + <ssm_status_fops); +} + +void cdns_pcie_debugfs_deinit(struct cdns_pcie *pci) +{ + if (!pci->debug_dir) + return; + + debugfs_remove_recursive(pci->debug_dir); +} +EXPORT_SYMBOL_GPL(cdns_pcie_debugfs_deinit); + +void cdns_pcie_debugfs_init(struct cdns_pcie *pci) +{ + char dirname[CDNS_DEBUGFS_BUF_MAX]; + struct device *dev =3D pci->dev; + + /* Create main directory for each platform driver. */ + snprintf(dirname, CDNS_DEBUGFS_BUF_MAX, "cdns_pcie_%s", dev_name(dev)); + pci->debug_dir =3D debugfs_create_dir(dirname, NULL); + + cdns_pcie_ltssm_debugfs_init(pci, pci->debug_dir); +} +EXPORT_SYMBOL_GPL(cdns_pcie_debugfs_init); diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c b/drive= rs/pci/controller/cadence/pcie-cadence-host-hpa.c index 0f540bed58e8..abc1d0e58b98 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c @@ -309,6 +309,17 @@ int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc = *rc) } EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_link_setup); =20 +void cdns_pcie_hpa_host_disable(struct cdns_pcie_rc *rc) +{ + struct pci_host_bridge *bridge; + + cdns_pcie_debugfs_deinit(&rc->pcie); + bridge =3D pci_host_bridge_from_priv(rc); + pci_stop_root_bus(bridge->bus); + pci_remove_root_bus(bridge->bus); +} +EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_disable); + int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) { struct device *dev =3D rc->pcie.dev; @@ -360,7 +371,13 @@ int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) if (!bridge->ops) bridge->ops =3D &cdns_pcie_hpa_host_ops; =20 - return pci_host_probe(bridge); + ret =3D pci_host_probe(bridge); + if (ret) + return ret; + + cdns_pcie_debugfs_init(pcie); + + return 0; } EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_setup); =20 diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index 9a464cbaf073..2320319af83b 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -14,6 +14,8 @@ #include "pcie-cadence-lga-regs.h" #include "pcie-cadence-hpa-regs.h" =20 +#define CDNS_PCIE_HPA_LTSSM_STATUS_MASK GENMASK(27, 20) + enum cdns_pcie_rp_bar { RP_BAR_UNDEFINED =3D -1, RP_BAR0, @@ -42,6 +44,138 @@ enum cdns_pcie_reg_bank { REG_BANKS_MAX, }; =20 +enum cdns_pcie_hpa_ltssm { + CDNS_PCIE_HPA_LTSSM_DETECT_QUIET =3D 0, + CDNS_PCIE_HPA_LTSSM_DETECT_QUIET_ENTRY =3D 1, + CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE =3D 2, + CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE_1 =3D 3, + CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE_2 =3D 4, + CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE_3 =3D 5, + CDNS_PCIE_HPA_LTSSM_RCVR_DETECTED_ST =3D 6, + CDNS_PCIE_HPA_LTSSM_RCVR_DETECTED_1 =3D 7, + CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE =3D 8, + CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE_1 =3D 9, + CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE_2 =3D 10, + CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE_3 =3D 11, + CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE =3D 12, + CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_1 =3D 13, + CDNS_PCIE_HPA_LTSSM_POLLING_CONFIG =3D 14, + CDNS_PCIE_HPA_LTSSM_POLLING_CONFIG_1 =3D 15, + CDNS_PCIE_HPA_LTSSM_POLLING_CONFIG_2 =3D 16, + CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_RC =3D 17, + CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_RC_1 =3D 18, + CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_RC_2 =3D 19, + CDNS_PCIE_HPA_LTSSM_CONFIG_LW_ACC_RC =3D 20, + CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_RC =3D 21, + CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_RC_1 =3D 22, + CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_ACC_RC =3D 23, + CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_EP =3D 24, + CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_EP_1 =3D 25, + CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_EP_2 =3D 26, + CDNS_PCIE_HPA_LTSSM_CONFIG_LW_ACC_EP =3D 27, + CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_EP =3D 28, + CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_EP_1 =3D 29, + CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_ACC_EP =3D 30, + CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_ACC_EP_1 =3D 31, + CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_1 =3D 32, + CDNS_PCIE_HPA_LTSSM_CONFIG_COMPLETE =3D 33, + CDNS_PCIE_HPA_LTSSM_CONFIG_COMPLETE_1 =3D 34, + CDNS_PCIE_HPA_LTSSM_CONFIG_COMPLETE_2 =3D 35, + CDNS_PCIE_HPA_LTSSM_CONFIG_IDLE =3D 36, + CDNS_PCIE_HPA_LTSSM_CONFIG_IDLE_1 =3D 37, + CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_2 =3D 38, + CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_3 =3D 39, + CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_4 =3D 40, + CDNS_PCIE_HPA_LTSSM_L0_STATE =3D 41, + CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_LOCK =3D 42, + CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_LOCK_1 =3D 43, + CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_CFG =3D 44, + CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_CFG_1 =3D 45, + CDNS_PCIE_HPA_LTSSM_RECOVERY_IDLE =3D 46, + CDNS_PCIE_HPA_LTSSM_RECOVERY_IDLE_1 =3D 47, + CDNS_PCIE_HPA_LTSSM_DISABLE_LINK =3D 48, + CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_1 =3D 49, + CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_2 =3D 50, + CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_3 =3D 51, + CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_4 =3D 52, + CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_5 =3D 53, + CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_6 =3D 54, + CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_7 =3D 55, + CDNS_PCIE_HPA_LTSSM_HOT_RESET =3D 56, + CDNS_PCIE_HPA_LTSSM_HOT_RESET_1 =3D 57, + CDNS_PCIE_HPA_LTSSM_HOT_RESET_2 =3D 58, + CDNS_PCIE_HPA_LTSSM_HOT_RESET_3 =3D 59, + CDNS_PCIE_HPA_LTSSM_L0S_ENTRY =3D 60, + CDNS_PCIE_HPA_LTSSM_L0S_1 =3D 61, + CDNS_PCIE_HPA_LTSSM_L0S_2 =3D 62, + CDNS_PCIE_HPA_LTSSM_L0S_3 =3D 63, + CDNS_PCIE_HPA_LTSSM_L0S_4 =3D 64, + CDNS_PCIE_HPA_LTSSM_L0S_5 =3D 65, + CDNS_PCIE_HPA_LTSSM_WAIT_FOR_LINK_TX =3D 66, + CDNS_PCIE_HPA_LTSSM_TX_FTS_ENTRY =3D 67, + CDNS_PCIE_HPA_LTSSM_TX_FTS_1 =3D 68, + CDNS_PCIE_HPA_LTSSM_TX_FTS_2 =3D 69, + CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_ST =3D 70, + CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_1 =3D 71, + CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_2 =3D 72, + CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_3 =3D 73, + CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED =3D 74, + CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED_1 =3D 75, + CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED_2 =3D 76, + CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED_3 =3D 77, + CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23 =3D 78, + CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_1 =3D 79, + CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_2 =3D 80, + CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_3 =3D 81, + CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_4 =3D 82, + CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_5 =3D 83, + CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_6 =3D 84, + CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_7 =3D 85, + CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_8 =3D 86, + CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_ENTRY =3D 87, + CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_ENTRY_FROM_RECOVERY =3D 88, + CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_EXIT_1 =3D 89, + CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_EXIT =3D 90, + CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_1 =3D 91, + CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_2 =3D 92, + CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_3 =3D 93, + CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_4 =3D 94, + CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_5 =3D 95, + CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_ACTIVE =3D 96, + CDNS_PCIE_HPA_LTSSM_L1_ENTRY =3D 97, + CDNS_PCIE_HPA_LTSSM_L1_1 =3D 98, + CDNS_PCIE_HPA_LTSSM_L1_2 =3D 99, + CDNS_PCIE_HPA_LTSSM_L1_3 =3D 100, + CDNS_PCIE_HPA_LTSSM_L1_4 =3D 101, + CDNS_PCIE_HPA_LTSSM_L1_IDLE =3D 102, + CDNS_PCIE_HPA_LTSSM_L1_EXIT =3D 103, + CDNS_PCIE_HPA_LTSSM_L2_ENTRY =3D 104, + CDNS_PCIE_HPA_LTSSM_L2_1 =3D 105, + CDNS_PCIE_HPA_LTSSM_L2_2 =3D 106, + CDNS_PCIE_HPA_LTSSM_L2_3 =3D 107, + CDNS_PCIE_HPA_LTSSM_L2_4 =3D 108, + CDNS_PCIE_HPA_LTSSM_L2_5 =3D 109, + CDNS_PCIE_HPA_LTSSM_L2_IDLE =3D 110, + CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY =3D 111, + CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_1 =3D 112, + CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_2 =3D 113, + CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_3 =3D 114, + CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_4 =3D 115, + CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_5 =3D 116, + CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_FROM_RECOVERY =3D 117, + CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ACTIVE =3D 118, + CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_EXIT =3D 119, + CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_EXIT_1 =3D 120, + CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_EXIT_2 =3D 121, + CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE0 =3D 122, + CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE1 =3D 123, + CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE2_1 =3D 124, + CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE2_2 =3D 125, + CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE3_1 =3D 126, + CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE3_2 =3D 127, + CDNS_PCIE_HPA_LTSSM_UNKNOWN =3D 0xFFFFFFFF, +}; + struct cdns_pcie_ops { int (*start_link)(struct cdns_pcie *pcie); void (*stop_link)(struct cdns_pcie *pcie); @@ -87,6 +221,7 @@ struct cdns_plat_pcie_of_data { * @ops: Platform-specific ops to control various inputs from Cadence PCIe * wrapper * @cdns_pcie_reg_offsets: Register bank offsets for different SoC + * @debug_dir: debugfs node */ struct cdns_pcie { void __iomem *reg_base; @@ -100,6 +235,7 @@ struct cdns_pcie { struct device_link **link; const struct cdns_pcie_ops *ops; const struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets; + struct dentry *debug_dir; }; =20 /** @@ -447,6 +583,7 @@ void cdns_pcie_host_disable(struct cdns_pcie_rc *rc); void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, int where); int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc); +void cdns_pcie_hpa_host_disable(struct cdns_pcie_rc *rc); #else static inline int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc) { @@ -472,6 +609,10 @@ static inline void cdns_pcie_host_disable(struct cdns_= pcie_rc *rc) { } =20 +static inline void cdns_pcie_hpa_host_disable(struct cdns_pcie_rc *rc) +{ +} + static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned= int devfn, int where) { @@ -535,4 +676,16 @@ bool cdns_pcie_hpa_link_up(struct cdns_pcie *pcie); =20 extern const struct dev_pm_ops cdns_pcie_pm_ops; =20 +#ifdef CONFIG_PCIE_CADENCE_DEBUGFS +void cdns_pcie_debugfs_deinit(struct cdns_pcie *pci); +void cdns_pcie_debugfs_init(struct cdns_pcie *pci); +#else +static inline void cdns_pcie_debugfs_deinit(struct cdns_pcie *pci) +{ +} +static inline void cdns_pcie_debugfs_init(struct cdns_pcie *pci) +{ +} +#endif + #endif /* _PCIE_CADENCE_H */ --=20 2.43.0 From nobody Mon May 25 01:59:22 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C375E4DBD84; Tue, 19 May 2026 12:37:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779194234; cv=none; b=i0tyiDxAbL6TsNsucCIvf3mV8S95dhltPhEoPD9grNjmokD91OFR7WYdZ5U1sC56RW4GKgPt1Mq2XliK24bxqTqFLXy5K9tVNPZ6dXk5Xa4o3j6oBQKw01Y+vEV8pZPPHSdQZvUHUgG08z+B7nOv6fVv8x1qVgub4qcGumlKgCM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779194234; c=relaxed/simple; bh=Xjj48Lq9rY1mktByfxZD2CA+vSErISSzacNj4c6HnEE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: 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(unknown []) by gzsmtp4 (Coremail) with SMTP id PygvCgDX4hY8WQxqQIRSEQ--.27887S5; Tue, 19 May 2026 20:36:19 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org Cc: robh@kernel.org, mpillai@cadence.com, a-garg7@ti.com, s-vadapalli@ti.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v6 3/3] PCI: cadence: Add LGA IP debugfs for LTSSM status Date: Tue, 19 May 2026 20:36:09 +0800 Message-ID: <20260519123609.1595280-4-18255117159@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519123609.1595280-1-18255117159@163.com> References: <20260519123609.1595280-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PygvCgDX4hY8WQxqQIRSEQ--.27887S5 X-Coremail-Antispam: 1Uf129KBjvJXoWxtF1UKr17tFyUJr1UGw4kZwb_yoWDGFy3pF ykCayvyF4IvwnFva1jy3WDZF45JFsayFZrArs7ArW0k3ZxA3WDWr45Jr4vkrZ5tFsrWr12 qwn0yrnrGayfJ3JanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pK0Ph-UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC6wMEp2oMWUPB1AAA3i Content-Type: text/plain; charset="utf-8" Extend debugfs support to LGA-based Cadence PCIe controllers. The 'ltssm_status' file now works for both HPA and LGA IP by selecting the appropriate register access based on the 'is_hpa' flag. Signed-off-by: Hans Zhang <18255117159@163.com> --- .../controller/cadence/pcie-cadence-debugfs.c | 61 ++++++++++++++++++- .../pci/controller/cadence/pcie-cadence-ep.c | 3 + .../controller/cadence/pcie-cadence-host.c | 9 ++- drivers/pci/controller/cadence/pcie-cadence.h | 43 +++++++++++++ 4 files changed, 112 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-debugfs.c b/driver= s/pci/controller/cadence/pcie-cadence-debugfs.c index 97c5deef2b1a..0a308f95e9f6 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-debugfs.c +++ b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c @@ -13,6 +13,58 @@ =20 #define CDNS_DEBUGFS_BUF_MAX 128 =20 +static const char *cdns_pcie_lga_ltssm_status_string(enum cdns_pcie_lga_lt= ssm ltssm) +{ + const char *str; + + switch (ltssm) { +#define CDNS_PCIE_LGA_LTSSM_NAME(n) case n: str =3D #n; break + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_DETECT_QUIET); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_DETECT_ACTIVE); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_POLLING_ACTIVE); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_POLLING_COMPLIANCE); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_POLLING_CONFIGURATION); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LINKWIDTH_STAR= T); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LINKWIDTH_ACCE= PT); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LANENUM_ACCEPT= ); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LANENUM_WAIT); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURATION_COMPLETE); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURATION_IDLE); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_RCVRLOCK); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_SPEED); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_RCVRCFG); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_IDLE); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_L0); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RX_L0S_ENTRY); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RX_L0S_IDLE); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RX_L0S_FTS); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_TX_L0S_ENTRY); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_TX_L0S_IDLE); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_TX_L0S_FTS); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_L1_ENTRY); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_L1_IDLE); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_L2_IDLE); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_L2_TRANSMITWAKE); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_DISABLED); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_ENTRY_MASTER); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_ACTIVE_MASTER); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_EXIT_MASTER); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_ENTRY_SLAVE); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_ACTIVE_SLAVE); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_EXIT_SLAVE); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_HOT_RESET); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_= 0); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_= 1); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_= 2); + CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_= 3); + default: + str =3D "CDNS_PCIE_LGA_LTSSM_UNKNOWN"; + break; + } + + return str + strlen("CDNS_PCIE_LGA_LTSSM_"); +} + static const char *cdns_pcie_hpa_ltssm_status_string(enum cdns_pcie_hpa_lt= ssm ltssm) { const char *str; @@ -158,6 +210,7 @@ static const char *cdns_pcie_hpa_ltssm_status_string(en= um cdns_pcie_hpa_ltssm lt static int ltssm_status_show(struct seq_file *s, void *v) { struct cdns_pcie *pci =3D s->private; + enum cdns_pcie_lga_ltssm lga_ltssm; enum cdns_pcie_hpa_ltssm hpa_ltssm; const char *str_ltssm; u32 val; @@ -168,11 +221,13 @@ static int ltssm_status_show(struct seq_file *s, void= *v) hpa_ltssm =3D FIELD_GET(CDNS_PCIE_HPA_LTSSM_STATUS_MASK, val); str_ltssm =3D cdns_pcie_hpa_ltssm_status_string(hpa_ltssm); } else { - /* TODO: LGA IP*/ - return 0; + val =3D cdns_pcie_readl(pci, CDNS_PCIE_LM_BASE); + lga_ltssm =3D FIELD_GET(CDNS_PCIE_LGA_LTSSM_STATUS_MASK, val); + str_ltssm =3D cdns_pcie_lga_ltssm_status_string(lga_ltssm); } =20 - seq_printf(s, "%s (0x%02x)\n", str_ltssm, hpa_ltssm); + seq_printf(s, "%s (0x%02x)\n", str_ltssm, + pci->is_hpa ? hpa_ltssm : lga_ltssm); =20 return 0; } diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci= /controller/cadence/pcie-cadence-ep.c index c0e1194a936b..370b19f4d38f 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -655,6 +655,7 @@ void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep) struct device *dev =3D ep->pcie.dev; struct pci_epc *epc =3D to_pci_epc(dev); =20 + cdns_pcie_debugfs_deinit(&ep->pcie); pci_epc_deinit_notify(epc); pci_epc_mem_free_addr(epc, ep->irq_phys_addr, ep->irq_cpu_addr, SZ_128K); @@ -761,6 +762,8 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) =20 pci_epc_init_notify(epc); =20 + cdns_pcie_debugfs_init(pcie); + return 0; =20 free_epc_mem: diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/p= ci/controller/cadence/pcie-cadence-host.c index 0bc9e6e90e0e..8105bb625eb7 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -364,6 +364,7 @@ void cdns_pcie_host_disable(struct cdns_pcie_rc *rc) { struct pci_host_bridge *bridge; =20 + cdns_pcie_debugfs_deinit(&rc->pcie); bridge =3D pci_host_bridge_from_priv(rc); pci_stop_root_bus(bridge->bus); pci_remove_root_bus(bridge->bus); @@ -423,7 +424,13 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) if (!bridge->ops) bridge->ops =3D &cdns_pcie_host_ops; =20 - return pci_host_probe(bridge); + ret =3D pci_host_probe(bridge); + if (ret) + return ret; + + cdns_pcie_debugfs_init(pcie); + + return 0; } EXPORT_SYMBOL_GPL(cdns_pcie_host_setup); =20 diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index 2320319af83b..8bc6564c65b9 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -14,6 +14,7 @@ #include "pcie-cadence-lga-regs.h" #include "pcie-cadence-hpa-regs.h" =20 +#define CDNS_PCIE_LGA_LTSSM_STATUS_MASK GENMASK(29, 24) #define CDNS_PCIE_HPA_LTSSM_STATUS_MASK GENMASK(27, 20) =20 enum cdns_pcie_rp_bar { @@ -44,6 +45,48 @@ enum cdns_pcie_reg_bank { REG_BANKS_MAX, }; =20 +enum cdns_pcie_lga_ltssm { + CDNS_PCIE_LGA_LTSSM_DETECT_QUIET =3D 0x00, + CDNS_PCIE_LGA_LTSSM_DETECT_ACTIVE =3D 0x01, + CDNS_PCIE_LGA_LTSSM_POLLING_ACTIVE =3D 0x02, + CDNS_PCIE_LGA_LTSSM_POLLING_COMPLIANCE =3D 0x03, + CDNS_PCIE_LGA_LTSSM_POLLING_CONFIGURATION =3D 0x04, + CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LINKWIDTH_START =3D 0x05, + CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LINKWIDTH_ACCEPT =3D 0x06, + CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LANENUM_ACCEPT =3D 0x07, + CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LANENUM_WAIT =3D 0x08, + CDNS_PCIE_LGA_LTSSM_CONFIGURATION_COMPLETE =3D 0x09, + CDNS_PCIE_LGA_LTSSM_CONFIGURATION_IDLE =3D 0x0A, + CDNS_PCIE_LGA_LTSSM_RECOVERY_RCVRLOCK =3D 0x0B, + CDNS_PCIE_LGA_LTSSM_RECOVERY_SPEED =3D 0x0C, + CDNS_PCIE_LGA_LTSSM_RECOVERY_RCVRCFG =3D 0x0D, + CDNS_PCIE_LGA_LTSSM_RECOVERY_IDLE =3D 0x0E, + CDNS_PCIE_LGA_LTSSM_L0 =3D 0x10, + CDNS_PCIE_LGA_LTSSM_RX_L0S_ENTRY =3D 0x11, + CDNS_PCIE_LGA_LTSSM_RX_L0S_IDLE =3D 0x12, + CDNS_PCIE_LGA_LTSSM_RX_L0S_FTS =3D 0x13, + CDNS_PCIE_LGA_LTSSM_TX_L0S_ENTRY =3D 0x14, + CDNS_PCIE_LGA_LTSSM_TX_L0S_IDLE =3D 0x15, + CDNS_PCIE_LGA_LTSSM_TX_L0S_FTS =3D 0x16, + CDNS_PCIE_LGA_LTSSM_L1_ENTRY =3D 0x17, + CDNS_PCIE_LGA_LTSSM_L1_IDLE =3D 0x18, + CDNS_PCIE_LGA_LTSSM_L2_IDLE =3D 0x19, + CDNS_PCIE_LGA_LTSSM_L2_TRANSMITWAKE =3D 0x1A, + CDNS_PCIE_LGA_LTSSM_DISABLED =3D 0x20, + CDNS_PCIE_LGA_LTSSM_LOOPBACK_ENTRY_MASTER =3D 0x21, + CDNS_PCIE_LGA_LTSSM_LOOPBACK_ACTIVE_MASTER =3D 0x22, + CDNS_PCIE_LGA_LTSSM_LOOPBACK_EXIT_MASTER =3D 0x23, + CDNS_PCIE_LGA_LTSSM_LOOPBACK_ENTRY_SLAVE =3D 0x24, + CDNS_PCIE_LGA_LTSSM_LOOPBACK_ACTIVE_SLAVE =3D 0x25, + CDNS_PCIE_LGA_LTSSM_LOOPBACK_EXIT_SLAVE =3D 0x26, + CDNS_PCIE_LGA_LTSSM_HOT_RESET =3D 0x27, + CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_0 =3D 0x28, + CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_1 =3D 0x29, + CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_2 =3D 0x2A, + CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_3 =3D 0x2B, + CDNS_PCIE_LGA_LTSSM_UNKNOWN =3D 0xFFFFFFFF, +}; + enum cdns_pcie_hpa_ltssm { CDNS_PCIE_HPA_LTSSM_DETECT_QUIET =3D 0, CDNS_PCIE_HPA_LTSSM_DETECT_QUIET_ENTRY =3D 1, --=20 2.43.0