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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-134cbdcf140sm22614537c88.5.2026.05.18.23.35.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 23:35:32 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Dmitry Baryshkov , Bartosz Golaszewski , Deepti Jaggi , Harshal Dev , Herbert Xu , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Shawn Guo Subject: [PATCH v2 1/8] dt-bindings: arm: qcom,ids: Add SoC ID for Nord SA8797P Date: Tue, 19 May 2026 14:34:58 +0800 Message-ID: <20260519063505.883379-2-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519063505.883379-1-shengchao.guo@oss.qualcomm.com> References: <20260519063505.883379-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA2MiBTYWx0ZWRfXxlYRim2e0fbw WIz3hDm21zq8pDlojAiA28mdfoTzKD7eXP75v8j9NiJ6wksDWtc9uOMZupREyncwrZp+8ztsjGo mwOys8NiviwnnU69fs/4qN9u63YI8J+dkOxsuptTQbznn/rFF2ER/qHQdl2HhCeu34E7RrABX+p UUAKn9Q/LUHzctaOW6x1wrQ2Jxq4ZaBpYvCeU6bAQVgL4slsNUPY/eAKZ2uqGo0XAgtgc59/aQ5 CpfSAeBRMx35dO7vByWhL0lxrR5SE+EXEwcEEfdipbHLKyUIOsN3uL4UA7vl5U6izsUZQNOFNiX xqipqFUvRuQ7LKZaDTi5C/ThNYRxeShPQoIJMyTTVdQztAbRRWheze8ks5IYek/RITcwUHLzSmF twkWgNmTc9bBGuZorTGzk+3tVhDTp0yEeg1CjoYQNmunSLrdkrLVj4+R3rXzyUcD6zwJH/uVFbO KtW7hxYc5hStPMMF25g== X-Authority-Analysis: v=2.4 cv=A5Jc+aWG c=1 sm=1 tr=0 ts=6a0c04b5 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=v3ITllUuhb3Bg83hOPoA:9 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-GUID: VMHcmmYWFQ47T3B7yVuItjtu95zBAxV9 X-Proofpoint-ORIG-GUID: VMHcmmYWFQ47T3B7yVuItjtu95zBAxV9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 spamscore=0 malwarescore=0 impostorscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190062 Content-Type: text/plain; charset="utf-8" From: Deepti Jaggi Nord is a SoC family from Qualcomm designed as the next generation of Lemans series. SA8797P is the automotive variant of Nord, where platform resources such as clocks, regulators, interconnects, etc. are managed by firmware through SCMI. Add SoC ID for Nord SA8797P. Signed-off-by: Deepti Jaggi Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- include/dt-bindings/arm/qcom,ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/q= com,ids.h index bc65e233eb93..3b353c46b3ab 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -297,6 +297,7 @@ #define QCOM_ID_QCS8275 675 #define QCOM_ID_QCS9075 676 #define QCOM_ID_QCS615 680 +#define QCOM_ID_SA8797P 690 #define QCOM_ID_CQ7790M 731 #define QCOM_ID_CQ7790S 732 #define QCOM_ID_CQ2390M 756 --=20 2.43.0 From nobody Mon May 25 02:57:20 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0169337BB8 for ; Tue, 19 May 2026 06:35:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-134cbdcf140sm22614537c88.5.2026.05.18.23.35.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 23:35:37 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Dmitry Baryshkov , Bartosz Golaszewski , Deepti Jaggi , Harshal Dev , Herbert Xu , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Shawn Guo Subject: [PATCH v2 2/8] soc: qcom: socinfo: Add SoC ID for Nord SA8797P Date: Tue, 19 May 2026 14:34:59 +0800 Message-ID: <20260519063505.883379-3-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519063505.883379-1-shengchao.guo@oss.qualcomm.com> References: <20260519063505.883379-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=Rt316imK c=1 sm=1 tr=0 ts=6a0c04ba cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=8lSouUAgmXO8ZBFbqGgA:9 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-ORIG-GUID: BnuhI_8jLnRS6jUWVHMmgd7mfFkm86ma X-Proofpoint-GUID: BnuhI_8jLnRS6jUWVHMmgd7mfFkm86ma X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA2MiBTYWx0ZWRfX5kK3/Oaq2Arf wd9OPqUPerIA+F0JVQixLCmroh4g95HK34v8LRzKn8jQ7dUijuAYRldXs1W/oqebSAN8c4l0KSv NJTdO9ZaykXCz1Fv9Dkn797YEvfcY1IGz1Sh6ShxiNxR2/FVYDZ3P5fF7Sl+pTTZoKyiJ8iTexS ZjunBwjdXlBC1PdRyrQtP2mjIc+QX1kDMXpxGuwHP2tfRlfaTjR1zkUaQ+Vmet5vHRu/JJYqqdI FC78mWawnmGK8jlZKlEUP1F+y+ZOjNMCKgFjkNayrOuhGkqz36X8rrbjIe9JQjGlBxPub5nb6Aw 5G73/GWDdMmTAsoBZzGnzyXPnZbaCVLAvHouaVY3UjbSKw16wm87uxT5upZFNeLnF3R12ocH83o DkgzjfPpcJQg17hEFj1/GVJCL352NjL+QBVQpb7CtpLEigbwYYIpnCW2Xb2EJs2h3+lOXMlEfN5 0gydghP3sWrgpRzCIrQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 phishscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190062 Content-Type: text/plain; charset="utf-8" From: Deepti Jaggi Add Nord SA8797P SoC ID to socinfo driver. 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Reviewed-by: Konrad Dybcio Signed-off-by: Shawn Guo --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 5c8bd29dfac4..ef29d4ad3c7d 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -194,6 +194,7 @@ static const char *const pmic_models[] =3D { [91] =3D "PMIV0108", [92] =3D "PMK8850", [93] =3D "PMH0101", + [94] =3D "PMAU0102", [95] =3D "SMB2370", [96] =3D "PMH0104", [97] =3D "PMH0110", --=20 2.43.0 From nobody Mon May 25 02:57:20 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E4A1305665 for ; Tue, 19 May 2026 06:35:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo Reviewed-by: Harshal Dev --- .../devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-en= gine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-eng= ine.yaml index ccb6b8dd8e11..c497528826a4 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.ya= ml +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.ya= ml @@ -16,6 +16,7 @@ properties: - qcom,eliza-inline-crypto-engine - qcom,kaanapali-inline-crypto-engine - qcom,milos-inline-crypto-engine + - qcom,nord-inline-crypto-engine - qcom,qcs8300-inline-crypto-engine - qcom,sa8775p-inline-crypto-engine - qcom,sc7180-inline-crypto-engine @@ -62,6 +63,7 @@ allOf: enum: - qcom,eliza-inline-crypto-engine - qcom,milos-inline-crypto-engine + - qcom,nord-inline-crypto-engine =20 then: required: --=20 2.43.0 From nobody Mon May 25 02:57:20 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D8CD31B83B for ; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-134cbdcf140sm22614537c88.5.2026.05.18.23.35.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 23:35:53 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Dmitry Baryshkov , Bartosz Golaszewski , Deepti Jaggi , Harshal Dev , Herbert Xu , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH v2 5/8] arm64: dts: qcom: Add device tree for Nord SoC series Date: Tue, 19 May 2026 14:35:02 +0800 Message-ID: <20260519063505.883379-6-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519063505.883379-1-shengchao.guo@oss.qualcomm.com> References: <20260519063505.883379-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: i-xjPL60EbSaZnhEQ0FEKrzIVDIcTSyt X-Proofpoint-ORIG-GUID: i-xjPL60EbSaZnhEQ0FEKrzIVDIcTSyt X-Authority-Analysis: v=2.4 cv=BICDalQG c=1 sm=1 tr=0 ts=6a0c04cc cx=c_pps a=JYo30EpNSr/tUYqK9jHPoA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=ZdEj2xVSEnUl0xzea1kA:9 a=Fk4IpSoW4aLDllm1B1p-:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA2MiBTYWx0ZWRfXzzGEOKPdSA9e NI6rtHH8rfBFb7iAI1BiguamEYl/drFhxTe9aVZn/Bz1HvbAPL54BBNtaoe+In4G3QfMZAesOS+ O59jZgtw1EJLV9/+0v69MDDB8NZMlv0B//yEVME2G1HXkUeG7Pctmc3dh6vR/qmzymQ4l9AHFa+ yxKje4ABtUxQvbDSb/IsSNFkB115REhFvLbYj5yklGDSzoR1ETFYWuqn0rKwPRrJRV/F7GpdygI apd6adDM/U53dYnFC8yFV5X4+q9qRnUqOZaZZVgmMbu9plpK4Z4O+lwd1PE8HB0AsBG+i8bVfoJ LOhKLvWZrAOYfkTrlIMMX4+f3FRrTyFe6OvPe7V7qHpUIoIZ3DCq3AIvU8IsONPhDAr9NjO7JSE 3gpjIQ3nsw2TbjFDEtxGPWLCUeqUeeao+PzSMgoyj+uxjKDq7dNlBgk0/0he50TXVbsJU2UVSIj pl7fA3klPfP2gJtfJ5w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 impostorscore=0 phishscore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190062 Content-Type: text/plain; charset="utf-8" Add base device tree include (nord.dtsi) for the Nord SoC series describing the core hardware components: - 18 Oryon (qcom,oryon-1-5) cores in three clusters, with PSCI-based power management and CPU/cluster idle states - ARM GICv3 interrupt controller with ITS - TLMM GPIO/pinctrl controller - 8 TSENS thermal sensors with thermal zones - 3 APPS SMMU-500 instances - 3 QUPv3 GENI SE QUP blocks - PDP SCMI channel and mailbox - Watchdog, TRNG and TCSR - Reserved memory, CMD-DB and firmware SCM - PSCI and architected timers Co-developed-by: Deepti Jaggi Signed-off-by: Deepti Jaggi Co-developed-by: Bartosz Golaszewski Signed-off-by: Bartosz Golaszewski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/nord.dtsi | 4511 ++++++++++++++++++++++++++++ 1 file changed, 4511 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/nord.dtsi diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/= nord.dtsi new file mode 100644 index 000000000000..b425a91a7890 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/nord.dtsi @@ -0,0 +1,4511 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include + +/ { + interrupt-parent =3D <&intc>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + power-domains =3D <&cpu0_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_0>; + clocks =3D <&cpu_perf 0>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x100>; + enable-method =3D "psci"; + power-domains =3D <&cpu1_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_0>; + clocks =3D <&cpu_perf 0>; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x200>; + enable-method =3D "psci"; + power-domains =3D <&cpu2_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_0>; + clocks =3D <&cpu_perf 0>; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x300>; + enable-method =3D "psci"; + power-domains =3D <&cpu3_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_0>; + clocks =3D <&cpu_perf 0>; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x400>; + enable-method =3D "psci"; + power-domains =3D <&cpu4_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_0>; + clocks =3D <&cpu_perf 0>; + }; + + cpu5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x500>; + enable-method =3D "psci"; + power-domains =3D <&cpu5_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_0>; + clocks =3D <&cpu_perf 0>; + }; + + cpu6: cpu@10000 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x10000>; + power-domains =3D <&cpu6_pd>; + power-domain-names =3D "psci"; + enable-method =3D "psci"; + next-level-cache =3D <&l2_10000>; + clocks =3D <&cpu_perf 1>; + + l2_10000: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + cpu7: cpu@10100 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x10100>; + enable-method =3D "psci"; + power-domains =3D <&cpu7_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_10000>; + clocks =3D <&cpu_perf 1>; + }; + + cpu8: cpu@10200 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x10200>; + enable-method =3D "psci"; + power-domains =3D <&cpu8_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_10000>; + clocks =3D <&cpu_perf 1>; + }; + + cpu9: cpu@10300 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x10300>; + enable-method =3D "psci"; + power-domains =3D <&cpu9_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_10000>; + clocks =3D <&cpu_perf 1>; + }; + + cpu10: cpu@10400 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x10400>; + enable-method =3D "psci"; + power-domains =3D <&cpu10_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_10000>; + clocks =3D <&cpu_perf 1>; + }; + + cpu11: cpu@10500 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x10500>; + enable-method =3D "psci"; + power-domains =3D <&cpu11_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_10000>; + clocks =3D <&cpu_perf 1>; + }; + + cpu12: cpu@20000 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x20000>; + enable-method =3D "psci"; + power-domains =3D <&cpu12_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_20000>; + clocks =3D <&cpu_perf 2>; + + l2_20000: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + cpu13: cpu@20100 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x20100>; + enable-method =3D "psci"; + power-domains =3D <&cpu13_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_20000>; + clocks =3D <&cpu_perf 2>; + }; + + cpu14: cpu@20200 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x20200>; + enable-method =3D "psci"; + power-domains =3D <&cpu14_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_20000>; + clocks =3D <&cpu_perf 2>; + }; + + cpu15: cpu@20300 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x20300>; + enable-method =3D "psci"; + power-domains =3D <&cpu15_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_20000>; + clocks =3D <&cpu_perf 2>; + }; + + cpu16: cpu@20400 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x20400>; + enable-method =3D "psci"; + power-domains =3D <&cpu16_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_20000>; + clocks =3D <&cpu_perf 2>; + }; + + cpu17: cpu@20500 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x20500>; + enable-method =3D "psci"; + power-domains =3D <&cpu17_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_20000>; + clocks =3D <&cpu_perf 2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + + core4 { + cpu =3D <&cpu4>; + }; + + core5 { + cpu =3D <&cpu5>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu6>; + }; + + core1 { + cpu =3D <&cpu7>; + }; + + core2 { + cpu =3D <&cpu8>; + }; + + core3 { + cpu =3D <&cpu9>; + }; + + core4 { + cpu =3D <&cpu10>; + }; + + core5 { + cpu =3D <&cpu11>; + }; + }; + + cluster2 { + core0 { + cpu =3D <&cpu12>; + }; + + core1 { + cpu =3D <&cpu13>; + }; + + core2 { + cpu =3D <&cpu14>; + }; + + core3 { + cpu =3D <&cpu15>; + }; + + core4 { + cpu =3D <&cpu16>; + }; + + core5 { + cpu =3D <&cpu17>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + core_off_c4: cluster-c4 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "retention"; + entry-latency-us =3D <93>; + exit-latency-us =3D <129>; + min-residency-us =3D <560>; + arm,psci-suspend-param =3D <0x00000003>; + }; + }; + + domain-idle-states { + cluster_pwr_dn: cluster-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x01000053>; + entry-latency-us =3D <2150>; + exit-latency-us =3D <1983>; + min-residency-us =3D <9144>; + }; + + domain_ss3: domain-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x02000153>; + entry-latency-us =3D <2800>; + exit-latency-us =3D <4400>; + min-residency-us =3D <10150>; + }; + }; + }; + + firmware: firmware { + scm { + compatible =3D "qcom,scm-nord", + "qcom,scm"; + qcom,dload-mode =3D <&tcsr 0x79000>; + }; + + pdp_scmi: scmi { + compatible =3D "arm,scmi"; + mboxes =3D <&pdp0_mbox 0>, + <&pdp0_mbox 11>, + <&pdp0_mbox 1>; + mbox-names =3D "tx", + "tx_reply", + "rx"; + shmem =3D <&pdp0_a2p>, + <&pdp0_p2a>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu_perf: protocol@13 { + reg =3D <0x13>; + #clock-cells =3D <1>; + }; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + /* Size will be updated by bootloader */ + reg =3D <0x0 0x80000000 0x0 0x0>; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + cpu0_pd: power-domain-cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster0_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu1_pd: power-domain-cpu1 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster0_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu2_pd: power-domain-cpu2 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster0_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu3_pd: power-domain-cpu3 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster0_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu4_pd: power-domain-cpu4 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster0_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu5_pd: power-domain-cpu5 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster0_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu6_pd: power-domain-cpu6 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster1_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu7_pd: power-domain-cpu7 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster1_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu8_pd: power-domain-cpu8 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster1_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu9_pd: power-domain-cpu9 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster1_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu10_pd: power-domain-cpu10 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster1_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu11_pd: power-domain-cpu11 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster1_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu12_pd: power-domain-cpu12 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster2_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu13_pd: power-domain-cpu13 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster2_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu14_pd: power-domain-cpu14 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster2_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu15_pd: power-domain-cpu15 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster2_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu16_pd: power-domain-cpu16 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster2_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu17_pd: power-domain-cpu17 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster2_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cluster0_pd: power-domain-cluster0 { + #power-domain-cells =3D <0>; + power-domains =3D <&system_pd>; + domain-idle-states =3D <&cluster_pwr_dn>; + }; + + cluster1_pd: power-domain-cluster1 { + #power-domain-cells =3D <0>; + power-domains =3D <&system_pd>; + domain-idle-states =3D <&cluster_pwr_dn>; + }; + + cluster2_pd: power-domain-cluster2 { + #power-domain-cells =3D <0>; + power-domains =3D <&system_pd>; + domain-idle-states =3D <&cluster_pwr_dn>; + }; + + system_pd: power-domain-system { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&domain_ss3>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + cpucp_scandump_mem: cpucp-scandump-region@80000000 { + reg =3D <0x0 0x80000000 0x0 0x800000>; + no-map; + }; + + tme_sail_mem: tme-sail-region@81ff0000 { + reg =3D <0x0 0x81ff0000 0x0 0x10000>; + no-map; + }; + + tz_sail_mailbox_mem: tz-sail-mailbox-region@82000000 { + reg =3D <0x0 0x82000000 0x0 0x8000>; + no-map; + }; + + sail_mailbox_mem: sail-mailbox-region@82008000 { + reg =3D <0x0 0x82008000 0x0 0x1f8000>; + no-map; + }; + + sail_ota_mem: sail-ota-region@82200000 { + reg =3D <0x0 0x82200000 0x0 0x5ff000>; + no-map; + }; + + sail_vdt_mem: sail-vdt-region@827ff000 { + reg =3D <0x0 0x827ff000 0x0 0x1000>; + no-map; + }; + + hyp_mem: hyp-region@82800000 { + reg =3D <0x0 0x82800000 0x0 0x2400000>; + no-map; + }; + + deepsleep_mem: deepsleep-region@84c00000 { + reg =3D <0x0 0x84c00000 0x0 0x800000>; + no-map; + }; + + deepsleep_backup_mem: deepsleep-backup-region@86a00000 { + reg =3D <0x0 0x86a00000 0x0 0x200000>; + no-map; + }; + + soccp_fe_vm_0: soccp-fe-vm-0-region@86c00000 { + reg =3D <0x0 0x86c00000 0x0 0xac000>; + no-map; + }; + + soccp_fe_vm_1: soccp-fe-vm-1-region@86cac000 { + reg =3D <0x0 0x86cac000 0x0 0x18d000>; + no-map; + }; + + soccp_fe_vm_2: soccp-fe-vm-2-region@86e39000 { + reg =3D <0x0 0x86e39000 0x0 0x1c7000>; + no-map; + }; + + tme_crash_dump_mem: tme-crash-dump-region@87000000 { + reg =3D <0x0 0x87000000 0x0 0xa0000>; + no-map; + }; + + pdp0_a2p: scmi-shmem@87060180 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x87608180 0x0 0x80>; + no-map; + }; + + tme_log_mem: tme-log-region@87140000 { + reg =3D <0x0 0x87140000 0x0 0x4000>; + no-map; + }; + + aop_cmd_db_p_mem: aop-cmd-db-p-region@87148000 { + compatible =3D "qcom,cmd-db"; + reg =3D <0x0 0x87148000 0x0 0x20000>; + no-map; + }; + + nsp_sync_buffer_mem: nsp-sync-buffer-region@871ff000 { + reg =3D <0x0 0x871ff000 0x0 0x1000>; + no-map; + }; + + ddr_training_checksum_data_mem: ddr-training-checksum-data-region@872000= 00 { + reg =3D <0x0 0x87200000 0x0 0x2000>; + no-map; + }; + + xbl_dtlog_mem: xbl-dtlog-region@87202000 { + reg =3D <0x0 0x87202000 0x0 0x60000>; + no-map; + }; + + xbl_ramdump_mem: xbl-ramdump-region@87262000 { + reg =3D <0x0 0x87262000 0x0 0x1c0000>; + no-map; + }; + + uefi_log: uefi-log@87442000 { + reg =3D <0x0 0x87442000 0x0 0x10000>; + no-map; + }; + + secdata_apss_mem: secdata-apss-region@87452000 { + reg =3D <0x0 0x87452000 0x0 0x1000>; + no-map; + }; + + antireplay_emulation_mem: antireplay-emulation-region@87453000 { + reg =3D <0x0 0x87453000 0x0 0x1000>; + no-map; + }; + + soccp_sdi_mem: soccp-sdi-region@87454000 { + reg =3D <0x0 0x87454000 0x0 0x40000>; + no-map; + }; + + hyp_mem_database_mem: hyp-mem-database-region@87494000 { + reg =3D <0x0 0x87494000 0x0 0x60000>; + no-map; + }; + + pmic_mini_dump_mem: pmic-mini-dump-region@874f4000 { + reg =3D <0x0 0x874f4000 0x0 0x80000>; + no-map; + }; + + qup_fw_mem: qup-fw-region@87574000 { + reg =3D <0x0 0x87574000 0x0 0x20000>; + no-map; + }; + + softsku_mem: softsku-region@87594000 { + reg =3D <0x0 0x87594000 0x0 0x9000>; + no-map; + }; + + resource_scheduler_mem: resource-scheduler-region@8759d000 { + reg =3D <0x0 0x8759d000 0x0 0x20000>; + no-map; + }; + + pdp_ns_mem: pdp-ns-mem-region@87600000 { + reg =3D <0x0 0x87600000 0x0 0x8000>, + <0x0 0x87609000 0x0 0x1f7000>; + no-map; + }; + + pdp0_p2a: scmi-shmem@87608000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x87608000 0x0 0x80>; + no-map; + }; + + tz_stat_mem: tz-stat-region@87a00000 { + reg =3D <0x0 0x87a00000 0x0 0x100000>; + no-map; + }; + + qdss_apps_mem: qdss-apps-region@87b00000 { + reg =3D <0x0 0x87b00000 0x0 0x2000000>; + no-map; + }; + + global_sync_mem: global-sync-region@89f00000 { + reg =3D <0x0 0x89f00000 0x0 0x400000>; + no-map; + }; + + tzffi_mem: tzffi-region@8a300000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0x8a300000 0x0 0x1400000>; + no-map; + }; + + gunyah_md_mem: gunyah-md-region@8b700000 { + reg =3D <0x0 0x8b700000 0x0 0x80000>; + no-map; + }; + + flashless_qntm_tool_mem: flashless-qntm-tool-region@8b780000 { + reg =3D <0x0 0x8b780000 0x0 0x182000>; + no-map; + }; + + ipa_fw_mem: ipa-fw-region@8bb00000 { + reg =3D <0x0 0x8bb00000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi-region@8bb10000 { + reg =3D <0x0 0x8bb10000 0x0 0xa000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode-region@8bb1a000 { + reg =3D <0x0 0x8bb1a000 0x0 0x2000>; + no-map; + }; + + gpu_microcode_2_mem: gpu-microcode-2-region@8bb1c000 { + reg =3D <0x0 0x8bb1c000 0x0 0x2000>; + no-map; + }; + + soccp_mem: soccp-region@8bc00000 { + reg =3D <0x0 0x8bc00000 0x0 0x300000>; + no-map; + }; + + cvp_mem: cvp-region@8d100000 { + reg =3D <0x0 0x8d100000 0x0 0x800000>; + no-map; + }; + + cdsp0_mem: cdsp0-region@8d900000 { + reg =3D <0x0 0x8d900000 0x0 0x2300000>; + no-map; + }; + + cdsp1_mem: cdsp1-region@8fc00000 { + reg =3D <0x0 0x8fc00000 0x0 0x2300000>; + no-map; + }; + + cdsp2_mem: cdsp2-region@91f00000 { + reg =3D <0x0 0x91f00000 0x0 0x2300000>; + no-map; + }; + + cdsp3_mem: cdsp3-region@94200000 { + reg =3D <0x0 0x94200000 0x0 0x2300000>; + no-map; + }; + + hpass_dsp0_mem: hpass-dsp0-region@96500000 { + reg =3D <0x0 0x96500000 0x0 0x2800000>; + no-map; + }; + + hpass_dsp1_mem: hpass-dsp1-region@98d00000 { + reg =3D <0x0 0x98d00000 0x0 0x2800000>; + no-map; + }; + + hpass_dsp2_mem: hpass-dsp2-region@9b500000 { + reg =3D <0x0 0x9b500000 0x0 0x2800000>; + no-map; + }; + + q6_cdsp0_dtb_mem: q6-cdsp0-dtb-region@9dd00000 { + reg =3D <0x0 0x9dd00000 0x0 0x80000>; + no-map; + }; + + q6_cdsp1_dtb_mem: q6-cdsp1-dtb-region@9dd80000 { + reg =3D <0x0 0x9dd80000 0x0 0x80000>; + no-map; + }; + + q6_cdsp2_dtb_mem: q6-cdsp2-dtb-region@9de00000 { + reg =3D <0x0 0x9de00000 0x0 0x80000>; + no-map; + }; + + q6_cdsp3_dtb_mem: q6-cdsp3-dtb-region@9de80000 { + reg =3D <0x0 0x9de80000 0x0 0x80000>; + no-map; + }; + + hpass_dsp0_dtb_mem: hpass-dsp0-dtb-region@9df00000 { + reg =3D <0x0 0x9df00000 0x0 0x80000>; + no-map; + }; + + hpass_dsp1_dtb_mem: hpass-dsp1-dtb-region@9df80000 { + reg =3D <0x0 0x9df80000 0x0 0x80000>; + no-map; + }; + + hpass_dsp2_dtb_mem: hpass-dsp2-dtb-region@9e000000 { + reg =3D <0x0 0x9e000000 0x0 0x100000>; + no-map; + }; + + camera_icp_1_mem: camera-icp-1-region@9e100000 { + reg =3D <0x0 0x9e100000 0x0 0x800000>; + no-map; + }; + + camera_icp_2_mem: camera-icp-2-region@9e900000 { + reg =3D <0x0 0x9e900000 0x0 0x800000>; + no-map; + }; + + camera_qup_1_mem: camera-qup-1-region@9f100000 { + reg =3D <0x0 0x9f100000 0x0 0x200000>; + no-map; + }; + + camera_qup_2_mem: camera-qup-2-region@9f300000 { + reg =3D <0x0 0x9f300000 0x0 0x200000>; + no-map; + }; + + video_mem: video-region@9f500000 { + reg =3D <0x0 0x9f500000 0x0 0xc00000>; + no-map; + }; + + pil_umd_reserved: mdt-load-region@a0100000 { + reg =3D <0x0 0xa0100000 0x0 0x100000>; + no-map; + }; + + mm_dspq: mm-dspq-region@ba200000 { + reg =3D <0x0 0xba200000 0x0 0x200000>; + no-map; + }; + + display_config_reserved: display-config-region@ba400000 { + reg =3D <0x0 0xba400000 0x0 0xa00000>; + no-map; + }; + + mm_calibration_data_mem: mm-calibration-data-region@bae00000 { + reg =3D <0x0 0xbae00000 0x0 0x800000>; + no-map; + }; + + audio_config_mem: audio-config-region@bb600000 { + reg =3D <0x0 0xbb600000 0x0 0xa00000>; + no-map; + }; + + dare_tz_mem: dare-tz-region@bc000000 { + reg =3D <0x0 0xbc000000 0x0 0xa300000>; + no-map; + }; + + hpass_rpc_remote_heap_mem: hpass-rpc-remote-heap-region@d4600000 { + reg =3D <0x0 0xd4600000 0x0 0x800000>; + no-map; + }; + + mdf_mem: mdf-region@d4e00000 { + reg =3D <0x0 0xd4e00000 0x0 0x2000000>; + no-map; + }; + + firmware_mem: firmware-region@d6e00000 { + reg =3D <0x0 0xd6e00000 0x0 0x800000>; + no-map; + }; + + firmware_shared_mem: firmware-shared-region@d7650000 { + reg =3D <0x0 0xd7650000 0x0 0x180000>; + no-map; + }; + + firmware_logs_mem: firmware-logs-region@d77d0000 { + reg =3D <0x0 0xd77d0000 0x0 0x20000>; + no-map; + }; + + sail_p_mem: sail-p-region@8c0000000 { + reg =3D <0x8 0xc0000000 0x0 0x8000000>; + no-map; + }; + + reserved_mem2: reserved-region@8c8000000 { + reg =3D <0x8 0xc8000000 0x0 0x18000000>; + no-map; + }; + + dump_mem: mem-dump-region { + alloc-ranges =3D <0x0 0x00000000 0x0 0xffffffff>; + size =3D <0x0 0x79b0000>; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges =3D <0 0 0 0 0x10 0>; + ranges =3D <0 0 0 0 0x10 0>; + + qupv3_2: geniqup@8c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x008c0000 0x0 0x2000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + iommus =3D <&apps_smmu_0 0x15a3 0x0>; + ranges; + + i2c14: i2c@880000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00880000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + spi14: spi@880000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00880000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart14: serial@880000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00880000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c15: i2c@884000 { + reg =3D <0x0 0x00884000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + spi15: spi@884000 { + reg =3D <0x0 0x00884000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart15: serial@884000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x00884000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c16: i2c@888000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00888000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + spi16: spi@888000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00888000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart16: serial@888000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00888000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c17: i2c@88c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x0088c000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + spi17: spi@88c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x0088c000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart17: serial@88c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x0088c000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c18: i2c@890000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00890000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + spi18: spi@890000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00890000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart18: serial@890000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00890000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c19: i2c@894000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00894000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + spi19: spi@894000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00894000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart19: serial@894000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00894000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c20: i2c@898000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00898000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + spi20: spi@898000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00898000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart20: serial@898000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00898000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + }; + + qupv3_0: geniqup@9c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x009c0000 0x0 0x2000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + iommus =3D <&apps_smmu_2 0x1003 0x0>; + ranges; + + i2c0: i2c@980000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00980000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + spi0: spi@980000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00980000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart0: serial@980000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00980000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c1: i2c@984000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00984000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + spi1: spi@984000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00984000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart1: serial@984000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00984000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c2: i2c@988000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00988000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + spi2: spi@988000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00988000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart2: serial@988000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00988000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c3: i2c@98c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x0098c000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + spi3: spi@98c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x0098c000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart3: serial@98c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x0098c000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c4: i2c@990000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00990000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + spi4: spi@990000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00990000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart4: serial@990000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00990000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c5: i2c@994000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00994000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + spi5: spi@994000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00994000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart5: serial@994000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00994000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + }; + + qupv3_1: geniqup@ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x00ac0000 0x0 0x2000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + iommus =3D <&apps_smmu_2 0x1043 0x0>; + ranges; + + i2c7: i2c@a80000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a80000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + spi7: spi@a80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a80000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart7: serial@a80000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a80000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c8: i2c@a84000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a84000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + spi8: spi@a84000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a84000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart8: serial@a84000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a84000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c9: i2c@a88000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a88000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart9: serial@a88000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a88000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c10: i2c@a8c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a8c000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart10: serial@a8c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a8c000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c11: i2c@a90000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a90000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + spi11: spi@a90000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a90000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart11: serial@a90000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a90000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c12: i2c@a94000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a94000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + spi12: spi@a94000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a94000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart12: serial@a94000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a94000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c13: i2c@a98000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a98000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + spi13: spi@a98000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a98000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart13: serial@a98000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a98000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + }; + + rng: rng@10c3000 { + compatible =3D "qcom,nord-trng", + "qcom,trng"; + reg =3D <0x0 0x010c3000 0x0 0x1000>; + }; + + ufs_mem_hc: ufshc@1d44000 { + compatible =3D "qcom,nord-ufshc", + "qcom,ufshc", + "jedec,ufs-2.0"; + interrupts =3D ; + lanes-per-direction =3D <2>; + iommus =3D <&apps_smmu_0 0x14c0 0x0>; + dma-coherent; + msi-parent =3D <&gic_its 0x14c0>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01f40000 0x0 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsr: syscon@1f60000 { + compatible =3D "qcom,nord-tcsr", + "syscon"; + reg =3D <0x0 0x01f60000 0x0 0xa0000>; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,nord-pdc", + "qcom,pdc"; + reg =3D <0x0 0x0b220000 0x0 0x10000>; + qcom,pdc-ranges =3D <0 745 43>, <67 543 31>, + <98 609 32>, <130 717 12>, + <142 251 5>, <147 796 16>; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&intc>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c22c000 { + compatible =3D "qcom,nord-tsens", + "qcom,tsens-v2"; + reg =3D <0x0 0x0c22c000 0x0 0x1000>, + <0x0 0x0c222000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <16>; + #thermal-sensor-cells =3D <1>; + }; + + tsens1: thermal-sensor@c22d000 { + compatible =3D "qcom,nord-tsens", + "qcom,tsens-v2"; + reg =3D <0x0 0x0c22d000 0x0 0x1000>, + <0x0 0x0c223000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <16>; + #thermal-sensor-cells =3D <1>; + }; + + tsens2: thermal-sensor@c22e000 { + compatible =3D "qcom,nord-tsens", + "qcom,tsens-v2"; + reg =3D <0x0 0x0c22e000 0x0 0x1000>, + <0x0 0x0c224000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <16>; + #thermal-sensor-cells =3D <1>; + }; + + tsens3: thermal-sensor@c22f000 { + compatible =3D "qcom,nord-tsens", + "qcom,tsens-v2"; + reg =3D <0x0 0x0c22f000 0x0 0x1000>, + <0x0 0x0c225000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <16>; + #thermal-sensor-cells =3D <1>; + }; + + tsens4: thermal-sensor@c230000 { + compatible =3D "qcom,nord-tsens", + "qcom,tsens-v2"; + reg =3D <0x0 0x0c230000 0x0 0x1000>, + <0x0 0x0c226000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <16>; + #thermal-sensor-cells =3D <1>; + }; + + tsens5: thermal-sensor@c231000 { + compatible =3D "qcom,nord-tsens", + "qcom,tsens-v2"; + reg =3D <0x0 0x0c231000 0x0 0x1000>, + <0x0 0x0c227000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <16>; + #thermal-sensor-cells =3D <1>; + }; + + tsens6: thermal-sensor@c232000 { + compatible =3D "qcom,nord-tsens", + "qcom,tsens-v2"; + reg =3D <0x0 0x0c232000 0x0 0x1000>, + <0x0 0x0c228000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <16>; + #thermal-sensor-cells =3D <1>; + }; + + tsens7: thermal-sensor@c233000 { + compatible =3D "qcom,nord-tsens", + "qcom,tsens-v2"; + reg =3D <0x0 0x0c233000 0x0 0x1000>, + <0x0 0x0c229000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <16>; + #thermal-sensor-cells =3D <1>; + }; + + tlmm: pinctrl@f100000 { + compatible =3D "qcom,nord-tlmm"; + reg =3D <0x0 0x0f100000 0x0 0xc0000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 181>; + wakeup-parent =3D <&pdc>; + }; + + apps_smmu_0: iommu@15a00000 { + compatible =3D "qcom,nord-smmu-500", + "qcom,smmu-500", + "arm,mmu-500"; + reg =3D <0x0 0x15a00000 0x0 0x100000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + dma-coherent; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + apps_smmu_1: iommu@15c00000 { + compatible =3D "qcom,nord-smmu-500", + "qcom,smmu-500", + "arm,mmu-500"; + reg =3D <0x0 0x15c00000 0x0 0x100000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + dma-coherent; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + apps_smmu_2: iommu@15e00000 { + compatible =3D "qcom,nord-smmu-500", + "qcom,smmu-500", + "arm,mmu-500"; + reg =3D <0x0 0x15e00000 0x0 0x100000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + dma-coherent; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + intc: interrupt-controller@17000000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x17000000 0x0 0x10000>, /* GICD */ + <0x0 0x17080000 0x0 0x480000>; /* GICR * 18 */ + interrupts =3D ; + #interrupt-cells =3D <3>; + interrupt-controller; + #redistributor-regions =3D <1>; + redistributor-stride =3D <0x0 0x40000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gic_its: msi-controller@17040000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x17040000 0x0 0x40000>; + msi-controller; + #msi-cells =3D <1>; + }; + }; + + pdp0_mbox: mailbox@17610000 { + compatible =3D "qcom,nord-cpucp-mbox", + "qcom,x1e80100-cpucp-mbox"; + reg =3D <0x0 0x17610000 0x0 0x4c08>, + <0x0 0x19980000 0x0 0x300>; + #mbox-cells =3D <1>; + interrupts =3D ; + }; + + memtimer: timer@17810000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x17810000 0x0 0x1000>; + ranges =3D <0x0 0x0 0x0 0x20000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + frame@17811000 { + reg =3D <0x17811000 0x1000>, + <0x17812000 0x1000>; + interrupts =3D , + ; + frame-number =3D <0>; + }; + + frame@17813000 { + reg =3D <0x17813000 0x1000>; + interrupts =3D ; + frame-number =3D <1>; + + status =3D "disabled"; + }; + + frame@17815000 { + reg =3D <0x17815000 0x1000>; + interrupts =3D ; + frame-number =3D <2>; + + status =3D "disabled"; + }; + + frame@17817000 { + reg =3D <0x17817000 0x1000>; + interrupts =3D ; + frame-number =3D <3>; + + status =3D "disabled"; + }; + + frame@17819000 { + reg =3D <0x17819000 0x1000>; + interrupts =3D ; + frame-number =3D <4>; + + status =3D "disabled"; + }; + + frame@1781b000 { + reg =3D <0x1781b000 0x1000>; + interrupts =3D ; + frame-number =3D <5>; + + status =3D "disabled"; + }; + + frame@1781d000 { + reg =3D <0x1781d000 0x1000>; + interrupts =3D ; + frame-number =3D <6>; + + status =3D "disabled"; + }; + }; + + watchdog@17826000 { + compatible =3D "qcom,apss-wdt-nord", + "qcom,kpss-wdt"; + reg =3D <0x0 0x17826000 0x0 0x1000>; + clocks =3D <&sleep_clk>; + interrupts =3D ; + }; + }; + + arch_timer: timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + thermal_zones: thermal-zones { + ddr-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-2-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-3-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-4-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-5-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpullc-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-2-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-3-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-4-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 12>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-5-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 13>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpullc-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 14>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + ddr-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 15>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + ddr-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-2-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-3-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-4-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-5-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpullc-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-2-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-3-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-4-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 12>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-5-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 13>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpullc-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 14>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + ddr-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 15>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + amux-2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-2-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-3-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-4-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-5-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpullc-2-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhvx-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhmx-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhvx-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhmx-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhvx-2-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 12>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhmx-2-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 13>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + pcie-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 15>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + amux-3-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-2-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-3-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-4-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-5-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpullc-2-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhvx-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhmx-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhvx-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhmx-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhvx-2-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 12>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhmx-2-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 13>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + pcie-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 15>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-0-2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-0-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-0-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-1-2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-1-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-1-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-2-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-2-2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-2-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-2-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-3-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 12>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-3-2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 13>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-3-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 14>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-3-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 15>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-0-3-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-0-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-0-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-1-3-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-1-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-1-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-2-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-2-3-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-2-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-2-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-3-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 12>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-3-3-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 13>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-3-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 14>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-3-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 15>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + amux-6-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpu-0-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cv-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + video-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + camera-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + ddr-2-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + ddr-3-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-0-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 12>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-1-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 13>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-2-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 14>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpu-0-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 15>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + amux-7-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-0-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-1-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-2-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpu-0-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-1-2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpu-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cv-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + video-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + camera-2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + ddr-2-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + ddr-3-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 12>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-1-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 13>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-134cbdcf140sm22614537c88.5.2026.05.18.23.35.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 23:35:57 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Dmitry Baryshkov , Bartosz Golaszewski , Deepti Jaggi , Harshal Dev , Herbert Xu , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH v2 6/8] arm64: dts: qcom: Add device tree for Nord SA8797P SoC Date: Tue, 19 May 2026 14:35:03 +0800 Message-ID: <20260519063505.883379-7-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519063505.883379-1-shengchao.guo@oss.qualcomm.com> References: <20260519063505.883379-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=JKULdcKb c=1 sm=1 tr=0 ts=6a0c04d0 cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=uQd1CpjfprTzC7XeMz8A:9 a=vr4QvYf-bLy2KjpDp97w:22 X-Proofpoint-GUID: 8HhSr9yhoAWdB9Bu_0A76j7y_BRmbwfH X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA2MiBTYWx0ZWRfX8fFxWdFzUqxj am0IAReEOiFX/eMiD5iyFTMHH+LCgEpvpIJEdCn8nu3kujUiGoIUUHLVGEVI1gxzW51R6BHgZLR Gbiq9ROaVCqWtJ3/EEESASmTpchQolMeimY1ti0T3ELRSQ5uGM2s99i1JlnfdhDES1UOxsZsUSx L0FYd7dBqhPwlBotiy8tZqQK0WzH6lT59JG3pqR0Ur6VLwJQmVbR8geuZVIQfVIdPPSZYX6tAzT bMTUUtblV4xiOx+moNbfrPPu0qkCuMK4LiEPWF78e0x9WL1ZO5vPCKxpZZmXyduNDlh0czGplHH i9/GHEe5vlDHLAMNoe2qED1ERRTtnkWOpDoZ9GRnPu00cPMA+85v2j82nQnZOYuWxiZuCvnuY4M qXXt5iamtyabgss8C/n9Q8IfkENJ8FBMkvxBU6txziwSl2JWMB3xM/6ZlCwFRrao/xg0pwhkqLf tk6QzZNfscrm5CbfUBg== X-Proofpoint-ORIG-GUID: 8HhSr9yhoAWdB9Bu_0A76j7y_BRmbwfH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 phishscore=0 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190062 Content-Type: text/plain; charset="utf-8" From: Deepti Jaggi Add SoC-level device tree include for SA8797P, an automotive variant of the Nord SoC family. The dtsi covers: - 64 SCMI shared memory regions reserved at 0xd7600000-0xd763f000 for SMC-based firmware communication channels - Three QUPV3 GENI SE QUP blocks (qupv3_0/1/2) with UART controllers using SCMI power and performance domains via scmi11 - UFS host controller with SCMI power domain via scmi3 - GPU SMMU node with SCMI power domain via scmi15 Also introduce scmi-common.dtsi providing the firmware-level SCMI channel nodes (scmi0, scmi3, scmi11, scmi15, scmi23) shared across SCMI based SoCs, each carrying clock, power domain, performance, and sensor protocol sub-nodes. Signed-off-by: Deepti Jaggi Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/nord-sa8797p.dtsi | 937 ++++++++++ arch/arm64/boot/dts/qcom/scmi-common.dtsi | 1918 ++++++++++++++++++++ 2 files changed, 2855 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/nord-sa8797p.dtsi create mode 100644 arch/arm64/boot/dts/qcom/scmi-common.dtsi diff --git a/arch/arm64/boot/dts/qcom/nord-sa8797p.dtsi b/arch/arm64/boot/d= ts/qcom/nord-sa8797p.dtsi new file mode 100644 index 000000000000..343de7512928 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/nord-sa8797p.dtsi @@ -0,0 +1,937 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include "nord.dtsi" +#include "scmi-common.dtsi" + +&i2c0 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 0>, + <&scmi11_dvfs 0>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c1 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 1>, + <&scmi11_dvfs 1>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c2 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 2>, + <&scmi11_dvfs 2>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c3 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 3>, + <&scmi11_dvfs 3>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c4 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 4>, + <&scmi11_dvfs 4>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c5 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 5>, + <&scmi11_dvfs 5>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c7 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 7>, + <&scmi11_dvfs 7>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c8 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 8>, + <&scmi11_dvfs 8>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c9 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 9>, + <&scmi11_dvfs 9>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c10 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 10>, + <&scmi11_dvfs 10>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c11 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 11>, + <&scmi11_dvfs 11>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c12 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 12>, + <&scmi11_dvfs 12>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c13 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 13>, + <&scmi11_dvfs 13>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c14 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 14>, + <&scmi11_dvfs 14>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c15 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 15>, + <&scmi11_dvfs 15>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c16 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 16>, + <&scmi11_dvfs 16>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c17 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 17>, + <&scmi11_dvfs 17>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c18 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 18>, + <&scmi11_dvfs 18>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c19 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 19>, + <&scmi11_dvfs 19>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c20 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 20>, + <&scmi11_dvfs 20>; + power-domain-names =3D "power", + "perf"; +}; + +&qupv3_0 { + compatible =3D "qcom,sa8797p-geni-se-qup", + "qcom,sa8255p-geni-se-qup"; +}; + +&qupv3_1 { + compatible =3D "qcom,sa8797p-geni-se-qup", + "qcom,sa8255p-geni-se-qup"; +}; + +&qupv3_2 { + compatible =3D "qcom,sa8797p-geni-se-qup", + "qcom,sa8255p-geni-se-qup"; +}; + +&reserved_memory { + shmem0: scmi-shmem@d7600000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7600000 0x0 0x1000>; + no-map; + }; + + shmem1: scmi-shmem@d7601000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7601000 0x0 0x1000>; + no-map; + }; + + shmem2: scmi-shmem@d7602000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7602000 0x0 0x1000>; + no-map; + }; + + shmem3: scmi-shmem@d7603000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7603000 0x0 0x1000>; + no-map; + }; + + shmem4: scmi-shmem@d7604000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7604000 0x0 0x1000>; + no-map; + }; + + shmem5: scmi-shmem@d7605000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7605000 0x0 0x1000>; + no-map; + }; + + shmem6: scmi-shmem@d7606000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7606000 0x0 0x1000>; + no-map; + }; + + shmem7: scmi-shmem@d7607000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7607000 0x0 0x1000>; + no-map; + }; + + shmem8: scmi-shmem@d7608000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7608000 0x0 0x1000>; + no-map; + }; + + shmem9: scmi-shmem@d7609000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7609000 0x0 0x1000>; + no-map; + }; + + shmem10: scmi-shmem@d760a000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd760a000 0x0 0x1000>; + no-map; + }; + + shmem11: scmi-shmem@d760b000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd760b000 0x0 0x1000>; + no-map; + }; + + shmem12: scmi-shmem@d760c000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd760c000 0x0 0x1000>; + no-map; + }; + + shmem13: scmi-shmem@d760d000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd760d000 0x0 0x1000>; + no-map; + }; + + shmem14: scmi-shmem@d760e000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd760e000 0x0 0x1000>; + no-map; + }; + + shmem15: scmi-shmem@d760f000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd760f000 0x0 0x1000>; + no-map; + }; + + shmem16: scmi-shmem@d7610000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7610000 0x0 0x1000>; + no-map; + }; + + shmem17: scmi-shmem@d7611000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7611000 0x0 0x1000>; + no-map; + }; + + shmem18: scmi-shmem@d7612000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7612000 0x0 0x1000>; + no-map; + }; + + shmem19: scmi-shmem@d7613000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7613000 0x0 0x1000>; + no-map; + }; + + shmem20: scmi-shmem@d7614000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7614000 0x0 0x1000>; + no-map; + }; + + shmem21: scmi-shmem@d7615000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7615000 0x0 0x1000>; + no-map; + }; + + shmem22: scmi-shmem@d7616000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7616000 0x0 0x1000>; + no-map; + }; + + shmem23: scmi-shmem@d7617000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7617000 0x0 0x1000>; + no-map; + }; + + shmem24: scmi-shmem@d7618000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7618000 0x0 0x1000>; + no-map; + }; + + shmem25: scmi-shmem@d7619000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7619000 0x0 0x1000>; + no-map; + }; + + shmem26: scmi-shmem@d761a000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd761a000 0x0 0x1000>; + no-map; + }; + + shmem27: scmi-shmem@d761b000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd761b000 0x0 0x1000>; + no-map; + }; + + shmem28: scmi-shmem@d761c000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd761c000 0x0 0x1000>; + no-map; + }; + + shmem29: scmi-shmem@d761d000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd761d000 0x0 0x1000>; + no-map; + }; + + shmem30: scmi-shmem@d761e000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd761e000 0x0 0x1000>; + no-map; + }; + + shmem31: scmi-shmem@d761f000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd761f000 0x0 0x1000>; + no-map; + }; + + shmem32: scmi-shmem@d7620000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7620000 0x0 0x1000>; + no-map; + }; + + shmem33: scmi-shmem@d7621000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7621000 0x0 0x1000>; + no-map; + }; + + shmem34: scmi-shmem@d7622000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7622000 0x0 0x1000>; + no-map; + }; + + shmem35: scmi-shmem@d7623000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7623000 0x0 0x1000>; + no-map; + }; + + shmem36: scmi-shmem@d7624000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7624000 0x0 0x1000>; + no-map; + }; + + shmem37: scmi-shmem@d7625000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7625000 0x0 0x1000>; + no-map; + }; + + shmem38: scmi-shmem@d7626000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7626000 0x0 0x1000>; + no-map; + }; + + shmem39: scmi-shmem@d7627000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7627000 0x0 0x1000>; + no-map; + }; + + shmem40: scmi-shmem@d7628000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7628000 0x0 0x1000>; + no-map; + }; + + shmem41: scmi-shmem@d7629000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7629000 0x0 0x1000>; + no-map; + }; + + shmem42: scmi-shmem@d762a000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd762a000 0x0 0x1000>; + no-map; + }; + + shmem43: scmi-shmem@d762b000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd762b000 0x0 0x1000>; + no-map; + }; + + shmem44: scmi-shmem@d762c000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd762c000 0x0 0x1000>; + no-map; + }; + + shmem45: scmi-shmem@d762d000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd762d000 0x0 0x1000>; + no-map; + }; + + shmem46: scmi-shmem@d762e000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd762e000 0x0 0x1000>; + no-map; + }; + + shmem47: scmi-shmem@d762f000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd762f000 0x0 0x1000>; + no-map; + }; + + shmem48: scmi-shmem@d7630000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7630000 0x0 0x1000>; + no-map; + }; + + shmem49: scmi-shmem@d7631000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7631000 0x0 0x1000>; + no-map; + }; + + shmem50: scmi-shmem@d7632000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7632000 0x0 0x1000>; + no-map; + }; + + shmem51: scmi-shmem@d7633000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7633000 0x0 0x1000>; + no-map; + }; + + shmem52: scmi-shmem@d7634000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7634000 0x0 0x1000>; + no-map; + }; + + shmem53: scmi-shmem@d7635000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7635000 0x0 0x1000>; + no-map; + }; + + shmem54: scmi-shmem@d7636000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7636000 0x0 0x1000>; + no-map; + }; + + shmem55: scmi-shmem@d7637000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7637000 0x0 0x1000>; + no-map; + }; + + shmem56: scmi-shmem@d7638000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7638000 0x0 0x1000>; + no-map; + }; + + shmem57: scmi-shmem@d7639000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7639000 0x0 0x1000>; + no-map; + }; + + shmem58: scmi-shmem@d763a000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd763a000 0x0 0x1000>; + no-map; + }; + + shmem59: scmi-shmem@d763b000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd763b000 0x0 0x1000>; + no-map; + }; + + shmem60: scmi-shmem@d763c000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd763c000 0x0 0x1000>; + no-map; + }; + + shmem61: scmi-shmem@d763d000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd763d000 0x0 0x1000>; + no-map; + }; + + shmem62: scmi-shmem@d763e000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd763e000 0x0 0x1000>; + no-map; + }; + + shmem63: scmi-shmem@d763f000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd763f000 0x0 0x1000>; + no-map; + }; +}; + +&spi0 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 0>, + <&scmi11_dvfs 0>; + power-domain-names =3D "power", + "perf"; +}; + +&spi1 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 1>, + <&scmi11_dvfs 1>; + power-domain-names =3D "power", + "perf"; +}; + +&spi2 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 2>, + <&scmi11_dvfs 2>; + power-domain-names =3D "power", + "perf"; +}; + +&spi3 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 3>, + <&scmi11_dvfs 3>; + power-domain-names =3D "power", + "perf"; +}; + +&spi4 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 4>, + <&scmi11_dvfs 4>; + power-domain-names =3D "power", + "perf"; +}; + +&spi5 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 5>, + <&scmi11_dvfs 5>; + power-domain-names =3D "power", + "perf"; +}; + +&spi7 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 7>, + <&scmi11_dvfs 7>; + power-domain-names =3D "power", + "perf"; +}; + +&spi8 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 8>, + <&scmi11_dvfs 8>; + power-domain-names =3D "power", + "perf"; +}; + +&spi11 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 11>, + <&scmi11_dvfs 11>; + power-domain-names =3D "power", + "perf"; +}; + +&spi12 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 12>, + <&scmi11_dvfs 12>; + power-domain-names =3D "power", + "perf"; +}; + +&spi13 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 13>, + <&scmi11_dvfs 13>; + power-domain-names =3D "power", + "perf"; +}; + +&spi14 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 14>, + <&scmi11_dvfs 14>; + power-domain-names =3D "power", + "perf"; +}; + +&spi15 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 15>, + <&scmi11_dvfs 15>; + power-domain-names =3D "power", + "perf"; +}; + +&spi16 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 16>, + <&scmi11_dvfs 16>; + power-domain-names =3D "power", + "perf"; +}; + +&spi17 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 17>, + <&scmi11_dvfs 17>; + power-domain-names =3D "power", + "perf"; +}; + +&spi18 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 18>, + <&scmi11_dvfs 18>; + power-domain-names =3D "power", + "perf"; +}; + +&spi19 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 19>, + <&scmi11_dvfs 19>; + power-domain-names =3D "power", + "perf"; +}; + +&spi20 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 20>, + <&scmi11_dvfs 20>; + power-domain-names =3D "power", + "perf"; +}; + +&uart0 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 0>, + <&scmi11_dvfs 0>; + power-domain-names =3D "power", + "perf"; +}; + +&uart1 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 1>, + <&scmi11_dvfs 1>; + power-domain-names =3D "power", + "perf"; +}; + +&uart2 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 2>, + <&scmi11_dvfs 2>; + power-domain-names =3D "power", + "perf"; +}; + +&uart3 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 3>, + <&scmi11_dvfs 3>; + power-domain-names =3D "power", + "perf"; +}; + +&uart4 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 4>, + <&scmi11_dvfs 4>; + power-domain-names =3D "power", + "perf"; +}; + +&uart5 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 5>, + <&scmi11_dvfs 5>; + power-domain-names =3D "power", + "perf"; +}; + +&uart7 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 7>, + <&scmi11_dvfs 7>; + power-domain-names =3D "power", + "perf"; +}; + +&uart8 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 8>, + <&scmi11_dvfs 8>; + power-domain-names =3D "power", + "perf"; +}; + +&uart9 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 9>, + <&scmi11_dvfs 9>; + power-domain-names =3D "power", + "perf"; +}; + +&uart10 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 10>, + <&scmi11_dvfs 10>; + power-domain-names =3D "power", + "perf"; +}; + +&uart11 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 11>, + <&scmi11_dvfs 11>; + power-domain-names =3D "power", + "perf"; +}; + +&uart12 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 12>, + <&scmi11_dvfs 12>; + power-domain-names =3D "power", + "perf"; +}; + +&uart13 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 13>, + <&scmi11_dvfs 13>; + power-domain-names =3D "power", + "perf"; +}; + +&uart14 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 14>, + <&scmi11_dvfs 14>; + power-domain-names =3D "power", + "perf"; +}; + +&uart15 { + compatible =3D "qcom,sa8797p-geni-debug-uart", + "qcom,sa8255p-geni-debug-uart"; + power-domains =3D <&scmi11_pd 15>, + <&scmi11_dvfs 15>; + power-domain-names =3D "power", + "perf"; +}; + +&uart16 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 16>, + <&scmi11_dvfs 16>; + power-domain-names =3D "power", + "perf"; +}; + +&uart17 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 17>, + <&scmi11_dvfs 17>; + power-domain-names =3D "power", + "perf"; +}; + +&uart18 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 18>, + <&scmi11_dvfs 18>; + power-domain-names =3D "power", + "perf"; +}; + +&uart19 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 19>, + <&scmi11_dvfs 19>; + power-domain-names =3D "power", + "perf"; +}; + +&uart20 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 20>, + <&scmi11_dvfs 20>; + power-domain-names =3D "power", + "perf"; +}; + +&ufs_mem_hc { + compatible =3D "qcom,sa8797p-ufshc", + "qcom,sa8255p-ufshc"; + reg =3D <0x0 0x01d44000 0x0 0x3000>; + power-domains =3D <&scmi3_pd 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/scmi-common.dtsi b/arch/arm64/boot/dt= s/qcom/scmi-common.dtsi new file mode 100644 index 000000000000..0c7ffe9e415c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/scmi-common.dtsi @@ -0,0 +1,1918 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include + +&firmware { + scmi0: scmi-0 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem0>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi0_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi0_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi0_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi1: scmi-1 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem1>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi1_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi1_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi1_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi2: scmi-2 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem2>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi2_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi2_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi2_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi3: scmi-3 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem3>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi3_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi3_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi3_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi4: scmi-4 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem4>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi4_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi4_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi4_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi5: scmi-5 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem5>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi5_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi5_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi5_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi6: scmi-6 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem6>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi6_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi6_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi6_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi7: scmi-7 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem7>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi7_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi7_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi7_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi8: scmi-8 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem8>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi8_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi8_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi8_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi9: scmi-9 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem9>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi9_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi9_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi9_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi10: scmi-10 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem10>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi10_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi10_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi10_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi11: scmi-11 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem11>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi11_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi11_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi11_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi12: scmi-12 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem12>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi12_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi12_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi12_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi13: scmi-13 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem13>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi13_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi13_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi13_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi14: scmi-14 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem14>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi14_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi14_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi14_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi15: scmi-15 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem15>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi15_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi15_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi15_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi16: scmi-16 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem16>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi16_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi16_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi16_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi17: scmi-17 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem17>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi17_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi17_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi17_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi18: scmi-18 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem18>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi18_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi18_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi18_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi19: scmi-19 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem19>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi19_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi19_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi19_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi20: scmi-20 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem20>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi20_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi20_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi20_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi21: scmi-21 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem21>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi21_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi21_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi21_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi22: scmi-22 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem22>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi22_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi22_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi22_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi23: scmi-23 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem23>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi23_sensor: protocol@15 { + reg =3D <0x15>; + #thermal-sensor-cells =3D <1>; + }; + }; + + scmi24: scmi-24 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem24>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi24_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi24_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi24_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi25: scmi-25 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem25>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi25_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi25_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi25_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi26: scmi-26 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem26>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi26_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi26_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi26_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi27: scmi-27 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem27>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi27_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi27_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi27_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi28: scmi-28 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem28>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi28_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi28_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi28_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi29: scmi-29 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem29>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi29_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi29_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi29_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi30: scmi-30 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem30>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi30_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi30_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi30_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi31: scmi-31 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem31>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi31_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi31_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi31_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi32: scmi-32 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem32>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi32_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi32_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi32_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi33: scmi-33 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem33>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi33_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi33_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi33_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi34: scmi-34 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem34>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi34_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi34_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi34_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi35: scmi-35 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem35>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi35_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi35_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi35_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi36: scmi-36 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem36>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi36_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi36_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi36_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi37: scmi-37 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem37>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi37_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi37_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi37_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi38: scmi-38 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem38>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi38_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi38_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi38_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi39: scmi-39 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem39>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi39_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi39_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi39_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi40: scmi-40 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem40>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi40_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi40_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi40_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi41: scmi-41 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem41>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi41_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi41_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi41_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi42: scmi-42 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem42>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi42_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi42_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi42_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi43: scmi-43 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem43>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi43_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi43_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi43_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi44: scmi-44 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem44>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi44_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi44_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi44_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi45: scmi-45 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem45>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi45_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi45_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi45_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi46: scmi-46 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem46>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi46_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi46_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi46_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi47: scmi-47 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem47>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi47_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi47_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi47_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi48: scmi-48 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem48>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi48_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi48_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi48_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi49: scmi-49 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem49>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi49_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi49_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi49_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi50: scmi-50 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem50>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi50_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi50_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi50_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi51: scmi-51 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem51>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi51_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi51_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi51_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi52: scmi-52 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem52>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi52_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi52_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi52_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi53: scmi-53 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem53>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi53_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi53_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi53_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi54: scmi-54 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem54>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi54_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi54_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi54_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi55: scmi-55 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem55>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi55_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi55_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi55_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi56: scmi-56 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem56>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi56_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi56_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi56_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi57: scmi-57 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem57>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi57_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi57_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi57_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi58: scmi-58 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem58>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi58_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi58_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi58_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi59: scmi-59 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem59>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi59_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi59_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi59_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi60: scmi-60 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem60>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi60_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi60_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi60_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi61: scmi-61 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem61>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi61_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi61_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi61_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi62: scmi-62 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem62>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi62_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi62_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi62_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi63: scmi-63 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem63>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi63_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi63_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi63_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; +}; --=20 2.43.0 From nobody Mon May 25 02:57:20 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D03E388368 for ; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-134cbdcf140sm22614537c88.5.2026.05.18.23.35.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 23:36:02 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Dmitry Baryshkov , Bartosz Golaszewski , Deepti Jaggi , Harshal Dev , Herbert Xu , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH v2 7/8] dt-bindings: arm: qcom: Document SA8797P Ride board Date: Tue, 19 May 2026 14:35:04 +0800 Message-ID: <20260519063505.883379-8-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519063505.883379-1-shengchao.guo@oss.qualcomm.com> References: <20260519063505.883379-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=F9ZnsKhN c=1 sm=1 tr=0 ts=6a0c04d3 cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=Ukdo0q4ZjtfF09RWrFwA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=vr4QvYf-bLy2KjpDp97w:22 X-Proofpoint-ORIG-GUID: nzWPYkIH1E2u4MTo97AlEnIbUMFP4Q0f X-Proofpoint-GUID: nzWPYkIH1E2u4MTo97AlEnIbUMFP4Q0f X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA2MiBTYWx0ZWRfX4MA89RXbIsBC ylNfeCVdD3tHkBbiV2X4Mi9CW5uoIEUvXBYWYaR/yufW3LUHnwhPrR9D1kizFaJl+ZRVuQ0saM8 QEdZAfsLNU5+rYXSdhrXQYDihqcxoRZfMgujLL4ysR+gDtSkQRmZoST/afcCOlNgw05S9jKnvmT bRgJ/jGXGfEMqWMRNQ7/YjKUEnqyAEScsOHoBY6kyZgOteYfZ2WfB3Yacf+lbrWJ4q3Dv1uH43Y lsZHXuyA3toNRbLsS0BNJWm9dWtfrwQf9lThtO5CVqWHkt2ZqDBQbKC3GaxzPs8rpO18fN3uu2Y ouWoWkzywQNcMW7Mwu4CxdBKxGbLTV3CYNnCntdR3znmM2zPnRjYvvPcdpBqIbCe7ckwj9MiM4h MyAViM2Ox2E1xuPGovoVYHIxJzH3SD7pD/R/g7l6p4/ZpwCpUPuzx84qxsyv4//O2yEmjWFQljR clL8w2hMWHgHPLSDC7w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 suspectscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 spamscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190062 The Nord is a new generation of SoC series from Qualcomm, and SA8797P is the automotive variant of Nord. SA8797P Ride is the automotive=E2=80=91g= rade development board built on SA8797P SoC. Document the board with a fallback on SA8797P and Nord compatible. Signed-off-by: Shawn Guo Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index af266d584fae..ab25323c3581 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -303,6 +303,12 @@ properties: - xiaomi,sagit - const: qcom,msm8998 =20 + - items: + - enum: + - qcom,sa8797p-ride + - const: qcom,sa8797p + - const: qcom,nord + - items: - enum: - 8dev,jalapeno --=20 2.43.0 From nobody Mon May 25 02:57:20 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4917938F95B for ; Tue, 19 May 2026 06:36:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-134cbdcf140sm22614537c88.5.2026.05.18.23.36.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 23:36:06 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Dmitry Baryshkov , Bartosz Golaszewski , Deepti Jaggi , Harshal Dev , Herbert Xu , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH v2 8/8] arm64: dts: qcom: Add device tree for SA8797P Ride board Date: Tue, 19 May 2026 14:35:05 +0800 Message-ID: <20260519063505.883379-9-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519063505.883379-1-shengchao.guo@oss.qualcomm.com> References: <20260519063505.883379-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: E7NDVG48qjWGpUWHc5bMOfusUAlSc51E X-Proofpoint-ORIG-GUID: E7NDVG48qjWGpUWHc5bMOfusUAlSc51E X-Authority-Analysis: v=2.4 cv=BICDalQG c=1 sm=1 tr=0 ts=6a0c04d8 cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=MxPmow6BhT1dHFM3JRMA:9 a=vr4QvYf-bLy2KjpDp97w:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA2MiBTYWx0ZWRfX0Oq+3Y13q/SI KZua9PIJY7uCbsIEc2FkGaNgl7g8008RaiMnfRuGJccZcdixqqzoZZ9o5pwT+74Hgo+q01QSykk XgIhC8mG3srjxZC2MmiZGcshRUxVt1Oc54VPPV8WfTANvLi8CWmqpAyzDWh1aKzYjwLDkRSvQz+ 4AanDr7FuX6DMBBkd81juVPFcY/hPQKGKzQCzWuiH8WFtv1waaHJ0OhtWf0p7gWAte8KwtbfH+a q9Tss4PsI7AW6rBb4iyewa8zMx7FozntrDfl1pp0q6G4/gVNRyIZtabE748Mjwbwv8w2oEo0Shy /nKJIqVz+cFUOF9xcJMh/JqX49RLjXv0prriybJsBPpHqLrw14o30gMB61thxjLOAEB8s8PKtz/ jKdpW7KUSwSdpl1fJ8Pq4UCRmP+Jw4+BvW6/cVlbsjMGRFkWqOxPMlw//0uyVr6lp3gwtYANVcS GTCfh9f9RNJTlMYdafg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 impostorscore=0 phishscore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190062 Content-Type: text/plain; charset="utf-8" From: Deepti Jaggi Add initial device tree for the Qualcomm SA8797P Ride reference board. - Configure UART15 as the primary console and UART4 as the secondary serial port - Enable UFS storage support - Define thermal zones for PMIC dies, UFS, and two SDRAM sensors, all sourced from SCMI sensor protocol on channel 23 Signed-off-by: Deepti Jaggi Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sa8797p-ride.dts | 306 ++++++++++++++++++++++ 2 files changed, 307 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sa8797p-ride.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 795cee4757ab..578e0da824f7 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -218,6 +218,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8540p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8775p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8775p-ride-r3.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sa8797p-ride.dtb sc7180-acer-aspire1-el2-dtbs :=3D sc7180-acer-aspire1.dtb sc7180-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-acer-aspire1.dtb sc7180-acer-aspire1-e= l2.dtb sc7180-ecs-liva-qc710-el2-dtbs :=3D sc7180-ecs-liva-qc710.dtb sc7180-el2.d= tbo diff --git a/arch/arm64/boot/dts/qcom/sa8797p-ride.dts b/arch/arm64/boot/dt= s/qcom/sa8797p-ride.dts new file mode 100644 index 000000000000..2eab2c6fc173 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8797p-ride.dts @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "nord-sa8797p.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. SA8797P Ride"; + compatible =3D "qcom,sa8797p-ride", "qcom,sa8797p", "qcom,nord"; + + aliases { + serial0 =3D &uart15; + serial1 =3D &uart4; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + clocks { + xo_board_clk: xo-board-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <38400000>; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32000>; + #clock-cells =3D <0>; + }; + }; +}; + +&scmi3 { + status =3D "okay"; +}; + +&scmi11 { + status =3D "okay"; +}; + +&scmi15 { + status =3D "okay"; +}; + +&scmi23 { + status =3D "okay"; +}; + +&thermal_zones { + pm_kobra_thermal: pm-a-die-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + thermal-sensors =3D <&scmi23_sensor 3>; + + trips { + trip0 { + temperature =3D <135000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + pm_kobra_trip1: trip1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pm_kai_0_thermal: pm-e-die-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + thermal-sensors =3D <&scmi23_sensor 4>; + + trips { + trip0 { + temperature =3D <135000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + kai_e_trip1: trip1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pm_kai_1_thermal: pm-f-die-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + thermal-sensors =3D <&scmi23_sensor 5>; + + trips { + trip0 { + temperature =3D <135000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + kai_f_trip1: trip1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pm_kai_2_thermal: pm-g-die-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + thermal-sensors =3D <&scmi23_sensor 6>; + + trips { + trip0 { + temperature =3D <135000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + kai_g_trip1: trip1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pm_kai_3_thermal: pm-h-die-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + thermal-sensors =3D <&scmi23_sensor 7>; + + trips { + trip0 { + temperature =3D <135000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + kai_h_trip1: trip1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pm_kai_4_thermal: pm-i-die-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + thermal-sensors =3D <&scmi23_sensor 8>; + + trips { + trip0 { + temperature =3D <135000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + kai_i_trip1: trip1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pm_kai_5_thermal: pm-j-die-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + thermal-sensors =3D <&scmi23_sensor 9>; + + trips { + trip0 { + temperature =3D <135000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + kai_j_trip1: trip1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pm_kai_6_thermal: pm-k-die-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + thermal-sensors =3D <&scmi23_sensor 10>; + + trips { + trip0 { + temperature =3D <135000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + kai_k_trip1: trip1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pm_kai_7_thermal: pm-l-die-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + thermal-sensors =3D <&scmi23_sensor 11>; + + trips { + trip0 { + temperature =3D <135000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + kai_l_trip1: trip1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pm_kai_ufs_thermal: ufs-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&scmi23_sensor 0>; + + trips { + trip0 { + temperature =3D <125000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <125000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pm_kai_sdram0_thermal: sdram0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&scmi23_sensor 1>; + + trips { + trip0 { + temperature =3D <125000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <125000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pm_kai_sdram1_thermal: sdram1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&scmi23_sensor 2>; + + trips { + trip0 { + temperature =3D <125000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <125000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; +}; + +&uart4 { + status =3D "okay"; +}; + +&uart15 { + status =3D "okay"; +}; + +&ufs_mem_hc { + status =3D "okay"; +}; --=20 2.43.0