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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83f8b9c2ea5sm2641252b3a.13.2026.05.18.22.51.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 22:52:01 -0700 (PDT) From: Joey Lu To: zhengxingda@iscas.ac.cn, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH v2 1/4] dt-bindings: display: verisilicon,dc: generalize for single-output variants Date: Tue, 19 May 2026 13:51:06 +0800 Message-ID: <20260519055114.1886525-2-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519055114.1886525-1-a0987203069@gmail.com> References: <20260519055114.1886525-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The existing schema assumes a fixed clock/reset topology and dual-output port structure matching the DC8200 IP block. This prevents reuse for single-output variants such as the Verisilicon DCU Lite used in the Nuvoton MA35D1 SoC. Rework the schema so that variant-specific constraints are expressed via allOf/if-then-else: - The thead,th1520-dc8200 compatible keeps its existing five-clock, three-reset, dual-port requirements. - A standalone verisilicon,dc compatible covers IPs whose identity is discovered entirely through hardware registers; these have flexible clock and reset counts, a single 'port' property, and no 'ports' requirement. Changes to the base schema: - Replace the fixed clock/reset items lists with minItems/maxItems ranges; variant sub-schemas tighten the constraints via if-then-else. - Add a 'port' property (graph.yaml single-port alias) alongside the existing 'ports', for single-output variants. - Drop the unconditional 'ports' requirement; each if-branch enforces its own port topology. - Tighten additionalProperties to unevaluatedProperties to allow per-variant schemas to add their own constraints cleanly. - Fix a stray space in the port@0 description. - Add a DT example for the generic verisilicon,dc compatible (Nuvoton MA35D1 DCU Lite). Signed-off-by: Joey Lu --- .../bindings/display/verisilicon,dc.yaml | 135 ++++++++++++++---- 1 file changed, 108 insertions(+), 27 deletions(-) diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml = b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml index 9dc35ab973f2..3a814c2e083e 100644 --- a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml @@ -14,10 +14,12 @@ properties: pattern: "^display@[0-9a-f]+$" =20 compatible: - items: - - enum: - - thead,th1520-dc8200 - - const: verisilicon,dc # DC IPs have discoverable ID/revision regis= ters + oneOf: + - items: + - enum: + - thead,th1520-dc8200 + - const: verisilicon,dc + - const: verisilicon,dc # DC IPs have discoverable ID/revision regi= sters =20 reg: maxItems: 1 @@ -26,32 +28,24 @@ properties: maxItems: 1 =20 clocks: - items: - - description: DC Core clock - - description: DMA AXI bus clock - - description: Configuration AHB bus clock - - description: Pixel clock of output 0 - - description: Pixel clock of output 1 + minItems: 2 + maxItems: 5 =20 clock-names: - items: - - const: core - - const: axi - - const: ahb - - const: pix0 - - const: pix1 + minItems: 2 + maxItems: 5 =20 resets: - items: - - description: DC Core reset - - description: DMA AXI bus reset - - description: Configuration AHB bus reset + minItems: 1 + maxItems: 3 =20 reset-names: - items: - - const: core - - const: axi - - const: ahb + minItems: 1 + maxItems: 3 + + port: + $ref: /schemas/graph.yaml#/properties/port + description: Single video output port for single-output variants. =20 ports: $ref: /schemas/graph.yaml#/properties/ports @@ -59,7 +53,7 @@ properties: properties: port@0: $ref: /schemas/graph.yaml#/properties/port - description: The first output channel , endpoint 0 should be + description: The first output channel, endpoint 0 should be used for DPI format output and endpoint 1 should be used for DP format output. =20 @@ -75,9 +69,75 @@ required: - interrupts - clocks - clock-names - - ports =20 -additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + const: thead,th1520-dc8200 + then: + properties: + clocks: + items: + - description: DC Core clock + - description: DMA AXI bus clock + - description: Configuration AHB bus clock + - description: Pixel clock of output 0 + - description: Pixel clock of output 1 + + clock-names: + items: + - const: core + - const: axi + - const: ahb + - const: pix0 + - const: pix1 + + resets: + items: + - description: DC Core reset + - description: DMA AXI bus reset + - description: Configuration AHB bus reset + + reset-names: + items: + - const: core + - const: axi + - const: ahb + + required: + - ports + + else: + properties: + clocks: + items: + - description: Bus clock that gates register access + - description: Pixel clock divider for display timing + + clock-names: + items: + - const: core + - const: pix0 + + resets: + maxItems: 1 + description: + Reset line for the display controller. + + reset-names: + items: + - const: core + + required: + - port + + not: + required: + - ports + +unevaluatedProperties: false =20 examples: - | @@ -120,3 +180,24 @@ examples: }; }; }; + + - | + #include + #include + #include + + display@40260000 { + compatible =3D "verisilicon,dc"; + reg =3D <0x40260000 0x20000>; + interrupts =3D ; + clocks =3D <&clk DCU_GATE>, <&clk DCUP_DIV>; + clock-names =3D "core", "pix0"; + resets =3D <&sys MA35D1_RESET_DISP>; + reset-names =3D "core"; + + port { + dpi_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; + }; --=20 2.43.0 From nobody Mon May 25 03:33:29 2026 Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com [209.85.210.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFD0D351C2D for ; Tue, 19 May 2026 05:52:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779169928; cv=none; b=fBYRCFqanue/AALZq6ALTnYFr6Bn5wVrVWE6oMkVUp/RLPsv91W4B/+BxEb/SfAymctAV0ATzxMjzednj6ClYDZX8EI2VONsHtnr7g+5kZVxpaRuFkc2Vmf4Qf8Sktxeopa2LxhCDyo0tLZaATWQqi3OZOVFNZMUcqR79fx6HU4= ARC-Message-Signature: i=1; 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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83f8b9c2ea5sm2641252b3a.13.2026.05.18.22.52.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 22:52:04 -0700 (PDT) From: Joey Lu To: zhengxingda@iscas.ac.cn, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH v2 2/4] drm/verisilicon: add model ID constants and DCU Lite chip identity Date: Tue, 19 May 2026 13:51:07 +0800 Message-ID: <20260519055114.1886525-3-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519055114.1886525-1-a0987203069@gmail.com> References: <20260519055114.1886525-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce symbolic constants VSDC_MODEL_DC8200 and VSDC_MODEL_DCU_LITE to replace magic numbers in the hardware database and probe path. Register the DCU Lite chip identity (model 0x0, revision 0x5560, customer_id 0x305) in vs_chip_identities[], making the existing vs_fill_chip_identity() path able to recognise Nuvoton MA35D1 hardware purely through register reads. Also add three register-level macros for forthcoming DCU Lite support: - VSDC_DISP_IRQ_VSYNC(n) in vs_crtc_regs.h, for per-output VSYNC IRQ bits used by the DCU Lite IRQ enable/status registers. - VSDC_FB_CONFIG_ENABLE, VSDC_FB_CONFIG_VALID and VSDC_FB_CONFIG_RESET in vs_primary_plane_regs.h, for the framebuffer enable and commit-cycle bits used by the DCU Lite plane update path. No behaviour change for existing DC8200 platforms. Signed-off-by: Joey Lu --- drivers/gpu/drm/verisilicon/vs_crtc_regs.h | 1 + drivers/gpu/drm/verisilicon/vs_hwdb.c | 16 ++++++++++++---- drivers/gpu/drm/verisilicon/vs_hwdb.h | 3 +++ .../gpu/drm/verisilicon/vs_primary_plane_regs.h | 3 +++ 4 files changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/verisilicon/vs_crtc_regs.h b/drivers/gpu/drm/v= erisilicon/vs_crtc_regs.h index c7930e817635..d4da22b08cd5 100644 --- a/drivers/gpu/drm/verisilicon/vs_crtc_regs.h +++ b/drivers/gpu/drm/verisilicon/vs_crtc_regs.h @@ -54,6 +54,7 @@ #define VSDC_DISP_GAMMA_DATA(n) (0x1460 + 0x4 * (n)) =20 #define VSDC_DISP_IRQ_STA 0x147C +#define VSDC_DISP_IRQ_VSYNC(n) BIT(n) =20 #define VSDC_DISP_IRQ_EN 0x1480 =20 diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.c b/drivers/gpu/drm/verisi= licon/vs_hwdb.c index 09336af0900a..a25c4b16181d 100644 --- a/drivers/gpu/drm/verisilicon/vs_hwdb.c +++ b/drivers/gpu/drm/verisilicon/vs_hwdb.c @@ -90,7 +90,7 @@ static const struct vs_formats vs_formats_with_yuv444 =3D= { =20 static struct vs_chip_identity vs_chip_identities[] =3D { { - .model =3D 0x8200, + .model =3D VSDC_MODEL_DC8200, .revision =3D 0x5720, .customer_id =3D ~0U, =20 @@ -98,7 +98,7 @@ static struct vs_chip_identity vs_chip_identities[] =3D { .formats =3D &vs_formats_no_yuv444, }, { - .model =3D 0x8200, + .model =3D VSDC_MODEL_DC8200, .revision =3D 0x5721, .customer_id =3D 0x30B, =20 @@ -106,7 +106,7 @@ static struct vs_chip_identity vs_chip_identities[] =3D= { .formats =3D &vs_formats_no_yuv444, }, { - .model =3D 0x8200, + .model =3D VSDC_MODEL_DC8200, .revision =3D 0x5720, .customer_id =3D 0x310, =20 @@ -114,13 +114,21 @@ static struct vs_chip_identity vs_chip_identities[] = =3D { .formats =3D &vs_formats_with_yuv444, }, { - .model =3D 0x8200, + .model =3D VSDC_MODEL_DC8200, .revision =3D 0x5720, .customer_id =3D 0x311, =20 .display_count =3D 2, .formats =3D &vs_formats_no_yuv444, }, + { + .model =3D VSDC_MODEL_DCU_LITE, + .revision =3D 0x5560, + .customer_id =3D 0x305, + + .display_count =3D 1, + .formats =3D &vs_formats_no_yuv444, + }, }; =20 int vs_fill_chip_identity(struct regmap *regs, diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.h b/drivers/gpu/drm/verisi= licon/vs_hwdb.h index 92192e4fa086..cca126bd2da5 100644 --- a/drivers/gpu/drm/verisilicon/vs_hwdb.h +++ b/drivers/gpu/drm/verisilicon/vs_hwdb.h @@ -9,6 +9,9 @@ #include #include =20 +#define VSDC_MODEL_DC8200 0x8200 +#define VSDC_MODEL_DCU_LITE 0x0 + struct vs_formats { const u32 *array; unsigned int num; diff --git a/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h b/drivers/= gpu/drm/verisilicon/vs_primary_plane_regs.h index cbb125c46b39..67d4b00f294e 100644 --- a/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h +++ b/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h @@ -16,6 +16,9 @@ #define VSDC_FB_STRIDE(n) (0x1408 + 0x4 * (n)) =20 #define VSDC_FB_CONFIG(n) (0x1518 + 0x4 * (n)) +#define VSDC_FB_CONFIG_ENABLE BIT(0) +#define VSDC_FB_CONFIG_VALID BIT(3) +#define VSDC_FB_CONFIG_RESET BIT(4) #define VSDC_FB_CONFIG_CLEAR_EN BIT(8) #define VSDC_FB_CONFIG_ROT_MASK GENMASK(13, 11) #define VSDC_FB_CONFIG_ROT(v) ((v) << 11) --=20 2.43.0 From nobody Mon May 25 03:33:29 2026 Received: from mail-pf1-f178.google.com (mail-pf1-f178.google.com [209.85.210.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FA62351C2E for ; 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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83f8b9c2ea5sm2641252b3a.13.2026.05.18.22.52.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 22:52:07 -0700 (PDT) From: Joey Lu To: zhengxingda@iscas.ac.cn, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH v2 3/4] drm/verisilicon: introduce per-variant hardware ops table Date: Tue, 19 May 2026 13:51:08 +0800 Message-ID: <20260519055114.1886525-4-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519055114.1886525-1-a0987203069@gmail.com> References: <20260519055114.1886525-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The DC driver directly calls DC8200-specific register sequences from vs_bridge.c, vs_crtc.c and vs_primary_plane.c. Supporting a second IP variant with a different register layout would require scattering if/else branches throughout those files. Instead, introduce struct vs_dc_funcs, a small vtable of function pointers covering every hardware-specific operation: bridge_enable/disable - panel output start/stop sequence crtc_begin/flush - per-frame commit begin/end hooks crtc_enable/disable - display output power on/off enable_vblank/disable_vblank - IRQ mask for vsync events plane_enable_ex/disable_ex - framebuffer enable/disable plane_update_ex - variant-specific plane update registers irq_handler - read and acknowledge pending IRQs Extract all DC8200-specific register operations from vs_bridge.c, vs_crtc.c, vs_primary_plane.c and vs_dc.c into a new vs_dc8200.c source file that implements the full vs_dc_funcs vtable and exposes vs_dc8200_funcs. Add atomic_begin and atomic_flush hooks in vs_crtc.c to dispatch to crtc_begin/crtc_flush; these are optional (NULL-checked) so that variants without a per-frame commit cycle can leave them unimplemented. After vs_fill_chip_identity() confirms a DC8200 (or compatible) identity, vs_dc_probe() assigns dc->funcs =3D &vs_dc8200_funcs so all callers automatically dispatch to the correct implementation. No functional change for DC8200 platforms. Signed-off-by: Joey Lu --- drivers/gpu/drm/verisilicon/Makefile | 2 +- drivers/gpu/drm/verisilicon/vs_bridge.c | 20 +--- drivers/gpu/drm/verisilicon/vs_crtc.c | 38 ++++++- drivers/gpu/drm/verisilicon/vs_dc.c | 6 +- drivers/gpu/drm/verisilicon/vs_dc.h | 32 ++++++ drivers/gpu/drm/verisilicon/vs_dc8200.c | 107 ++++++++++++++++++ .../gpu/drm/verisilicon/vs_primary_plane.c | 32 +----- 7 files changed, 186 insertions(+), 51 deletions(-) create mode 100644 drivers/gpu/drm/verisilicon/vs_dc8200.c diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisil= icon/Makefile index fd8d805fbcde..f4fbd9f7d6a2 100644 --- a/drivers/gpu/drm/verisilicon/Makefile +++ b/drivers/gpu/drm/verisilicon/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only =20 -verisilicon-dc-objs :=3D vs_bridge.o vs_crtc.o vs_dc.o vs_drm.o vs_hwdb.o = vs_plane.o vs_primary_plane.o +verisilicon-dc-objs :=3D vs_bridge.o vs_crtc.o vs_dc.o vs_dc8200.o vs_drm.= o vs_hwdb.o vs_plane.o vs_primary_plane.o =20 obj-$(CONFIG_DRM_VERISILICON_DC) +=3D verisilicon-dc.o diff --git a/drivers/gpu/drm/verisilicon/vs_bridge.c b/drivers/gpu/drm/veri= silicon/vs_bridge.c index 7a93049368db..6a9af10c64e6 100644 --- a/drivers/gpu/drm/verisilicon/vs_bridge.c +++ b/drivers/gpu/drm/verisilicon/vs_bridge.c @@ -162,15 +162,8 @@ static void vs_bridge_enable_common(struct vs_crtc *cr= tc, VSDC_DISP_PANEL_CONFIG_DE_EN | VSDC_DISP_PANEL_CONFIG_DAT_EN | VSDC_DISP_PANEL_CONFIG_CLK_EN); - regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), - VSDC_DISP_PANEL_CONFIG_RUNNING); - regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START, - VSDC_DISP_PANEL_START_MULTI_DISP_SYNC); - regmap_set_bits(dc->regs, VSDC_DISP_PANEL_START, - VSDC_DISP_PANEL_START_RUNNING(output)); - - regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(crtc->id), - VSDC_DISP_PANEL_CONFIG_EX_COMMIT); + + dc->funcs->bridge_enable(dc, output); } =20 static void vs_bridge_atomic_enable_dpi(struct drm_bridge *bridge, @@ -228,14 +221,7 @@ static void vs_bridge_atomic_disable(struct drm_bridge= *bridge, struct vs_dc *dc =3D crtc->dc; unsigned int output =3D crtc->id; =20 - regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START, - VSDC_DISP_PANEL_START_MULTI_DISP_SYNC | - VSDC_DISP_PANEL_START_RUNNING(output)); - regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), - VSDC_DISP_PANEL_CONFIG_RUNNING); - - regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(crtc->id), - VSDC_DISP_PANEL_CONFIG_EX_COMMIT); + dc->funcs->bridge_disable(dc, output); } =20 static const struct drm_bridge_funcs vs_dpi_bridge_funcs =3D { diff --git a/drivers/gpu/drm/verisilicon/vs_crtc.c b/drivers/gpu/drm/verisi= licon/vs_crtc.c index 9080344398ca..a87caa6f73ba 100644 --- a/drivers/gpu/drm/verisilicon/vs_crtc.c +++ b/drivers/gpu/drm/verisilicon/vs_crtc.c @@ -16,10 +16,33 @@ #include "vs_crtc_regs.h" #include "vs_crtc.h" #include "vs_dc.h" -#include "vs_dc_top_regs.h" #include "vs_drm.h" #include "vs_plane.h" =20 +static void vs_crtc_atomic_begin(struct drm_crtc *crtc, + struct drm_atomic_commit *state) +{ + struct vs_crtc *vcrtc =3D drm_crtc_to_vs_crtc(crtc); + struct vs_dc *dc =3D vcrtc->dc; + unsigned int output =3D vcrtc->id; + + if (dc->funcs->crtc_begin) + dc->funcs->crtc_begin(dc, output); +} + +static void vs_crtc_atomic_flush(struct drm_crtc *crtc, + struct drm_atomic_commit *state) +{ + struct vs_crtc *vcrtc =3D drm_crtc_to_vs_crtc(crtc); + struct vs_dc *dc =3D vcrtc->dc; + unsigned int output =3D vcrtc->id; + + if (dc->funcs->crtc_flush) + dc->funcs->crtc_flush(dc, output); + + drm_crtc_vblank_atomic_flush(crtc, state); +} + static void vs_crtc_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_commit *state) { @@ -30,6 +53,9 @@ static void vs_crtc_atomic_disable(struct drm_crtc *crtc, drm_crtc_vblank_off(crtc); =20 clk_disable_unprepare(dc->pix_clk[output]); + + if (dc->funcs->crtc_disable) + dc->funcs->crtc_disable(dc, output); } =20 static void vs_crtc_atomic_enable(struct drm_crtc *crtc, @@ -42,6 +68,9 @@ static void vs_crtc_atomic_enable(struct drm_crtc *crtc, drm_WARN_ON(&dc->drm_dev->base, clk_prepare_enable(dc->pix_clk[output])); =20 + if (dc->funcs->crtc_enable) + dc->funcs->crtc_enable(dc, output); + drm_crtc_vblank_on(crtc); } =20 @@ -119,7 +148,8 @@ static bool vs_crtc_mode_fixup(struct drm_crtc *crtc, } =20 static const struct drm_crtc_helper_funcs vs_crtc_helper_funcs =3D { - .atomic_flush =3D drm_crtc_vblank_atomic_flush, + .atomic_begin =3D vs_crtc_atomic_begin, + .atomic_flush =3D vs_crtc_atomic_flush, .atomic_enable =3D vs_crtc_atomic_enable, .atomic_disable =3D vs_crtc_atomic_disable, .mode_set_nofb =3D vs_crtc_mode_set_nofb, @@ -132,7 +162,7 @@ static int vs_crtc_enable_vblank(struct drm_crtc *crtc) struct vs_crtc *vcrtc =3D drm_crtc_to_vs_crtc(crtc); struct vs_dc *dc =3D vcrtc->dc; =20 - regmap_set_bits(dc->regs, VSDC_TOP_IRQ_EN, VSDC_TOP_IRQ_VSYNC(vcrtc->id)); + dc->funcs->enable_vblank(dc, vcrtc->id); =20 return 0; } @@ -142,7 +172,7 @@ static void vs_crtc_disable_vblank(struct drm_crtc *crt= c) struct vs_crtc *vcrtc =3D drm_crtc_to_vs_crtc(crtc); struct vs_dc *dc =3D vcrtc->dc; =20 - regmap_clear_bits(dc->regs, VSDC_TOP_IRQ_EN, VSDC_TOP_IRQ_VSYNC(vcrtc->id= )); + dc->funcs->disable_vblank(dc, vcrtc->id); } =20 static const struct drm_crtc_funcs vs_crtc_funcs =3D { diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c b/drivers/gpu/drm/verisili= con/vs_dc.c index dad9967bc10b..c94957024189 100644 --- a/drivers/gpu/drm/verisilicon/vs_dc.c +++ b/drivers/gpu/drm/verisilicon/vs_dc.c @@ -8,9 +8,7 @@ #include #include =20 -#include "vs_crtc.h" #include "vs_dc.h" -#include "vs_dc_top_regs.h" #include "vs_drm.h" #include "vs_hwdb.h" =20 @@ -33,7 +31,7 @@ static irqreturn_t vs_dc_irq_handler(int irq, void *priva= te) struct vs_dc *dc =3D private; u32 irqs; =20 - regmap_read(dc->regs, VSDC_TOP_IRQ_ACK, &irqs); + irqs =3D dc->funcs->irq_handler(dc); =20 vs_drm_handle_irq(dc, irqs); =20 @@ -136,6 +134,8 @@ static int vs_dc_probe(struct platform_device *pdev) dev_info(dev, "Found DC%x rev %x customer %x\n", dc->identity.model, dc->identity.revision, dc->identity.customer_id); =20 + dc->funcs =3D &vs_dc8200_funcs; + if (port_count > dc->identity.display_count) { dev_err(dev, "too many downstream ports than HW capability\n"); ret =3D -EINVAL; diff --git a/drivers/gpu/drm/verisilicon/vs_dc.h b/drivers/gpu/drm/verisili= con/vs_dc.h index ed1016f18758..45172c1a525c 100644 --- a/drivers/gpu/drm/verisilicon/vs_dc.h +++ b/drivers/gpu/drm/verisilicon/vs_dc.h @@ -14,6 +14,7 @@ #include =20 #include +#include =20 #include "vs_hwdb.h" =20 @@ -22,6 +23,34 @@ =20 struct vs_drm_dev; struct vs_crtc; +struct vs_dc; + +struct vs_dc_funcs { + /* Bridge: atomic_enable, atomic_disable */ + void (*bridge_enable)(struct vs_dc *dc, unsigned int output); + void (*bridge_disable)(struct vs_dc *dc, unsigned int output); + + /* CRTC: atomic_begin, atomic_flush */ + void (*crtc_begin)(struct vs_dc *dc, unsigned int output); + void (*crtc_flush)(struct vs_dc *dc, unsigned int output); + + /* CRTC: atomic_enable, atomic_disable */ + void (*crtc_enable)(struct vs_dc *dc, unsigned int output); + void (*crtc_disable)(struct vs_dc *dc, unsigned int output); + + /* CRTC: enable_vblank, disable_vblank */ + void (*enable_vblank)(struct vs_dc *dc, unsigned int output); + void (*disable_vblank)(struct vs_dc *dc, unsigned int output); + + /* Primary plane: atomic_enable, atomic_disable, atomic_update */ + void (*plane_enable_ex)(struct vs_dc *dc, unsigned int output); + void (*plane_disable_ex)(struct vs_dc *dc, unsigned int output); + void (*plane_update_ex)(struct vs_dc *dc, unsigned int output, + struct drm_plane_state *state); + + /* IRQ handler */ + u32 (*irq_handler)(struct vs_dc *dc); +}; =20 struct vs_dc { struct regmap *regs; @@ -33,6 +62,9 @@ struct vs_dc { =20 struct vs_drm_dev *drm_dev; struct vs_chip_identity identity; + const struct vs_dc_funcs *funcs; }; =20 +extern const struct vs_dc_funcs vs_dc8200_funcs; + #endif /* _VS_DC_H_ */ diff --git a/drivers/gpu/drm/verisilicon/vs_dc8200.c b/drivers/gpu/drm/veri= silicon/vs_dc8200.c new file mode 100644 index 000000000000..db9e1b3cd903 --- /dev/null +++ b/drivers/gpu/drm/verisilicon/vs_dc8200.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Icenowy Zheng + */ + +#include + +#include "vs_bridge_regs.h" +#include "vs_dc.h" +#include "vs_dc_top_regs.h" +#include "vs_plane.h" +#include "vs_primary_plane_regs.h" + +static void vs_dc8200_bridge_enable(struct vs_dc *dc, unsigned int output) +{ + regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), + VSDC_DISP_PANEL_CONFIG_RUNNING); + regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START, + VSDC_DISP_PANEL_START_MULTI_DISP_SYNC); + regmap_set_bits(dc->regs, VSDC_DISP_PANEL_START, + VSDC_DISP_PANEL_START_RUNNING(output)); + + regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(output), + VSDC_DISP_PANEL_CONFIG_EX_COMMIT); +} + +static void vs_dc8200_bridge_disable(struct vs_dc *dc, unsigned int output) +{ + regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), + VSDC_DISP_PANEL_CONFIG_RUNNING); + regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START, + VSDC_DISP_PANEL_START_MULTI_DISP_SYNC | + VSDC_DISP_PANEL_START_RUNNING(output)); + + regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(output), + VSDC_DISP_PANEL_CONFIG_EX_COMMIT); +} + +static void vs_dc8200_enable_vblank(struct vs_dc *dc, unsigned int output) +{ + regmap_set_bits(dc->regs, VSDC_TOP_IRQ_EN, + VSDC_TOP_IRQ_VSYNC(output)); +} + +static void vs_dc8200_disable_vblank(struct vs_dc *dc, unsigned int output) +{ + regmap_clear_bits(dc->regs, VSDC_TOP_IRQ_EN, + VSDC_TOP_IRQ_VSYNC(output)); +} + +static void vs_dc8200_plane_commit(struct vs_dc *dc, unsigned int output) +{ + regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), + VSDC_FB_CONFIG_EX_COMMIT); +} + +static void vs_dc8200_plane_enable_ex(struct vs_dc *dc, unsigned int outpu= t) +{ + regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), + VSDC_FB_CONFIG_EX_FB_EN); + regmap_update_bits(dc->regs, VSDC_FB_CONFIG_EX(output), + VSDC_FB_CONFIG_EX_DISPLAY_ID_MASK, + VSDC_FB_CONFIG_EX_DISPLAY_ID(output)); + + vs_dc8200_plane_commit(dc, output); +} + +static void vs_dc8200_plane_disable_ex(struct vs_dc *dc, unsigned int outp= ut) +{ + regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), + VSDC_FB_CONFIG_EX_FB_EN); + + vs_dc8200_plane_commit(dc, output); +} + +static void vs_dc8200_plane_update_ex(struct vs_dc *dc, unsigned int outpu= t, + struct drm_plane_state *state) +{ + regmap_write(dc->regs, VSDC_FB_TOP_LEFT(output), + VSDC_MAKE_PLANE_POS(state->crtc_x, state->crtc_y)); + regmap_write(dc->regs, VSDC_FB_BOTTOM_RIGHT(output), + VSDC_MAKE_PLANE_POS(state->crtc_x + state->crtc_w, + state->crtc_y + state->crtc_h)); + regmap_write(dc->regs, VSDC_FB_BLEND_CONFIG(output), + VSDC_FB_BLEND_CONFIG_BLEND_DISABLE); + + vs_dc8200_plane_commit(dc, output); +} + +static u32 vs_dc8200_irq_handler(struct vs_dc *dc) +{ + u32 irqs; + + regmap_read(dc->regs, VSDC_TOP_IRQ_ACK, &irqs); + return irqs; +} + +const struct vs_dc_funcs vs_dc8200_funcs =3D { + .bridge_enable =3D vs_dc8200_bridge_enable, + .bridge_disable =3D vs_dc8200_bridge_disable, + .enable_vblank =3D vs_dc8200_enable_vblank, + .disable_vblank =3D vs_dc8200_disable_vblank, + .plane_enable_ex =3D vs_dc8200_plane_enable_ex, + .plane_disable_ex =3D vs_dc8200_plane_disable_ex, + .plane_update_ex =3D vs_dc8200_plane_update_ex, + .irq_handler =3D vs_dc8200_irq_handler, +}; diff --git a/drivers/gpu/drm/verisilicon/vs_primary_plane.c b/drivers/gpu/d= rm/verisilicon/vs_primary_plane.c index 1f2be41ae496..75bc36a078f7 100644 --- a/drivers/gpu/drm/verisilicon/vs_primary_plane.c +++ b/drivers/gpu/drm/verisilicon/vs_primary_plane.c @@ -53,12 +53,6 @@ static int vs_primary_plane_atomic_check(struct drm_plan= e *plane, return 0; } =20 -static void vs_primary_plane_commit(struct vs_dc *dc, unsigned int output) -{ - regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), - VSDC_FB_CONFIG_EX_COMMIT); -} - static void vs_primary_plane_atomic_enable(struct drm_plane *plane, struct drm_atomic_commit *atomic_state) { @@ -69,13 +63,8 @@ static void vs_primary_plane_atomic_enable(struct drm_pl= ane *plane, unsigned int output =3D vcrtc->id; struct vs_dc *dc =3D vcrtc->dc; =20 - regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), - VSDC_FB_CONFIG_EX_FB_EN); - regmap_update_bits(dc->regs, VSDC_FB_CONFIG_EX(output), - VSDC_FB_CONFIG_EX_DISPLAY_ID_MASK, - VSDC_FB_CONFIG_EX_DISPLAY_ID(output)); - - vs_primary_plane_commit(dc, output); + if (dc->funcs->plane_enable_ex) + dc->funcs->plane_enable_ex(dc, output); } =20 static void vs_primary_plane_atomic_disable(struct drm_plane *plane, @@ -88,10 +77,8 @@ static void vs_primary_plane_atomic_disable(struct drm_p= lane *plane, unsigned int output =3D vcrtc->id; struct vs_dc *dc =3D vcrtc->dc; =20 - regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), - VSDC_FB_CONFIG_EX_FB_EN); - - vs_primary_plane_commit(dc, output); + if (dc->funcs->plane_disable_ex) + dc->funcs->plane_disable_ex(dc, output); } =20 static void vs_primary_plane_atomic_update(struct drm_plane *plane, @@ -133,18 +120,11 @@ static void vs_primary_plane_atomic_update(struct drm= _plane *plane, regmap_write(dc->regs, VSDC_FB_STRIDE(output), fb->pitches[0]); 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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83f8b9c2ea5sm2641252b3a.13.2026.05.18.22.52.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 22:52:11 -0700 (PDT) From: Joey Lu To: zhengxingda@iscas.ac.cn, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH v2 4/4] drm/verisilicon: add Nuvoton MA35D1 DCU Lite display controller support Date: Tue, 19 May 2026 13:51:09 +0800 Message-ID: <20260519055114.1886525-5-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519055114.1886525-1-a0987203069@gmail.com> References: <20260519055114.1886525-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Nuvoton MA35D1 SoC integrates a Verisilicon DCU Lite display controller. While its register layout is broadly similar to the DC8200, several differences require dedicated hardware ops: 1. No CONFIG_EX commit path: framebuffer updates use enable (bit 0) and reset (bit 4) bits in FB_CONFIG instead of the DC8200 staging registers (FB_CONFIG_EX, FB_TOP_LEFT, FB_BOTTOM_RIGHT, FB_BLEND_CONFIG, PANEL_CONFIG_EX). 2. No PANEL_START register: panel output starts when PANEL_CONFIG.RUNNING is set; no multi-display sync start register is used. 3. Different IRQ registers: DCU Lite uses DISP_IRQ_STA (0x147C) / DISP_IRQ_EN (0x1480) versus DC8200's TOP_IRQ_ACK (0x0010) / TOP_IRQ_EN (0x0014). 4. Per-frame commit cycle: DCU Lite requires the VALID bit in FB_CONFIG to be set at the start of each atomic commit (crtc_begin) and cleared after (crtc_flush). 5. Simpler clock topology: only "core" (bus gate) and "pix0" (pixel divider) clocks; no axi or ahb clocks. Make axi_clk and ahb_clk optional (devm_clk_get_optional_enabled) so DCU Lite nodes without those clocks are handled gracefully. Add vs_dcu_lite.c implementing the vs_dc_funcs vtable for the above differences. After chip identity detection, vs_dc_probe() now selects vs_dcu_lite_funcs when the identified model is VSDC_MODEL_DCU_LITE (model register reads 0, revision 0x5560, customer_id 0x305). Extend Kconfig to allow building on ARCH_MA35 platforms. Signed-off-by: Joey Lu --- drivers/gpu/drm/verisilicon/Kconfig | 2 +- drivers/gpu/drm/verisilicon/Makefile | 2 +- drivers/gpu/drm/verisilicon/vs_dc.c | 9 ++- drivers/gpu/drm/verisilicon/vs_dc.h | 1 + drivers/gpu/drm/verisilicon/vs_dcu_lite.c | 78 +++++++++++++++++++++++ 5 files changed, 87 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/verisilicon/vs_dcu_lite.c diff --git a/drivers/gpu/drm/verisilicon/Kconfig b/drivers/gpu/drm/verisili= con/Kconfig index 7cce86ec8603..295d246eb4b4 100644 --- a/drivers/gpu/drm/verisilicon/Kconfig +++ b/drivers/gpu/drm/verisilicon/Kconfig @@ -2,7 +2,7 @@ config DRM_VERISILICON_DC tristate "DRM Support for Verisilicon DC-series display controllers" depends on DRM && COMMON_CLK - depends on RISCV || COMPILE_TEST + depends on RISCV || ARCH_MA35 || COMPILE_TEST select DRM_BRIDGE_CONNECTOR select DRM_CLIENT_SELECTION select DRM_DISPLAY_HELPER diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisil= icon/Makefile index f4fbd9f7d6a2..bf88f627e65c 100644 --- a/drivers/gpu/drm/verisilicon/Makefile +++ b/drivers/gpu/drm/verisilicon/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only =20 -verisilicon-dc-objs :=3D vs_bridge.o vs_crtc.o vs_dc.o vs_dc8200.o vs_drm.= o vs_hwdb.o vs_plane.o vs_primary_plane.o +verisilicon-dc-objs :=3D vs_bridge.o vs_crtc.o vs_dc.o vs_dc8200.o vs_dcu_= lite.o vs_drm.o vs_hwdb.o vs_plane.o vs_primary_plane.o =20 obj-$(CONFIG_DRM_VERISILICON_DC) +=3D verisilicon-dc.o diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c b/drivers/gpu/drm/verisili= con/vs_dc.c index c94957024189..77bc63c629f7 100644 --- a/drivers/gpu/drm/verisilicon/vs_dc.c +++ b/drivers/gpu/drm/verisilicon/vs_dc.c @@ -90,13 +90,13 @@ static int vs_dc_probe(struct platform_device *pdev) return PTR_ERR(dc->core_clk); } =20 - dc->axi_clk =3D devm_clk_get_enabled(dev, "axi"); + dc->axi_clk =3D devm_clk_get_optional_enabled(dev, "axi"); if (IS_ERR(dc->axi_clk)) { dev_err(dev, "can't get axi clock\n"); return PTR_ERR(dc->axi_clk); } =20 - dc->ahb_clk =3D devm_clk_get_enabled(dev, "ahb"); + dc->ahb_clk =3D devm_clk_get_optional_enabled(dev, "ahb"); if (IS_ERR(dc->ahb_clk)) { dev_err(dev, "can't get ahb clock\n"); return PTR_ERR(dc->ahb_clk); @@ -134,7 +134,10 @@ static int vs_dc_probe(struct platform_device *pdev) dev_info(dev, "Found DC%x rev %x customer %x\n", dc->identity.model, dc->identity.revision, dc->identity.customer_id); =20 - dc->funcs =3D &vs_dc8200_funcs; + if (dc->identity.model =3D=3D VSDC_MODEL_DC8200) + dc->funcs =3D &vs_dc8200_funcs; + else + dc->funcs =3D &vs_dcu_lite_funcs; =20 if (port_count > dc->identity.display_count) { dev_err(dev, "too many downstream ports than HW capability\n"); diff --git a/drivers/gpu/drm/verisilicon/vs_dc.h b/drivers/gpu/drm/verisili= con/vs_dc.h index 45172c1a525c..d77d4a1babdf 100644 --- a/drivers/gpu/drm/verisilicon/vs_dc.h +++ b/drivers/gpu/drm/verisilicon/vs_dc.h @@ -66,5 +66,6 @@ struct vs_dc { }; =20 extern const struct vs_dc_funcs vs_dc8200_funcs; +extern const struct vs_dc_funcs vs_dcu_lite_funcs; =20 #endif /* _VS_DC_H_ */ diff --git a/drivers/gpu/drm/verisilicon/vs_dcu_lite.c b/drivers/gpu/drm/ve= risilicon/vs_dcu_lite.c new file mode 100644 index 000000000000..11ef57d5ebaa --- /dev/null +++ b/drivers/gpu/drm/verisilicon/vs_dcu_lite.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Joey Lu + */ + +#include + +#include "vs_crtc_regs.h" +#include "vs_dc.h" +#include "vs_primary_plane_regs.h" + +static void vs_dcu_lite_bridge_enable(struct vs_dc *dc, unsigned int outpu= t) +{ + regmap_set_bits(dc->regs, VSDC_FB_CONFIG(output), + VSDC_FB_CONFIG_RESET); +} + +static void vs_dcu_lite_bridge_disable(struct vs_dc *dc, unsigned int outp= ut) +{ + regmap_clear_bits(dc->regs, VSDC_FB_CONFIG(output), + VSDC_FB_CONFIG_RESET); +} + +static void vs_dcu_lite_crtc_begin(struct vs_dc *dc, unsigned int output) +{ + regmap_set_bits(dc->regs, VSDC_FB_CONFIG(output), + VSDC_FB_CONFIG_VALID); +} + +static void vs_dcu_lite_crtc_flush(struct vs_dc *dc, unsigned int output) +{ + regmap_clear_bits(dc->regs, VSDC_FB_CONFIG(output), + VSDC_FB_CONFIG_VALID); +} + +static void vs_dcu_lite_crtc_enable(struct vs_dc *dc, unsigned int output) +{ + regmap_set_bits(dc->regs, VSDC_FB_CONFIG(output), + VSDC_FB_CONFIG_ENABLE); +} + +static void vs_dcu_lite_crtc_disable(struct vs_dc *dc, unsigned int output) +{ + regmap_clear_bits(dc->regs, VSDC_FB_CONFIG(output), + VSDC_FB_CONFIG_ENABLE); +} + +static void vs_dcu_lite_enable_vblank(struct vs_dc *dc, unsigned int outpu= t) +{ + regmap_set_bits(dc->regs, VSDC_DISP_IRQ_EN, + VSDC_DISP_IRQ_VSYNC(output)); +} + +static void vs_dcu_lite_disable_vblank(struct vs_dc *dc, unsigned int outp= ut) +{ + regmap_clear_bits(dc->regs, VSDC_DISP_IRQ_EN, + VSDC_DISP_IRQ_VSYNC(output)); +} + +static u32 vs_dcu_lite_irq_handler(struct vs_dc *dc) +{ + u32 irqs; + + regmap_read(dc->regs, VSDC_DISP_IRQ_STA, &irqs); + return irqs; +} + +const struct vs_dc_funcs vs_dcu_lite_funcs =3D { + .bridge_enable =3D vs_dcu_lite_bridge_enable, + .bridge_disable =3D vs_dcu_lite_bridge_disable, + .crtc_begin =3D vs_dcu_lite_crtc_begin, + .crtc_flush =3D vs_dcu_lite_crtc_flush, + .crtc_enable =3D vs_dcu_lite_crtc_enable, + .crtc_disable =3D vs_dcu_lite_crtc_disable, + .enable_vblank =3D vs_dcu_lite_enable_vblank, + .disable_vblank =3D vs_dcu_lite_disable_vblank, + .irq_handler =3D vs_dcu_lite_irq_handler, +}; --=20 2.43.0