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Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Imran Shaik X-Mailer: b4 0.14.2 X-Proofpoint-GUID: dbpSg-NycqYa1O7NFpu3xQOIqN21-YlA X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDE3NCBTYWx0ZWRfX949WUEyioGQi 65Sts2tmnAHrHhGfK2LQgra8SzgSVgvi+DWhZWKrtKF69TbSN0Lm+WtMpPv8SeA/qSRmXuBl5zI W3nBgeIM1PvX+5leygQoeMZ7TXZLsQGHjEXJuU89MgT01eYmwVn2g5XhiIG01Gm3/WiwTqTXv9N KSe7lB0WZdmYC5JsH+N3XNigQo2mY24I7XAdIKhTnzUHHWe9a9wVWTfOP8cUzDOpPVcV+ngI3gx uHVpWMC89KcSbqS6Oa8IJMRA+5AMFU/AK4dOktoaiKvrYqpDtI/o+WZezlvSDWbFOIokAi94b3B rOvhPeEiUZhdHY58fynDrY0CJoCLGpFVGm+jYkXDsMPItUYGqWgEGAjpSOvvVNg7LUP5WTbiWdJ wC7lZ4rNVNtlK/aqh/mhqca/GRi3WY2PqlN1+RXi8j3oZrCoObPHRRt9ZnNt/kULrTRQrQWQ7/p JZvwsJhmOrKfqRP6mLQ== X-Proofpoint-ORIG-GUID: dbpSg-NycqYa1O7NFpu3xQOIqN21-YlA X-Authority-Analysis: v=2.4 cv=SNhykuvH c=1 sm=1 tr=0 ts=6a0c9db0 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=sA6xLUNpRn-UYiqxgCcA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_05,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 bulkscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190174 The Qualcomm Shikra cpufreq hardware is functionally identical to EPSS, but supports only up to 12 frequency lookup table (LUT) entries. Introduce Shikra specific bindings to represent this constrained EPSS variant. Signed-off-by: Imran Shaik --- .../bindings/cpufreq/shikra-cpufreq-qcom-hw.yaml | 133 +++++++++++++++++= ++++ 1 file changed, 133 insertions(+) diff --git a/Documentation/devicetree/bindings/cpufreq/shikra-cpufreq-qcom-= hw.yaml b/Documentation/devicetree/bindings/cpufreq/shikra-cpufreq-qcom-hw.= yaml new file mode 100644 index 0000000000000000000000000000000000000000..52079ed661671554fcca8677409= ee11199f5727b --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/shikra-cpufreq-qcom-hw.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/shikra-cpufreq-qcom-hw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CPUFREQ HW for Qualcomm Shikra SoC + +maintainers: + - Imran Shaik + - Taniya Das + +description: | + + CPUFREQ HW is a hardware engine used by some Qualcomm SoCs to manage + frequency in hardware. It is capable of controlling frequency for + multiple clusters. + + The Qualcomm Shikra CPUFREQ HW supports up to 12 frequency lookup table + (LUT) entries. + +properties: + compatible: + enum: + - qcom,shikra-cpufreq-epss + + reg: + items: + - description: Frequency domain 0 register region + - description: Frequency domain 1 register region + + reg-names: + items: + - const: freq-domain0 + - const: freq-domain1 + + clocks: + items: + - description: XO Clock + - description: GPLL0 Clock + + clock-names: + items: + - const: xo + - const: alternate + + interrupts: + items: + - description: IRQ line for DCVSH 0 + - description: IRQ line for DCVSH 1 + + interrupt-names: + items: + - const: dcvsh-irq-0 + - const: dcvsh-irq-1 + + '#freq-domain-cells': + const: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#freq-domain-cells' + +additionalProperties: false + +examples: + - | + #include + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 0>; + clocks =3D <&cpufreq_hw 0>; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x100>; + enable-method =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 0>; + clocks =3D <&cpufreq_hw 0>; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x200>; + enable-method =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 0>; + clocks =3D <&cpufreq_hw 0>; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78c"; + reg =3D <0x0 0x300>; + enable-method =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 1>; + clocks =3D <&cpufreq_hw 1>; + }; + }; + + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpufreq@fd91000 { + compatible =3D "qcom,shikra-cpufreq-epss"; + reg =3D <0x0fd91000 0x1000>, <0x0fd92000 0x1000>; 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Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Imran Shaik , Konrad Dybcio X-Mailer: b4 0.14.2 X-Proofpoint-GUID: fvLtP8x5IoS_XqQLjAG_cgbfnBpoUSFA X-Authority-Analysis: v=2.4 cv=LcMMLDfi c=1 sm=1 tr=0 ts=6a0c9db5 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=9mH7G91LJRnKxjVXxHoA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-ORIG-GUID: fvLtP8x5IoS_XqQLjAG_cgbfnBpoUSFA X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDE3NCBTYWx0ZWRfX8mLHK3BAd46W pszSK5caAQPFCqZmRLjbneUcX/zH9S9cU/VPco/hvBLP81tjffU2iG9zDpuy3QOqiRiQM5F7uTI iSIT1X9eh8wZJr6O6eDFJuZh/5ImFRWiTlq4MkfkyueTTmuheLA6DVtT2v7ImI3pZZGKbHQ3ILo +vjuEY65399PbyVMW7BcQK1AbWptACPLOOJ1VkjB5vulQTHxiIB9oYeG6e0EHs6ftR/Q+c0HBBv yui9XGwNwMIemydVuFp2NLkUJ/m4KiQ6N1WCsxRtIyDEpQsH40JevVbE6BByi9fx6KZ/Rw/bG8C HQ766VTs850/f1fwTSPYGmPX+RLHmtk7SFzK71Cfi9Fzcotd3QrJ0qejcDXi0BALIyLHS/SG6ES Vu6/hAVdHgVxQRlMddxi9g8sUZvIZx+B5bOjrX76v8YOIQIdhGq32lG1lxVddlkOneycacmTpMa /PX0HilbM7KMGuSRO3A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_05,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 spamscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190174 From: Taniya Das The Qualcomm Shikra cpufreq hardware is functionally identical to EPSS, but supports only up to 12 frequency lookup table (LUT) entries. Hence, add shikra_epss_soc_data that reuses EPSS configuration with appropriate LUT entries limit. Signed-off-by: Taniya Das Reviewed-by: Konrad Dybcio Signed-off-by: Imran Shaik --- drivers/cpufreq/qcom-cpufreq-hw.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufr= eq-hw.c index ea9a20d27b8fdceb9341ee53e5fa27b7a6d92483..d50b868dced309cceb7b49b69df= f933e4bd9e357 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 #include @@ -40,6 +41,7 @@ struct qcom_cpufreq_soc_data { u32 reg_intr_clr; u32 reg_current_vote; u32 reg_perf_state; + u32 lut_max_entries; u8 lut_row_size; }; =20 @@ -156,7 +158,7 @@ static unsigned int qcom_cpufreq_get_freq(struct cpufre= q_policy *policy) soc_data =3D qcom_cpufreq.soc_data; =20 index =3D readl_relaxed(data->base + soc_data->reg_perf_state); - index =3D min(index, LUT_MAX_ENTRIES - 1); + index =3D min(index, soc_data->lut_max_entries - 1); =20 return policy->freq_table[index].frequency; } @@ -211,7 +213,7 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_= dev, struct qcom_cpufreq_data *drv_data =3D policy->driver_data; const struct qcom_cpufreq_soc_data *soc_data =3D qcom_cpufreq.soc_data; =20 - table =3D kzalloc_objs(*table, LUT_MAX_ENTRIES + 1); + table =3D kzalloc_objs(*table, soc_data->lut_max_entries + 1); if (!table) return -ENOMEM; =20 @@ -236,7 +238,7 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_= dev, icc_scaling_enabled =3D false; } =20 - for (i =3D 0; i < LUT_MAX_ENTRIES; i++) { + for (i =3D 0; i < soc_data->lut_max_entries; i++) { data =3D readl_relaxed(drv_data->base + soc_data->reg_freq_lut + i * soc_data->lut_row_size); src =3D FIELD_GET(LUT_SRC, data); @@ -405,6 +407,7 @@ static const struct qcom_cpufreq_soc_data qcom_soc_data= =3D { .reg_current_vote =3D 0x704, .reg_perf_state =3D 0x920, .lut_row_size =3D 32, + .lut_max_entries =3D LUT_MAX_ENTRIES, }; =20 static const struct qcom_cpufreq_soc_data epss_soc_data =3D { @@ -416,11 +419,25 @@ static const struct qcom_cpufreq_soc_data epss_soc_da= ta =3D { .reg_intr_clr =3D 0x308, .reg_perf_state =3D 0x320, .lut_row_size =3D 4, + .lut_max_entries =3D LUT_MAX_ENTRIES, +}; + +static const struct qcom_cpufreq_soc_data shikra_epss_soc_data =3D { + .reg_enable =3D 0x0, + .reg_domain_state =3D 0x20, + .reg_dcvs_ctrl =3D 0xb0, + .reg_freq_lut =3D 0x100, + .reg_volt_lut =3D 0x200, + .reg_intr_clr =3D 0x308, + .reg_perf_state =3D 0x320, + .lut_row_size =3D 4, + .lut_max_entries =3D 12, }; =20 static const struct of_device_id qcom_cpufreq_hw_match[] =3D { { .compatible =3D "qcom,cpufreq-hw", .data =3D &qcom_soc_data }, { .compatible =3D "qcom,cpufreq-epss", .data =3D &epss_soc_data }, + { .compatible =3D "qcom,shikra-cpufreq-epss", .data =3D &shikra_epss_soc_= data }, {} }; MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match); --=20 2.34.1