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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-134cbed2232sm23323747c88.7.2026.05.19.00.17.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 May 2026 00:17:58 -0700 (PDT) From: Hangxiang Ma Date: Tue, 19 May 2026 00:17:56 -0700 Subject: [PATCH 1/3] arm64: dts: qcom: sm8750: Add camss node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260519-pakala-camera-v1-1-b6d897864916@oss.qualcomm.com> References: <20260519-pakala-camera-v1-0-b6d897864916@oss.qualcomm.com> In-Reply-To: <20260519-pakala-camera-v1-0-b6d897864916@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma X-Mailer: b4 0.14.3 X-Proofpoint-GUID: H8B-ha77gdgt2xA-unLE8wK0fhFXpBSG X-Proofpoint-ORIG-GUID: H8B-ha77gdgt2xA-unLE8wK0fhFXpBSG X-Authority-Analysis: v=2.4 cv=a9sAM0SF c=1 sm=1 tr=0 ts=6a0c0ea9 cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=T-Dl8XKw7-qrnIs-YWIA:9 a=es2bXTfkhrpURJIW:21 a=QEXdDO2ut3YA:10 a=vr4QvYf-bLy2KjpDp97w:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA3MCBTYWx0ZWRfX52ReTBjKFs+s mokr4cSvpv6EoMJhvKiPUonQHx5RYJr3S+otjihMCyVJro4YF9on3VQK62dvwPmDbYRZ2/jRIoN NYJKyrWRUW+SC9bi5xBvuNSWvM1IkiAs5aJKnSydXhd7ocGzJngUzlYH5CWxiYEz1BH9aX9yozT v2Lk4Jtf6JagNTV91VxwV6TZKVuo+F1zSb56X9ig1a/Fsos+YNM+UV8/FVibSAx3Svm9qajP2ic 8fxpI+Q3AlibaiRhj6ER5px/ltQ9nPf+C1UYhkgSdQEeTvPCMwyCEuURg0KDtRYUNXLSRkcRcZj bYulEERmDw2FLuio5xzOIHaiipFpaPPHPPRFrewDW6zWnE/zsy3+swXbPEx+gByLM9C2SQzNho7 5SAePIWiNOhwW87atheaxAK1sf1kCWsXbBcK23BfODAQRwVVA1uHtc+O3dhV89wYwYYWpLa10Su esSV5VGnHoRGq9dwFcg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 impostorscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 suspectscore=0 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190070 Add node for the SM8750 camera subsystem. Signed-off-by: Hangxiang Ma --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 203 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 203 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index 70830cb49e73..8ed3d8c791e3 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -3032,6 +3032,209 @@ videocc: clock-controller@aaf0000 { #power-domain-cells =3D <1>; }; =20 + camss: isp@ad27000 { + compatible =3D "qcom,sm8750-camss"; + + reg =3D <0x0 0x0ad27000 0x0 0x2b00>, + <0x0 0x0ad2a000 0x0 0x2b00>, + <0x0 0x0ad2d000 0x0 0x2b00>, + <0x0 0x0ad6d000 0x0 0xa00>, + <0x0 0x0ad72000 0x0 0xa00>, + <0x0 0x0ada9000 0x0 0x2000>, + <0x0 0x0adab000 0x0 0x2000>, + <0x0 0x0adad000 0x0 0x2000>, + <0x0 0x0adaf000 0x0 0x2000>, + <0x0 0x0adb1000 0x0 0x2000>, + <0x0 0x0adb3000 0x0 0x2000>, + <0x0 0x0ad8b000 0x0 0x400>, + <0x0 0x0ad8c000 0x0 0x400>, + <0x0 0x0ad8d000 0x0 0x400>, + <0x0 0x0ac86000 0x0 0x10000>, + <0x0 0x0ac96000 0x0 0x10000>, + <0x0 0x0aca6000 0x0 0x10000>, + <0x0 0x0ad6e000 0x0 0x3000>, + <0x0 0x0ad73000 0x0 0x3000>; + reg-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "csitpg0", + "csitpg1", + "csitpg2", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + clocks =3D <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>, + <&camcc CAM_CC_CAM_TOP_AHB_CLK>, + <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-names =3D "camnoc_nrt_axi", + "camnoc_rt_axi", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe2", + "cpas_vfe_lite", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "gcc_axi_hf", + "gcc_axi_sf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe2", + "vfe2_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid", + "qdss_debug_xo"; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_NRT_ICP_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "ahb", + "hf_mnoc", + "sf_mnoc", + "sf_icp_mnoc"; + + iommus =3D <&apps_smmu 0x1c00 0x00>; + + power-domains =3D <&camcc CAM_CC_TFE_0_GDSC>, + <&camcc CAM_CC_TFE_1_GDSC>, + <&camcc CAM_CC_TFE_2_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names =3D "ife0", + "ife1", + "ife2", + "top"; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + }; + + port@2 { + reg =3D <2>; + }; + + port@3 { + reg =3D <3>; + }; + + port@4 { + reg =3D <4>; + }; + + port@5 { + reg =3D <5>; + }; + }; + + }; + mdss: display-subsystem@ae00000 { compatible =3D "qcom,sm8750-mdss"; reg =3D <0x0 0x0ae00000 0x0 0x1000>; --=20 2.34.1 From nobody Mon May 25 03:55:49 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2246D3CF042 for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-134cbed2232sm23323747c88.7.2026.05.19.00.17.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 May 2026 00:17:59 -0700 (PDT) From: Hangxiang Ma Date: Tue, 19 May 2026 00:17:57 -0700 Subject: [PATCH 2/3] arm64: dts: qcom: sm8750: Add CCI definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260519-pakala-camera-v1-2-b6d897864916@oss.qualcomm.com> References: <20260519-pakala-camera-v1-0-b6d897864916@oss.qualcomm.com> In-Reply-To: <20260519-pakala-camera-v1-0-b6d897864916@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA3MCBTYWx0ZWRfX+CMvQZ5ooUuq DyTFc7CS3EZuGKy+djDwulWd67xoZQWDcDBZQ6npeffae1+Flg5nU087fJKBKaI7IlNPG71yyqu nSn0OaUwLAPFxz9634tVCD6gGjb4unF2Ma0gESh7Qch2bzYn8VB88bLLL2ZQWEZ5L5+k/rZX8Pw FhifWXO2Fm+CLYtSnlN709eh/mMx0OaCbZwyKlkXKcz+5cSL425nQaebpqBMh3UDODs4pszWMG/ abklOsemudFbuHLhLmfgn7bdoBMMLPLvxaCUYs6C5KyEsde0Hgkp2HG8UrsPuOSJgcjyHCj1rSn SPg7nzuSbHjM/D/SKPgaXj2h3LSvuujAAZkT/1lcu2bu09rc9ottg2Ya4c7naL2L3ZY6EEzkEK5 LT1LAeowzDPjFO6Nk08Hxqwh7v6cuRHNzTxvHz691xtQySYZKahBBBOSqC8RSE7ZXbhS3Lb4u0b NxI9fsUkTBsPoz7NufA== X-Proofpoint-GUID: Jp_FcaO-Ly0Bf1Q9W2rfs97ki4dZy724 X-Proofpoint-ORIG-GUID: Jp_FcaO-Ly0Bf1Q9W2rfs97ki4dZy724 X-Authority-Analysis: v=2.4 cv=WZM8rUhX c=1 sm=1 tr=0 ts=6a0c0eaa cx=c_pps a=bS7HVuBVfinNPG3f6cIo3Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=--cV21oE9J2x1QxDxCAA:9 a=QEXdDO2ut3YA:10 a=vBUdepa8ALXHeOFLBtFW:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 phishscore=0 spamscore=0 impostorscore=0 adultscore=0 bulkscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190070 Qualcomm SM8750 SoC has three Camera Control Interface (CCI). Each controller contains two I2C hosts. Signed-off-by: Hangxiang Ma --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 282 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 282 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index 8ed3d8c791e3..7570189fdb5d 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -3032,6 +3032,96 @@ videocc: clock-controller@aaf0000 { #power-domain-cells =3D <1>; }; =20 + cci0: cci@ac7b000 { + compatible =3D "qcom,sm8750-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac7b000 0x0 0x1000>; + interrupts =3D ; + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks =3D <&camcc CAM_CC_CAM_TOP_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names =3D "ahb", "cci"; + pinctrl-0 =3D <&cci0_0_default &cci0_1_default>; + pinctrl-1 =3D <&cci0_0_sleep &cci0_1_sleep>; + pinctrl-names =3D "default", "sleep"; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + cci0_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci1: cci@ac7c000 { + compatible =3D "qcom,sm8750-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac7c000 0x0 0x1000>; + interrupts =3D ; + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks =3D <&camcc CAM_CC_CAM_TOP_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names =3D "ahb", "cci"; + pinctrl-0 =3D <&cci1_0_default &cci1_1_default>; + pinctrl-1 =3D <&cci1_0_sleep &cci1_1_sleep>; + pinctrl-names =3D "default", "sleep"; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + cci1_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci2: cci@ac7d000 { + compatible =3D "qcom,sm8750-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac7d000 0x0 0x1000>; + interrupts =3D ; + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks =3D <&camcc CAM_CC_CAM_TOP_AHB_CLK>, + <&camcc CAM_CC_CCI_2_CLK>; + clock-names =3D "ahb", "cci"; + pinctrl-0 =3D <&cci2_0_default &cci2_1_default>; + pinctrl-1 =3D <&cci2_0_sleep &cci2_1_sleep>; + pinctrl-names =3D "default", "sleep"; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + cci2_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci2_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + camss: isp@ad27000 { compatible =3D "qcom,sm8750-camss"; =20 @@ -3804,6 +3894,198 @@ tlmm: pinctrl@f100000 { gpio-ranges =3D <&tlmm 0 0 216>; wakeup-parent =3D <&pdc>; =20 + cci0_0_default: cci0-0-default-state { + sda-pins { + pins =3D "gpio113"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up; + }; + + scl-pins { + pins =3D "gpio114"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci0_0_sleep: cci0-0-sleep-state { + sda-pins { + pins =3D "gpio113"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio114"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci0_1_default: cci0-1-default-state { + sda-pins { + pins =3D "gpio115"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up; + }; + + scl-pins { + pins =3D "gpio116"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci0_1_sleep: cci0-1-sleep-state { + sda-pins { + pins =3D "gpio115"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio116"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci1_0_default: cci1-0-default-state { + sda-pins { + pins =3D "gpio117"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up; + }; + + scl-pins { + pins =3D "gpio118"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci1_0_sleep: cci1-0-sleep-state { + sda-pins { + pins =3D "gpio117"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio118"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci1_1_default: cci1-1-default-state { + sda-pins { + pins =3D "gpio111"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up; + }; + + scl-pins { + pins =3D "gpio164"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci1_1_sleep: cci1-1-sleep-state { + sda-pins { + pins =3D "gpio111"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio164"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci2_0_default: cci2-0-default-state { + sda-pins { + pins =3D "gpio112"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up; + }; + + scl-pins { + pins =3D "gpio153"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci2_0_sleep: cci2-0-sleep-state { + sda-pins { + pins =3D "gpio112"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio153"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci2_1_default: cci2-1-default-state { + sda-pins { + pins =3D "gpio119"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up; + }; + + scl-pins { + pins =3D "gpio120"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci2_1_sleep: cci2-1-sleep-state { + sda-pins { + pins =3D "gpio119"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio120"; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-134cbed2232sm23323747c88.7.2026.05.19.00.18.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 May 2026 00:18:01 -0700 (PDT) From: Hangxiang Ma Date: Tue, 19 May 2026 00:17:58 -0700 Subject: [PATCH 3/3] arm64: dts: qcom: sm8750: Add camera MCLK pinctrl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260519-pakala-camera-v1-3-b6d897864916@oss.qualcomm.com> References: <20260519-pakala-camera-v1-0-b6d897864916@oss.qualcomm.com> In-Reply-To: <20260519-pakala-camera-v1-0-b6d897864916@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma X-Mailer: b4 0.14.3 X-Authority-Analysis: v=2.4 cv=Rt316imK c=1 sm=1 tr=0 ts=6a0c0eaa cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=ze2PbGEXSmdAYQ4Rbr8A:9 a=QEXdDO2ut3YA:10 a=vr4QvYf-bLy2KjpDp97w:22 X-Proofpoint-ORIG-GUID: wiYDgZBg-126pm5Sia8QX3qpl081ecKn X-Proofpoint-GUID: wiYDgZBg-126pm5Sia8QX3qpl081ecKn X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA3MCBTYWx0ZWRfXxMELKPqUvdY9 OWS3Zh0fpxP9eFZMb7K0in99cg27dI5Z9jSaQigVZKcvhDPh23he0WnKPlXY8uv6kz0Sjw+G1Sm 5pueMY2xjzbaLtthTdHQ8vmkvy1lddup6SD9X4AuGe8sAesAptZoKcHQ3GUoqKiZ/HmEe2MCsZJ 7HnJhV/GBssFy3MTKnc+KO1Xh3tc+9nkS5xos1WJnGHSWExdePtgudvV17gX9//3BkALrKBhNK+ zT1gqy7bcUuU+z3TNuRiTEvyhgwXoXpdKJ1eDzDvTC2XlSPuVWK3V5x7aA2073KVDAUJ1o+NqvU ZH82kH7AnUUbCPWtc1O8zcRy+Tq+7LgXIpvawR0IdSflmbQEZ3Ic57mKahXGYjWcRw9/1S97+93 7lzUtaUibkKaQwKDbmw4r5ztkg/wTfbDCgrdbKj0bXw4JtUiQyg/wCwc+bx4BwuqRIgRYYxxC9g kEnv3I8a3Q5DBMhnLNw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 phishscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190070 Define pinctrl definitions to enable camera master clocks on SM8750. Signed-off-by: Hangxiang Ma Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 56 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index 7570189fdb5d..84ab550db2f4 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -3894,6 +3894,62 @@ tlmm: pinctrl@f100000 { gpio-ranges =3D <&tlmm 0 0 216>; wakeup-parent =3D <&pdc>; =20 + cam0_default: cam0-default-state { + pins =3D "gpio89"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + + cam1_default: cam1-default-state { + pins =3D "gpio90"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + + cam2_default: cam2-default-state { + pins =3D "gpio91"; + function =3D "cam_asc_mclk2"; + drive-strength =3D <2>; + bias-disable; + }; + + cam3_default: cam3-default-state { + pins =3D "gpio92"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + + cam4_default: cam4-default-state { + pins =3D "gpio93"; + function =3D "cam_asc_mclk4"; + drive-strength =3D <2>; + bias-disable; + }; + + cam5_default: cam5-default-state { + pins =3D "gpio94"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + + cam6_default: cam6-default-state { + pins =3D "gpio95"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + + cam7_default: cam7-default-state { + pins =3D "gpio96"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + cci0_0_default: cci0-0-default-state { sda-pins { pins =3D "gpio113"; --=20 2.34.1