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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bd5d12372bsm230501035ad.75.2026.05.19.06.15.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 May 2026 06:15:10 -0700 (PDT) From: Jie Gan Date: Tue, 19 May 2026 21:14:56 +0800 Subject: [PATCH v5] arm64: dts: qcom: glymur: add coresight nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260519-add-coresight-nodes-for-glymur-v5-1-3dad99fe31e0@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAFBiDGoC/43NsQ6CMBDG8VchnT0CtNXWyfcwDoVeoYlQbaGRE N7dwuRgossl/xt+30ICeouBnLOFeIw2WDek4IeMNJ0aWgSrU5OqqI4FLzkoraFxHoNtuxEGpzG AcR7a+9xPHpgsGFdKokZBEvLwaOxrH7jeUnc2jM7P+16k2/dvOlIoQVBVU6nr6sT1xYWQPyd1b 1zf5+mQbSGyT1X8VFlSGTecGcZKIeUXdV3XN3dSS7opAQAA To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jie Gan X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779196507; l=23912; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=wBpUw5EPiTr71C3EqwDm03gDzBovj3oITIiWu/Fpqhg=; b=fSj0HoPWzc5RfxIXbI8lLaqzOCa8eYrTr/GyVQehI4fl+RZ38WJ5hoHOPGd/61vlPRbboXxV2 P+eZSrgVs23DwkvlgqFHCPnBD/2Ex6+y3/bHnGV5qb0FuHJ2nEFXL6o X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Authority-Analysis: v=2.4 cv=MfBcfZ/f c=1 sm=1 tr=0 ts=6a0c6261 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=Ym7NTek2rUbMElXwnXkA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: WraGt08uOFUbwaRY_kyzNHkFA8ssC00V X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDEzMSBTYWx0ZWRfXz1vhUerbYUVS 1Z4Wh1cydAlwUgoCajiUUmx0aXURqJyk/eoodYuqNNzElcK2LxIgG/40/PlVnIuIXyalgPWvO0y RDxbT9wRMOAvGFdfdzgzODzTHkhp8A5xpL4Dvs3FmQCjoK3YeaUH4bwBdPRYe4sKVfxR3dEzxlI kwAlfT9MZA0HMizpaywnFNiZRRDhNcE1UDA1g0L1rh/6LfChtBupaWwHeyZluuvkm5ppHx566Hh Z9pGiZryebo0hPtRaf2G/IK4+mDEKorF7j8b2cI/cRBmB/8PW4sgFq5aCQLzV9/oEUVEWDnl5AU OCppmp0mZcqHQVMUYsLZZ0Ewj+Glf+fBPCcKiaZew+kJg5Vp1vLViOLigvT4mWFaxzzRHjFFSjf LI40po6clP5lZCfMPX2OVYu4I/rrPIRXikeTzus4ql5iGS+mKg1AldbG0b2WB4R6FFOidPfA/T6 uvbw+p7C2CveJEaXQDA== X-Proofpoint-ORIG-GUID: WraGt08uOFUbwaRY_kyzNHkFA8ssC00V X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 adultscore=0 malwarescore=0 bulkscore=0 impostorscore=0 spamscore=0 phishscore=0 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190131 Add CoreSight nodes to enable trace paths like TPDM->ETF/STM->ETF. These devices are part of the AOSS, CDSP, QDSS, PCIe5, TraceNoc and some small subsystems, such as GCC, IPCC, PMU and so on. Delete cti_wpss DT node on Mahua since this device will cause NoC issue on Mahua device. Signed-off-by: Jie Gan --- Changes in v5: 1. change the compatible of the traceNoC device to platform driver compatible: qcom,coresight-itnoc Link to v4: https://lore.kernel.org/r/20260518-add-coresight-nodes-for-glym= ur-v4-1-45f54f441899@oss.qualcomm.com Changes in v4: 1. fix the wrong MMIO size for the traceNoC device: tn@11200000 Link to v3: https://lore.kernel.org/r/20260515-add-coresight-nodes-for-glym= ur-v3-1-83ab39db275d@oss.qualcomm.com Changes in V3: 1. Delete cti_wpss node in Mahua to prevent crash issue Link to V2 - https://lore.kernel.org/all/20260318-add-coresight-dt-nodes-fo= r-glymur-v2-1-d76e08f21fa5@oss.qualcomm.com/ Changes in V2: 1. removed two cti devices due to GFX block is down - cti@11c42000 - cti@11c4b000 2. changes two TPDM devices to static: - tpdm-cdsp-cmsr - tpdm-cdsp-cmsr2 Link to v1 - https://lore.kernel.org/all/20251230-add-coresight-nodes-for-g= lymur-v1-1-103b6d24f1ca@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/glymur.dtsi | 1097 ++++++++++++++++++++++++++++++= ++++ arch/arm64/boot/dts/qcom/mahua.dtsi | 1 + 2 files changed, 1098 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index 0c5cb8532b20..a606235bdb4b 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -341,6 +341,18 @@ domain_ss3: domain-sleep-0 { }; }; =20 + dummy-sink { + compatible =3D "arm,coresight-dummy-sink"; + + in-ports { + port { + eud_in: endpoint { + remote-endpoint =3D <&swao_rep_out1>; + }; + }; + }; + }; + firmware { scm: scm { compatible =3D "qcom,scm-glymur", "qcom,scm"; @@ -5501,6 +5513,1035 @@ rx-pins { }; }; =20 + stm: stm@10002000 { + compatible =3D "arm,coresight-stm", "arm,primecell"; + reg =3D <0x0 0x10002000 0x0 0x1000>, + <0x0 0x16280000 0x0 0x180000>; + reg-names =3D "stm-base", + "stm-stimulus-base"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint =3D <&funnel0_in7>; + }; + }; + }; + }; + + tpda@10004000 { + compatible =3D "qcom,coresight-tpda", "arm,primecell"; + reg =3D <0x0 0x10004000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <1>; + + qdss_tpda_in1: endpoint { + remote-endpoint =3D <&spdm_tpdm_out>; + }; + }; + }; + + out-ports { + port { + qdss_tpda_out: endpoint { + remote-endpoint =3D <&funnel0_in6>; + }; + }; + }; + }; + + tpdm@1000f000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1000f000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <32>; + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + spdm_tpdm_out: endpoint { + remote-endpoint =3D <&qdss_tpda_in1>; + }; + }; + }; + }; + + funnel@10041000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x10041000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + funnel0_in0: endpoint { + remote-endpoint =3D <&tn_ag_out>; + }; + }; + + port@6 { + reg =3D <6>; + + funnel0_in6: endpoint { + remote-endpoint =3D <&qdss_tpda_out>; + }; + }; + + port@7 { + reg =3D <7>; + + funnel0_in7: endpoint { + remote-endpoint =3D <&stm_out>; + }; + }; + }; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint =3D <&aoss_funnel_in6>; + }; + }; + }; + }; + + tpdm@1102c000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1102c000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + gcc_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in36>; + }; + }; + }; + }; + + tpdm@11180000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11180000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-element-bits =3D <32>; + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + cdsp_tpdm_out: endpoint { + remote-endpoint =3D <&cdsp_tpda_in0>; + }; + }; + }; + }; + + tpdm@11185000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11185000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + cdsp_dpm1_tpdm_out: endpoint { + remote-endpoint =3D <&cdsp_tpda_in5>; + }; + }; + }; + }; + + tpdm@11186000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11186000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + cdsp_dpm2_tpdm_out: endpoint { + remote-endpoint =3D <&cdsp_tpda_in6>; + }; + }; + }; + }; + + tpda@11188000 { + compatible =3D "qcom,coresight-tpda", "arm,primecell"; + reg =3D <0x0 0x11188000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + cdsp_tpda_in0: endpoint { + remote-endpoint =3D <&cdsp_tpdm_out>; + }; + }; + + port@1 { + reg =3D <1>; + + cdsp_tpda_in1: endpoint { + remote-endpoint =3D <&cdsp_llm_tpdm_out>; + }; + }; + + port@2 { + reg =3D <2>; + + cdsp_tpda_in2: endpoint { + remote-endpoint =3D <&cdsp_llm2_tpdm_out>; + }; + }; + + port@3 { + reg =3D <3>; + + cdsp_tpda_in3: endpoint { + remote-endpoint =3D <&cdsp_cmsr_tpdm_out>; + }; + }; + + port@4 { + reg =3D <4>; + + cdsp_tpda_in4: endpoint { + remote-endpoint =3D <&cdsp_cmsr2_tpdm_out>; + }; + }; + + port@5 { + reg =3D <5>; + + cdsp_tpda_in5: endpoint { + remote-endpoint =3D <&cdsp_dpm1_tpdm_out>; + }; + }; + + port@6 { + reg =3D <6>; + + cdsp_tpda_in6: endpoint { + remote-endpoint =3D <&cdsp_dpm2_tpdm_out>; + }; + }; + }; + + out-ports { + port { + cdsp_tpda_out: endpoint { + remote-endpoint =3D <&cdsp_funnel_in0>; + }; + }; + }; + }; + + funnel@11189000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x11189000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + cdsp_funnel_in0: endpoint { + remote-endpoint =3D <&cdsp_tpda_out>; + }; + }; + }; + + out-ports { + port { + cdsp_funnel_out: endpoint { + remote-endpoint =3D <&tn_ag_in53>; + }; + }; + }; + }; + + cti@11193000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x11193000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + }; + + cti_wpss: cti@111ab000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x111ab000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + }; + + tpdm@111d0000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111d0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + qm_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in35>; + }; + }; + }; + }; + + tn@11200000 { + compatible =3D "qcom,coresight-itnoc"; + reg =3D <0x0 0x11200000 0x0 0x3c00>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@6 { + reg =3D <6>; + + tn_ag_in6: endpoint { + remote-endpoint =3D <&mm_dsb_tpdm_out>; + }; + }; + + port@10 { + reg =3D <0x10>; + + tn_ag_in16: endpoint { + remote-endpoint =3D <&east_dsb_tpdm_out>; + }; + }; + + port@21 { + reg =3D <0x21>; + + tn_ag_in33: endpoint { + remote-endpoint =3D <&west_dsb_tpdm_out>; + }; + }; + + port@23 { + reg =3D <0x23>; + + tn_ag_in35: endpoint { + remote-endpoint =3D <&qm_tpdm_out>; + }; + }; + + port@24 { + reg =3D <0x24>; + + tn_ag_in36: endpoint { + remote-endpoint =3D <&gcc_tpdm_out>; + }; + }; + + port@32 { + reg =3D <0x32>; + + tn_ag_in50: endpoint { + remote-endpoint =3D <&pcie_rscc_tpda_out>; + }; + }; + + port@35 { + reg =3D <0x35>; + + tn_ag_in53: endpoint { + remote-endpoint =3D <&cdsp_funnel_out>; + }; + }; + + port@3f { + reg =3D <0x3f>; + + tn_ag_in63: endpoint { + remote-endpoint =3D <¢er_dsb_tpdm_out>; + }; + }; + + port@40 { + reg =3D <0x40>; + + tn_ag_in64: endpoint { + remote-endpoint =3D <&ipcc_cmb_tpdm_out>; + }; + }; + + port@41 { + reg =3D <0x41>; + + tn_ag_in65: endpoint { + remote-endpoint =3D <&qrng_tpdm_out>; + }; + }; + + port@42 { + reg =3D <0x42>; + + tn_ag_in66: endpoint { + remote-endpoint =3D <&pmu_tpdm_out>; + }; + }; + + port@43 { + reg =3D <0x43>; + + tn_ag_in67: endpoint { + remote-endpoint =3D <&rdpm_west_cmb0_tpdm_out>; + }; + }; + + port@44 { + reg =3D <0x44>; + + tn_ag_in68: endpoint { + remote-endpoint =3D <&rdpm_west_cmb1_tpdm_out>; + }; + }; + + port@45 { + reg =3D <0x45>; + + tn_ag_in69: endpoint { + remote-endpoint =3D <&rdpm_west_cmb2_tpdm_out>; + }; + }; + + port@4b { + reg =3D <0x4b>; + + tn_ag_in75: endpoint { + remote-endpoint =3D <&south_dsb2_tpdm_out>; + }; + }; + + port@52 { + reg =3D <0x52>; + + tn_ag_in82: endpoint { + remote-endpoint =3D <&south_dsb_tpdm_out>; + }; + }; + + port@53 { + reg =3D <0x53>; + + tn_ag_in83: endpoint { + remote-endpoint =3D <¢er_dsb1_tpdm_out>; + }; + }; + }; + + out-ports { + port { + tn_ag_out: endpoint { + remote-endpoint =3D <&funnel0_in0>; + }; + }; + }; + }; + + tpdm@11207000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11207000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + mm_dsb_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in6>; + }; + }; + }; + }; + + tpdm@1120b000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1120b000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + east_dsb_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in16>; + }; + }; + }; + }; + + tpdm@11213000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11213000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + west_dsb_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in33>; + }; + }; + }; + }; + + tpdm@11219000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11219000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + center_dsb_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in63>; + }; + }; + }; + }; + + tpdm@1121a000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1121a000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + ipcc_cmb_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in64>; + }; + }; + }; + }; + + tpdm@1121b000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1121b000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + qrng_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in65>; + }; + }; + }; + }; + + tpdm@1121c000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1121c000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + pmu_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in66>; + }; + }; + }; + }; + + tpdm@1121d000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1121d000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + rdpm_west_cmb0_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in67>; + }; + }; + }; + }; + + tpdm@1121e000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1121e000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + rdpm_west_cmb1_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in68>; + }; + }; + }; + }; + + tpdm@1121f000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1121f000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + rdpm_west_cmb2_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in69>; + }; + }; + }; + }; + + tpdm@11220000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11220000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + center_dsb1_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in83>; + }; + }; + }; + }; + + tpdm@11224000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11224000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + south_dsb2_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in75>; + }; + }; + }; + }; + + tpdm@11228000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11228000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + south_dsb_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in82>; + }; + }; + }; + }; + + tpdm@11470000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11470000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <32>; + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + pcie_rscc_tpdm_out: endpoint { + remote-endpoint =3D <&pcie_rscc_tpda_in0>; + }; + }; + }; + }; + + tpda@11471000 { + compatible =3D "qcom,coresight-tpda", "arm,primecell"; + reg =3D <0x0 0x11471000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + pcie_rscc_tpda_in0: endpoint { + remote-endpoint =3D <&pcie_rscc_tpdm_out>; + }; + }; + }; + + out-ports { + port { + pcie_rscc_tpda_out: endpoint { + remote-endpoint =3D <&tn_ag_in50>; + }; + }; + }; + }; + + tpdm@11c03000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11c03000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + swao_prio4_tpdm_out: endpoint { + remote-endpoint =3D <&aoss_tpda_in4>; + }; + }; + }; + }; + + funnel@11c04000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x11c04000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@5 { + reg =3D <5>; + + aoss_funnel_in5: endpoint { + remote-endpoint =3D <&aoss_tpda_out>; + }; + }; + + port@6 { + reg =3D <6>; + + aoss_funnel_in6: endpoint { + remote-endpoint =3D <&funnel0_out>; + }; + }; + }; + + out-ports { + port { + aoss_funnel_out: endpoint { + remote-endpoint =3D <&etf0_in>; + }; + }; + }; + }; + + tmc_etf: tmc@11c05000 { + compatible =3D "arm,coresight-tmc", "arm,primecell"; + reg =3D <0x0 0x11c05000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + etf0_in: endpoint { + remote-endpoint =3D <&aoss_funnel_out>; + }; + }; + }; + + out-ports { + port { + etf0_out: endpoint { + remote-endpoint =3D <&swao_rep_in>; + }; + }; + }; + }; + + replicator@11c06000 { + compatible =3D "arm,coresight-dynamic-replicator", "arm,primecell"; + reg =3D <0x0 0x11c06000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + swao_rep_in: endpoint { + remote-endpoint =3D <&etf0_out>; + }; + }; + }; + + out-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <1>; + + swao_rep_out1: endpoint { + remote-endpoint =3D <&eud_in>; + }; + }; + }; + }; + + tpda@11c08000 { + compatible =3D "qcom,coresight-tpda", "arm,primecell"; + reg =3D <0x0 0x11c08000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + aoss_tpda_in0: endpoint { + remote-endpoint =3D <&swao_prio0_tpdm_out>; + }; + }; + + port@1 { + reg =3D <1>; + + aoss_tpda_in1: endpoint { + remote-endpoint =3D <&swao_prio1_tpdm_out>; + }; + }; + + port@2 { + reg =3D <2>; + + aoss_tpda_in2: endpoint { + remote-endpoint =3D <&swao_prio2_tpdm_out>; + }; + }; + + port@3 { + reg =3D <3>; + + aoss_tpda_in3: endpoint { + remote-endpoint =3D <&swao_prio3_tpdm_out>; + }; + }; + + port@4 { + reg =3D <4>; + + aoss_tpda_in4: endpoint { + remote-endpoint =3D <&swao_prio4_tpdm_out>; + }; + }; + + port@5 { + reg =3D <5>; + + aoss_tpda_in5: endpoint { + remote-endpoint =3D <&swao_tpdm_out>; + }; + }; + }; + + out-ports { + port { + aoss_tpda_out: endpoint { + remote-endpoint =3D <&aoss_funnel_in5>; + }; + }; + }; + }; + + tpdm@11c09000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11c09000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + swao_prio0_tpdm_out: endpoint { + remote-endpoint =3D <&aoss_tpda_in0>; + }; + }; + }; + }; + + tpdm@11c0a000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11c0a000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + swao_prio1_tpdm_out: endpoint { + remote-endpoint =3D <&aoss_tpda_in1>; + }; + }; + }; + }; + + tpdm@11c0b000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11c0b000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + swao_prio2_tpdm_out: endpoint { + remote-endpoint =3D <&aoss_tpda_in2>; + }; + }; + }; + }; + + tpdm@11c0c000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11c0c000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + swao_prio3_tpdm_out: endpoint { + remote-endpoint =3D <&aoss_tpda_in3>; + }; + }; + }; + }; + + tpdm@11c0d000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11c0d000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-element-bits =3D <32>; + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + swao_tpdm_out: endpoint { + remote-endpoint =3D <&aoss_tpda_in5>; + }; + }; + }; + }; + apps_smmu: iommu@15000000 { compatible =3D "qcom,glymur-smmu-500", "qcom,smmu-500", @@ -7132,4 +8173,60 @@ gpuss-1-critical { }; }; }; + + tpdm-cdsp-llm { + compatible =3D "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits =3D <32>; + + out-ports { + port { + cdsp_llm_tpdm_out: endpoint { + remote-endpoint =3D <&cdsp_tpda_in1>; + }; + }; + }; + }; + + tpdm-cdsp-llm2 { + compatible =3D "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits =3D <32>; + + out-ports { + port { + cdsp_llm2_tpdm_out: endpoint { + remote-endpoint =3D <&cdsp_tpda_in2>; + }; + }; + }; + }; + + tpdm-cdsp-cmsr { + compatible =3D "qcom,coresight-static-tpdm"; + + qcom,cmb-element-bits =3D <32>; + qcom,dsb-element-bits =3D <32>; + + out-ports { + port { + cdsp_cmsr_tpdm_out: endpoint { + remote-endpoint =3D <&cdsp_tpda_in3>; + }; + }; + }; + }; + + tpdm-cdsp-cmsr2 { + compatible =3D "qcom,coresight-static-tpdm"; + + qcom,cmb-element-bits =3D <32>; + qcom,dsb-element-bits =3D <32>; + + out-ports { + port { + cdsp_cmsr2_tpdm_out: endpoint { + remote-endpoint =3D <&cdsp_tpda_in4>; + }; + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom= /mahua.dtsi index 990a02c6afc1..22822b6b2e8b 100644 --- a/arch/arm64/boot/dts/qcom/mahua.dtsi +++ b/arch/arm64/boot/dts/qcom/mahua.dtsi @@ -21,6 +21,7 @@ /delete-node/ &cpu_pd15; /delete-node/ &cpu_pd16; /delete-node/ &cpu_pd17; +/delete-node/ &cti_wpss; /delete-node/ &thermal_aoss_6; /delete-node/ &thermal_aoss_7; /delete-node/ &thermal_cpu_2_0_0; --- base-commit: e98d21c170b01ddef366f023bbfcf6b31509fa83 change-id: 20260515-add-coresight-nodes-for-glymur-49045aa9ede8 Best regards, --=20 Jie Gan