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Signed-off-by: Janani Sunil --- .../devicetree/bindings/iio/dac/adi,ad5529r.yaml | 217 +++++++++++++++++= ++++ MAINTAINERS | 7 + 2 files changed, 224 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5529r.yaml b/D= ocumentation/devicetree/bindings/iio/dac/adi,ad5529r.yaml new file mode 100644 index 000000000000..eb66f6ca063d --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5529r.yaml @@ -0,0 +1,217 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/dac/adi,ad5529r.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD5529R 16-Channel 12/16-bit High Voltage DAC + +maintainers: + - Janani Sunil + +description: | + The AD5529R is a 16-channel, 12-bit or 16-bit, high voltage, buffered vo= ltage output + digital-to-analog converter (DAC) with an integrated precision reference. + The device operates from unipolar and bipolar supplies. It is guaranteed + monotonic and has built-in rail-to-rail output buffers that can source or + sink up to 25mA. + + Specifications: + * 16 independent 12-bit or 16-bit DAC channels + * Independently programmable output ranges: 0V to 5V, 0V to 10V, 0V to 2= 0V, + 0V to 40V, =C2=B15V, =C2=B110V, =C2=B115V, and =C2=B120V + * The device supports SPI communication with Mode 0 and Mode 3. + * 4.096V precision reference, 12ppm/=C2=B0C maximum + * Built-in function generation: Toggle, Sinusoidal Dither, and Ramp wave= forms + * Multiplexer for output voltage, load current sense and die temperature + + Datasheet: https://www.analog.com/media/en/technical-documentation/data-= sheets/ad5529r.pdf + +properties: + compatible: + enum: + - adi,ad5529r-16 # 16-bit variant + - adi,ad5529r-12 # 12-bit variant + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 25000000 + description: + Maximum SPI frequency. The device supports SPI Mode 0 and Mode 3. + Read operations are limited to 25MHz maximum. + + reset-gpios: + maxItems: 1 + description: + GPIO connected to the RESET pin. Active low. When asserted low, + performs a power-on reset and initializes the device to its default = state. + + clear-gpios: + maxItems: 1 + description: + GPIO connected to the CLEAR pin. Active low. When asserted low, + clears all DAC data registers without affecting configuration settin= gs. + + interrupts: + maxItems: 1 + description: + Interrupt connected to the ALARM pin. Active low interrupt output + for overtemperature conditions, SPI CRC errors, and function complet= ion. + + tg0-gpios: + maxItems: 1 + description: + GPIO connected to the TG0 toggle pin. Pulsing this pin allows all + selected DACs to be updated synchronously for coordinated output cha= nges. + + tg1-gpios: + maxItems: 1 + description: + GPIO connected to the TG1 toggle pin. Pulsing this pin allows all + selected DACs to be updated synchronously for coordinated output cha= nges. + + tg2-gpios: + maxItems: 1 + description: + GPIO connected to the TG2 toggle pin. Pulsing this pin allows all + selected DACs to be updated synchronously for coordinated output cha= nges. + + tg3-gpios: + maxItems: 1 + description: + GPIO connected to the TG3 toggle pin. Pulsing this pin allows all + selected DACs to be updated synchronously for coordinated output cha= nges. + + io-channels: + maxItems: 1 + description: + ADC channel connected to the MUXOUT pin for monitoring output voltag= e, + load current sense, and die temperature. + + io-channel-names: + const: muxout + + vdd-supply: + description: Digital power supply (1.08V to 1.98V) + + avdd-supply: + description: Analog power supply (4.75V to 5.25V) + + hvdd-supply: + description: + High voltage positive supply (7V to 45V). Supply voltage should be c= hosen + based on configured output ranges (see datasheet Table 9). + + hvss-supply: + description: + High voltage negative supply (-22.5V to 0V). Required only when usin= g bipolar + output ranges (=C2=B15V, =C2=B110V, =C2=B115V, =C2=B120V). Supply vo= ltage should be + chosen based on configured output ranges (see datasheet Table 9). + + vref-supply: + description: + External voltage reference supply (4.056V to 4.136V, typically 4.096= V). + When specified, the device uses external reference mode and the VREF= pin becomes an + input. The device uses the internal 4.096V precision reference other= wise. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^channel@([0-9]|1[0-5])$": + type: object + description: Child nodes for individual channel configuration + + properties: + reg: + description: Channel number. + minimum: 0 + maximum: 15 + + adi,output-range-microvolt: + description: | + Output voltage range for this channel as [min, max] in microvolt= s. + If not specified, defaults to 0V to 5V range. + oneOf: + - items: + - const: 0 + - enum: [5000000, 10000000, 20000000, 40000000] + - items: + - const: -5000000 + - const: 5000000 + - items: + - const: -10000000 + - const: 10000000 + - items: + - const: -15000000 + - const: 15000000 + - items: + - const: -20000000 + - const: 20000000 + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - vdd-supply + - avdd-supply + - hvdd-supply + +dependencies: + spi-cpha: [ spi-cpol ] + spi-cpol: [ spi-cpha ] + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + dac@0 { + compatible =3D "adi,ad5529r-16"; + reg =3D <0>; + spi-max-frequency =3D <25000000>; + + vdd-supply =3D <&vdd_regulator>; + avdd-supply =3D <&avdd_regulator>; + hvdd-supply =3D <&hvdd_regulator>; + hvss-supply =3D <&hvss_regulator>; + + reset-gpios =3D <&gpio0 87 GPIO_ACTIVE_LOW>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + channel@0 { + reg =3D <0>; + adi,output-range-microvolt =3D <0 5000000>; + }; + + channel@1 { + reg =3D <1>; + adi,output-range-microvolt =3D <(-10000000) 10000000>; + }; + + channel@2 { + reg =3D <2>; + adi,output-range-microvolt =3D <0 40000000>; + }; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index d6c3c7d22403..320e84765ce6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1507,6 +1507,13 @@ W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad4851.yaml F: drivers/iio/adc/ad4851.c =20 +ANALOG DEVICES INC AD5529R DRIVER +M: Janani Sunil +L: linux-iio@vger.kernel.org +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/dac/adi,ad5529r.yaml + ANALOG DEVICES INC AD5706R DRIVER M: Alexis Czezar Torreno L: linux-iio@vger.kernel.org --=20 2.43.0 From nobody Mon May 25 02:54:03 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B53133A9FE; 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Tue, 19 May 2026 11:43:34 -0400 From: Janani Sunil Date: Tue, 19 May 2026 17:42:59 +0200 Subject: [PATCH v3 2/2] iio: dac: Add AD5529R DAC driver support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260519-ad5529r-driver-v3-2-267c0731aa68@analog.com> References: <20260519-ad5529r-driver-v3-0-267c0731aa68@analog.com> In-Reply-To: <20260519-ad5529r-driver-v3-0-267c0731aa68@analog.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , "David Lechner" , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , "Jonathan Corbet" , Shuah Khan CC: , , , , Janani Sunil , Janani Sunil X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779205400; l=18839; i=janani.sunil@analog.com; s=20260507; h=from:subject:message-id; bh=bCdfVJd42btD4SEVg+Su1t7xd0jewWm2n2LYVtC++kk=; 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Supports both 12-bit and 16-bit + resolution variants. + + To compile this driver as a module, choose M here: the + module will be called ad5529r. + config AD5592R_BASE tristate =20 diff --git a/drivers/iio/dac/Makefile b/drivers/iio/dac/Makefile index 003431798498..f35e060b3643 100644 --- a/drivers/iio/dac/Makefile +++ b/drivers/iio/dac/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_AD5446) +=3D ad5446.o obj-$(CONFIG_AD5446_SPI) +=3D ad5446-spi.o obj-$(CONFIG_AD5446_I2C) +=3D ad5446-i2c.o obj-$(CONFIG_AD5449) +=3D ad5449.o +obj-$(CONFIG_AD5529R) +=3D ad5529r.o obj-$(CONFIG_AD5592R_BASE) +=3D ad5592r-base.o obj-$(CONFIG_AD5592R) +=3D ad5592r.o obj-$(CONFIG_AD5593R) +=3D ad5593r.o diff --git a/drivers/iio/dac/ad5529r.c b/drivers/iio/dac/ad5529r.c new file mode 100644 index 000000000000..9bb63030db95 --- /dev/null +++ b/drivers/iio/dac/ad5529r.c @@ -0,0 +1,527 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * AD5529R Digital-to-Analog Converter Driver + * 16-Channel, 12/16-Bit, 40V High Voltage Precision DAC + * + * Copyright 2026 Analog Devices Inc. + * Author: Janani Sunil + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AD5529R_REG_INTERFACE_CONFIG_A 0x00 +#define AD5529R_REG_DEVICE_CONFIG 0x02 +#define AD5529R_REG_CHIP_GRADE 0x06 +#define AD5529R_REG_SCRATCH_PAD 0x0A +#define AD5529R_REG_SPI_REVISION 0x0B +#define AD5529R_REG_VENDOR_H 0x0D +#define AD5529R_REG_STREAM_MODE 0x0E +#define AD5529R_REG_INTERFACE_STATUS_A 0x11 +#define AD5529R_REG_MULTI_DAC_CH_SEL 0x14 +#define AD5529R_REG_OUT_RANGE_BASE 0x3C +#define AD5529R_REG_OUT_RANGE(ch) (AD5529R_REG_OUT_RANGE_BASE + (ch) * 2) +#define AD5529R_REG_DAC_INPUT_A_BASE 0x148 +#define AD5529R_REG_DAC_INPUT_A(ch) (AD5529R_REG_DAC_INPUT_A_BASE + (ch) = * 2) +#define AD5529R_REG_DAC_DATA_READBACK_BASE 0x16A +#define AD5529R_REG_TSENS_ALERT_FLAG 0x18C +#define AD5529R_REG_TSENS_SHTD_FLAG 0x18E +#define AD5529R_REG_FUNC_BUSY 0x1A0 +#define AD5529R_REG_REF_SEL 0x1A2 +#define AD5529R_REG_INIT_CRC_ERR_STAT 0x1A4 +#define AD5529R_REG_MULTI_DAC_HOTPATH_SW_LDAC 0x1A8 + +#define AD5529R_INTERFACE_CONFIG_A_SW_RESET (BIT(7) | BIT(0)) +#define AD5529R_INTERFACE_CONFIG_A_ADDR_ASCENSION BIT(5) +#define AD5529R_INTERFACE_CONFIG_A_SDO_ENABLE BIT(4) +#define AD5529R_REF_SEL_MASK BIT(0) +#define AD5529R_MAX_REGISTER 0x232 +#define AD5529R_8BIT_REG_MAX 0x13 +#define AD5529R_SPI_READ_FLAG 0x80 + +struct ad5529r_model_data { + const char *model_name; + unsigned int resolution; + const struct iio_chan_spec *channels; + unsigned int num_channels; +}; + +#define AD5529R_DAC_CHANNEL(chan, bits) { \ + .type =3D IIO_VOLTAGE, \ + .indexed =3D 1, \ + .output =3D 1, \ + .channel =3D (chan), \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_OFFSET), \ + .scan_type =3D { \ + .format =3D 'u', \ + .realbits =3D (bits), \ + .storagebits =3D 16, \ + }, \ +} + +static const char * const ad5529r_supply_names[] =3D { + "vdd", + "avdd", + "hvdd", +}; + +static const struct iio_chan_spec ad5529r_channels_16bit[] =3D { + AD5529R_DAC_CHANNEL(0, 16), + AD5529R_DAC_CHANNEL(1, 16), + AD5529R_DAC_CHANNEL(2, 16), + AD5529R_DAC_CHANNEL(3, 16), + AD5529R_DAC_CHANNEL(4, 16), + AD5529R_DAC_CHANNEL(5, 16), + AD5529R_DAC_CHANNEL(6, 16), + AD5529R_DAC_CHANNEL(7, 16), + AD5529R_DAC_CHANNEL(8, 16), + AD5529R_DAC_CHANNEL(9, 16), + AD5529R_DAC_CHANNEL(10, 16), + AD5529R_DAC_CHANNEL(11, 16), + AD5529R_DAC_CHANNEL(12, 16), + AD5529R_DAC_CHANNEL(13, 16), + AD5529R_DAC_CHANNEL(14, 16), + AD5529R_DAC_CHANNEL(15, 16), +}; + +static const struct iio_chan_spec ad5529r_channels_12bit[] =3D { + AD5529R_DAC_CHANNEL(0, 12), + AD5529R_DAC_CHANNEL(1, 12), + AD5529R_DAC_CHANNEL(2, 12), + AD5529R_DAC_CHANNEL(3, 12), + AD5529R_DAC_CHANNEL(4, 12), + AD5529R_DAC_CHANNEL(5, 12), + AD5529R_DAC_CHANNEL(6, 12), + AD5529R_DAC_CHANNEL(7, 12), + AD5529R_DAC_CHANNEL(8, 12), + AD5529R_DAC_CHANNEL(9, 12), + AD5529R_DAC_CHANNEL(10, 12), + AD5529R_DAC_CHANNEL(11, 12), + AD5529R_DAC_CHANNEL(12, 12), + AD5529R_DAC_CHANNEL(13, 12), + AD5529R_DAC_CHANNEL(14, 12), + AD5529R_DAC_CHANNEL(15, 12), +}; + +static const struct ad5529r_model_data ad5529r_16bit_model_data =3D { + .model_name =3D "ad5529r-16", + .resolution =3D 16, + .channels =3D ad5529r_channels_16bit, + .num_channels =3D ARRAY_SIZE(ad5529r_channels_16bit), +}; + +static const struct ad5529r_model_data ad5529r_12bit_model_data =3D { + .model_name =3D "ad5529r-12", + .resolution =3D 12, + .channels =3D ad5529r_channels_12bit, + .num_channels =3D ARRAY_SIZE(ad5529r_channels_12bit), +}; + +enum ad5529r_output_range { + AD5529R_RANGE_0V_5V, + AD5529R_RANGE_0V_10V, + AD5529R_RANGE_0V_20V, + AD5529R_RANGE_0V_40V, + AD5529R_RANGE_NEG5V_5V, + AD5529R_RANGE_NEG10V_10V, + AD5529R_RANGE_NEG15V_15V, + AD5529R_RANGE_NEG20V_20V, +}; + +static const s32 ad5529r_output_ranges_mv[8][2] =3D { + [AD5529R_RANGE_0V_5V] =3D { 0, 5000 }, + [AD5529R_RANGE_0V_10V] =3D { 0, 10000 }, + [AD5529R_RANGE_0V_20V] =3D { 0, 20000 }, + [AD5529R_RANGE_0V_40V] =3D { 0, 40000 }, + [AD5529R_RANGE_NEG5V_5V] =3D { -5000, 5000 }, + [AD5529R_RANGE_NEG10V_10V] =3D { -10000, 10000 }, + [AD5529R_RANGE_NEG15V_15V] =3D { -15000, 15000 }, + [AD5529R_RANGE_NEG20V_20V] =3D { -20000, 20000 }, +}; + +struct ad5529r_state { + struct spi_device *spi; + const struct ad5529r_model_data *model_data; + struct regmap *regmap_8bit; + struct regmap *regmap_16bit; + struct regulator *vref_regulator; + enum ad5529r_output_range output_range_idx[16]; +}; + +static const struct regmap_range ad5529r_8bit_readable_ranges[] =3D { + regmap_reg_range(AD5529R_REG_INTERFACE_CONFIG_A, AD5529R_REG_CHIP_GRADE), + regmap_reg_range(AD5529R_REG_SCRATCH_PAD, AD5529R_REG_VENDOR_H), + regmap_reg_range(AD5529R_REG_STREAM_MODE, AD5529R_REG_INTERFACE_STATUS_A), +}; + +static const struct regmap_range ad5529r_16bit_readable_ranges[] =3D { + regmap_reg_range(AD5529R_REG_MULTI_DAC_CH_SEL, AD5529R_REG_INIT_CRC_ERR_S= TAT), + regmap_reg_range(AD5529R_REG_MULTI_DAC_HOTPATH_SW_LDAC, AD5529R_MAX_REGIS= TER), +}; + +static const struct regmap_access_table ad5529r_8bit_readable_table =3D { + .yes_ranges =3D ad5529r_8bit_readable_ranges, + .n_yes_ranges =3D ARRAY_SIZE(ad5529r_8bit_readable_ranges), +}; + +static const struct regmap_access_table ad5529r_16bit_readable_table =3D { + .yes_ranges =3D ad5529r_16bit_readable_ranges, + .n_yes_ranges =3D ARRAY_SIZE(ad5529r_16bit_readable_ranges), +}; + +static const struct regmap_range ad5529r_8bit_read_only_ranges[] =3D { + regmap_reg_range(AD5529R_REG_DEVICE_CONFIG, AD5529R_REG_CHIP_GRADE), + regmap_reg_range(AD5529R_REG_SPI_REVISION, AD5529R_REG_VENDOR_H), +}; + +static const struct regmap_range ad5529r_16bit_read_only_ranges[] =3D { + regmap_reg_range(AD5529R_REG_DAC_DATA_READBACK_BASE, + (AD5529R_REG_DAC_DATA_READBACK_BASE + 15 * 2)), + regmap_reg_range(AD5529R_REG_TSENS_ALERT_FLAG, AD5529R_REG_TSENS_SHTD_FLA= G), + regmap_reg_range(AD5529R_REG_FUNC_BUSY, AD5529R_REG_FUNC_BUSY), + regmap_reg_range(AD5529R_REG_INIT_CRC_ERR_STAT, AD5529R_REG_INIT_CRC_ERR_= STAT), +}; + +static const struct regmap_access_table ad5529r_8bit_writeable_table =3D { + .no_ranges =3D ad5529r_8bit_read_only_ranges, + .n_no_ranges =3D ARRAY_SIZE(ad5529r_8bit_read_only_ranges), +}; + +static const struct regmap_access_table ad5529r_16bit_writeable_table =3D { + .no_ranges =3D ad5529r_16bit_read_only_ranges, + .n_no_ranges =3D ARRAY_SIZE(ad5529r_16bit_read_only_ranges), +}; + +static const struct regmap_config ad5529r_regmap_8bit_config =3D { + .name =3D "ad5529r-8bit", + .reg_bits =3D 16, + .val_bits =3D 8, + .max_register =3D AD5529R_8BIT_REG_MAX, + .read_flag_mask =3D AD5529R_SPI_READ_FLAG, + .rd_table =3D &ad5529r_8bit_readable_table, + .wr_table =3D &ad5529r_8bit_writeable_table, +}; + +static const struct regmap_config ad5529r_regmap_16bit_config =3D { + .name =3D "ad5529r-16bit", + .reg_bits =3D 16, + .val_bits =3D 16, + .max_register =3D AD5529R_MAX_REGISTER, + .read_flag_mask =3D AD5529R_SPI_READ_FLAG, + .val_format_endian =3D REGMAP_ENDIAN_LITTLE, + .rd_table =3D &ad5529r_16bit_readable_table, + .wr_table =3D &ad5529r_16bit_writeable_table, + .reg_stride =3D 2, +}; + +static struct regmap *ad5529r_get_regmap(struct ad5529r_state *st, + unsigned int reg) +{ + if (reg <=3D AD5529R_8BIT_REG_MAX) + return st->regmap_8bit; + + return st->regmap_16bit; +} + +static int ad5529r_reset(struct ad5529r_state *st) +{ + struct reset_control *rst; + int ret; + + rst =3D devm_reset_control_get_optional_exclusive(&st->spi->dev, NULL); + if (IS_ERR(rst)) + return PTR_ERR(rst); + + if (rst) { + ret =3D reset_control_deassert(rst); + if (ret) + return ret; + } else { + ret =3D regmap_write(st->regmap_8bit, AD5529R_REG_INTERFACE_CONFIG_A, + AD5529R_INTERFACE_CONFIG_A_SW_RESET); + if (ret) + return ret; + } + + fsleep(10000); + + return regmap_write(st->regmap_8bit, AD5529R_REG_INTERFACE_CONFIG_A, + AD5529R_INTERFACE_CONFIG_A_SDO_ENABLE | + AD5529R_INTERFACE_CONFIG_A_ADDR_ASCENSION); +} + +static int ad5529r_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct ad5529r_state *st =3D iio_priv(indio_dev); + unsigned int reg_addr, reg_val_h; + int ret, range_idx, span_mv; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + reg_addr =3D AD5529R_REG_DAC_INPUT_A(chan->channel); + ret =3D regmap_read(st->regmap_16bit, reg_addr, ®_val_h); + if (ret) + return ret; + + *val =3D reg_val_h; + + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + range_idx =3D st->output_range_idx[chan->channel]; + + span_mv =3D ad5529r_output_ranges_mv[range_idx][1] - + ad5529r_output_ranges_mv[range_idx][0]; + *val =3D span_mv; + *val2 =3D st->model_data->resolution; + + return IIO_VAL_FRACTIONAL_LOG2; + case IIO_CHAN_INFO_OFFSET: + range_idx =3D st->output_range_idx[chan->channel]; + + if (ad5529r_output_ranges_mv[range_idx][0] < 0) + *val =3D -(1 << (st->model_data->resolution - 1)); + else + *val =3D 0; + + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int ad5529r_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + struct ad5529r_state *st =3D iio_priv(indio_dev); + unsigned int reg_addr; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + if (val < 0 || val > GENMASK(st->model_data->resolution - 1, 0)) + return -EINVAL; + + reg_addr =3D AD5529R_REG_DAC_INPUT_A(chan->channel); + + return regmap_write(st->regmap_16bit, reg_addr, val); + default: + return -EINVAL; + } +} + +static int ad5529r_find_output_range(const s32 *vals) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(ad5529r_output_ranges_mv); i++) { + if (vals[0] =3D=3D ad5529r_output_ranges_mv[i][0] * 1000 && + vals[1] =3D=3D ad5529r_output_ranges_mv[i][1] * 1000) + return i; + } + + return -EINVAL; +} + +static int ad5529r_parse_channel_ranges(struct device *dev, + struct ad5529r_state *st) +{ + int ret, ch, range_idx; + s32 vals[2]; + + device_for_each_child_node_scoped(dev, child) { + range_idx =3D AD5529R_RANGE_0V_5V; + + ret =3D fwnode_property_read_u32(child, "reg", &ch); + if (ret) + return dev_err_probe(dev, ret, + "Missing reg property in channel node\n"); + + if (ch >=3D 16) + return dev_err_probe(dev, -EINVAL, + "Invalid channel number: %d\n", ch); + + if (!fwnode_property_read_u32_array(child, + "adi,output-range-microvolt", + vals, 2)) { + range_idx =3D ad5529r_find_output_range(vals); + if (range_idx < 0) + return dev_err_probe(dev, range_idx, + "Invalid range [%d %d] for ch %d\n", + vals[0], vals[1], ch); + } + + st->output_range_idx[ch] =3D range_idx; + ret =3D regmap_write(st->regmap_16bit, + AD5529R_REG_OUT_RANGE(ch), range_idx); + if (ret) + return dev_err_probe(dev, ret, + "Failed to configure range for ch %d\n", + ch); + } + + return 0; +} + +static int ad5529r_debugfs_reg_read(struct ad5529r_state *st, unsigned int= reg, + unsigned int *val) +{ + return regmap_read(ad5529r_get_regmap(st, reg), reg, val); +} + +static int ad5529r_debugfs_reg_write(struct ad5529r_state *st, unsigned in= t reg, + unsigned int val) +{ + return regmap_write(ad5529r_get_regmap(st, reg), reg, val); +} + +static int ad5529r_reg_access(struct iio_dev *indio_dev, + unsigned int reg, + unsigned int writeval, + unsigned int *readval) +{ + struct ad5529r_state *st =3D iio_priv(indio_dev); + + if (readval) + return ad5529r_debugfs_reg_read(st, reg, readval); + + return ad5529r_debugfs_reg_write(st, reg, writeval); +} + +static void ad5529r_disable_regulator(void *regulator) +{ + regulator_disable(regulator); +} + +static const struct iio_info ad5529r_info =3D { + .read_raw =3D ad5529r_read_raw, + .write_raw =3D ad5529r_write_raw, + .debugfs_reg_access =3D ad5529r_reg_access, +}; + +static int ad5529r_probe(struct spi_device *spi) +{ + struct device *dev =3D &spi->dev; + struct iio_dev *indio_dev; + struct ad5529r_state *st; + int ret; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + + st->spi =3D spi; + + st->model_data =3D spi_get_device_match_data(spi); + if (!st->model_data) + return dev_err_probe(dev, -EINVAL, "Failed to identify device variant\n"= ); + + ret =3D devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ad5529r_supply_nam= es), + ad5529r_supply_names); + if (ret) + return dev_err_probe(dev, ret, + "Failed to get and enable regulators\n"); + + ret =3D devm_regulator_get_enable_optional(dev, "hvss"); + if (ret) + return dev_err_probe(dev, ret, + "Failed to get and enable hvss regulator\n"); + + st->vref_regulator =3D devm_regulator_get_optional(dev, "vref"); + if (IS_ERR(st->vref_regulator)) { + if (PTR_ERR(st->vref_regulator) !=3D -ENODEV) + return dev_err_probe(dev, PTR_ERR(st->vref_regulator), + "Failed to get vref regulator\n"); + st->vref_regulator =3D NULL; + } + + if (st->vref_regulator) { + ret =3D regulator_enable(st->vref_regulator); + if (ret) + return dev_err_probe(dev, ret, + "Failed to enable vref regulator\n"); + + ret =3D devm_add_action_or_reset(dev, ad5529r_disable_regulator, + st->vref_regulator); + if (ret) + return dev_err_probe(dev, ret, + "Failed to add vref regulator cleanup\n"); + } + + st->regmap_8bit =3D devm_regmap_init_spi(spi, &ad5529r_regmap_8bit_config= ); + if (IS_ERR(st->regmap_8bit)) + return dev_err_probe(dev, PTR_ERR(st->regmap_8bit), + "Failed to initialize 8-bit regmap\n"); + + st->regmap_16bit =3D devm_regmap_init_spi(spi, &ad5529r_regmap_16bit_conf= ig); + if (IS_ERR(st->regmap_16bit)) + return dev_err_probe(dev, PTR_ERR(st->regmap_16bit), + "Failed to initialize 16-bit regmap\n"); + + ret =3D ad5529r_reset(st); + if (ret) + return dev_err_probe(dev, ret, "Failed to reset device\n"); + + ret =3D regmap_update_bits(st->regmap_16bit, AD5529R_REG_REF_SEL, + AD5529R_REF_SEL_MASK, + st->vref_regulator ? 0 : AD5529R_REF_SEL_MASK); + if (ret) + return dev_err_probe(dev, ret, "Failed to configure reference\n"); + + ret =3D ad5529r_parse_channel_ranges(dev, st); + if (ret) + return ret; + + indio_dev->name =3D st->model_data->model_name; + indio_dev->info =3D &ad5529r_info; + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->channels =3D st->model_data->channels; + indio_dev->num_channels =3D st->model_data->num_channels; + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct of_device_id ad5529r_of_match[] =3D { + { .compatible =3D "adi,ad5529r-16", .data =3D &ad5529r_16bit_model_data }, + { .compatible =3D "adi,ad5529r-12", .data =3D &ad5529r_12bit_model_data }, + { } +}; +MODULE_DEVICE_TABLE(of, ad5529r_of_match); + +static const struct spi_device_id ad5529r_id[] =3D { + { "ad5529r-16", .driver_data =3D (kernel_ulong_t)&ad5529r_16bit_model_dat= a }, + { "ad5529r-12", .driver_data =3D (kernel_ulong_t)&ad5529r_12bit_model_dat= a }, + { } +}; +MODULE_DEVICE_TABLE(spi, ad5529r_id); + +static struct spi_driver ad5529r_driver =3D { + .driver =3D { + .name =3D "ad5529r", + .of_match_table =3D ad5529r_of_match, + }, + .probe =3D ad5529r_probe, + .id_table =3D ad5529r_id, +}; +module_spi_driver(ad5529r_driver); + +MODULE_AUTHOR("Janani Sunil "); +MODULE_DESCRIPTION("Analog Devices AD5529R 12/16-bit DAC driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0