From nobody Mon May 25 04:34:30 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 962A03A9001 for ; Mon, 18 May 2026 22:21:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779142871; cv=none; b=SiLKnSpNLhUnw779jsLueZKkqn4HJ/GBYJVZC3Fjjrud8C0PEQ6m2jNdR7irzWIB7MKRT1EOmqa6u80FWAhulsHkZDJcAOBiHE6t0e01+hjL52n+K9eyuPpX01KkolraKJK/X8cRLEuRPlB4hPQ7brKk8av0pKBpza6dP8Y4HSI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779142871; c=relaxed/simple; bh=RI5M292dnns+QA/N4s9MWozsKnc5cghUbjZ1Ts5Njm0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PzpyhRFdKmrA3VTHqgo05YPlupAZFejO1N1hsUI8Nz8wpxS4SEmrUqybxgJ4kty/PMrgjfQpAQcWgYt3RX5LtctDyzu5TXkVgMrapxaPXnnMKnhAo3TOusvZfUe9cdbfLeQx0AnQptS9WziFtC4EAjujoY8fIozr4ClIOifDdJ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=l+ni/C4o; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="l+ni/C4o" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779142867; x=1810678867; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RI5M292dnns+QA/N4s9MWozsKnc5cghUbjZ1Ts5Njm0=; b=l+ni/C4oidtLIGpqMlYlC5v8u3xtB4+MEPsuFm+175F8izP45EwTy2Un WtV33X0Y060YrpbV0vTJWay7wUfhos1vNVRqGw0TSc8hy+8bVN3KH/ziV YBu8z5wBHjrdVzSYEfoGbFCoZ6S4hqb/XQBQVYbBniO47+NYwaPBlvNrM 8GFtRq1ThkMK6xH/C3YAvWeaY2GvAKiw9x/73hhwXsBWwNo5B/hYaC92I rU8tCU6IHKoOBcyXJYpX4AQRYRSd1HrPW56gTlfUqitH8kx/K8qAGe5nu q+RwvEEcsAf/nSeE7LMyNFL6qC31j4qXh0oHzZasR2i0tuLXT7dC9uEt0 A==; X-CSE-ConnectionGUID: a//rQPKHTyeMZa5sLCqGhA== X-CSE-MsgGUID: U9jA6M5sRCmDU1bCuRy/Cg== X-IronPort-AV: E=McAfee;i="6800,10657,11790"; a="90317857" X-IronPort-AV: E=Sophos;i="6.23,242,1770624000"; d="scan'208";a="90317857" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2026 15:21:06 -0700 X-CSE-ConnectionGUID: oNv3ONqtTFOtbpmsdDR+vg== X-CSE-MsgGUID: 81HB9Y0/QryBmVea3S6NPQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,242,1770624000"; d="scan'208";a="244564547" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by orviesa005.jf.intel.com with ESMTP; 18 May 2026 15:21:06 -0700 From: Sohil Mehta To: Dave Hansen , Borislav Petkov , x86@kernel.org Cc: Thomas Gleixner , Ingo Molnar , "H . Peter Anvin" , Josh Poimboeuf , Richard Weinberger , Andrew Cooper , Tony Luck , Sohil Mehta , "Ahmed S . Darwish" , linux-kernel@vger.kernel.org Subject: [PATCH v3 1/3] x86/cpu/intel: Don't clear X86_BUG_F00F before setting it Date: Mon, 18 May 2026 15:17:16 -0700 Message-ID: <20260518221718.3303288-2-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260518221718.3303288-1-sohil.mehta@intel.com> References: <20260518221718.3303288-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Richard Weinberger On x86 SMP systems with the F00F bug present, the following warning occurs for each AP: WARNING: arch/x86/kernel/cpu/cpuid-deps.c:126 at do_clear_cpu_cap+0xb4/0x= 110 Call Trace: clear_cpu_cap+0x8/0x10 init_intel+0x1b/0x4b0 identify_cpu+0x154/0x750 identify_secondary_cpu+0x3d/0x90 start_secondary+0x6b/0xf0 startup_32_smp+0x151/0x160 The X86_BUG_F00F flag is first cleared in intel_workarounds() and then set for the affected models. This sequence works fine on the BSP but on AP bringup, where alternatives have already been patched, clearing the flag triggers the warning. There is no technical reason for clearing the flag before setting it. It is mainly an artifact of the introduction of X86_BUG_F00F in commit e2604b49e8a8 ("x86, cpu: Convert F00F bug detection"). Remove the unnecessary clearing of the flag. Note that the fixes tag references a recent commit that introduced the warning rather than the old commit that converted F00F bug detection to use clear_cpu_bug(). Fixes: ee8962082a44 ("x86/alternatives: Catch late X86_FEATURE modifiers") Signed-off-by: Richard Weinberger [sohil: reworded the commit message] Signed-off-by: Sohil Mehta Reviewed-by: Ahmed S. Darwish --- v3: - Picked up Ahmed's review tag. v2: - Reworded commit message to clarify the issue. --- arch/x86/kernel/cpu/intel.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index f28c0efb7c8f..e957c5a1501c 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -395,7 +395,6 @@ static void intel_workarounds(struct cpuinfo_x86 *c) * system. Announce that the fault handler will be checking for it. * The Quark is also family 5, but does not have the same bug. */ - clear_cpu_bug(c, X86_BUG_F00F); if (c->x86_vfm >=3D INTEL_FAM5_START && c->x86_vfm < INTEL_QUARK_X1000) { static int f00f_workaround_enabled; =20 --=20 2.43.0 From nobody Mon May 25 04:34:30 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0E2B3AB283 for ; Mon, 18 May 2026 22:21:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779142870; cv=none; b=AOrPh/zr18F3mCIaamVy2GUxDSrQJiHzu9oFmGAuwW6UiIK1DteQlt+zDBpY74t2oBCJLVwmv35VOJ7cZeR1evrsxu57QdMxLq1pr4w6K776yu5V0F6xz/T2pt6hSTwxW5S3TV61LMcJQFDVvEeYM5eN7kQHmLZu4j22pa/f73A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779142870; c=relaxed/simple; bh=D1ZgGQjfRdsiaJd2opOYWb72S7Ib6zYLfiyUZijWnFQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=e+c9wwRO50aSSesL9hrNnUQNYOT8rOm9oOKUit76Y3z4Nv8/7a/jncOLdkqH/PyPH3YarHZm2JWWyU0sG4rDc+heCL13PYYz8A9UzWTHDrGAV17nwRpRV8qOJ9Xeq2jxj9XsFmcqcAGRqJfWK6TjLuHbxqf7iZz5M8Dc0fjATwc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YLKb0tEw; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YLKb0tEw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779142869; x=1810678869; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=D1ZgGQjfRdsiaJd2opOYWb72S7Ib6zYLfiyUZijWnFQ=; b=YLKb0tEwP+X8EyngFXhyhS9OSwHizITQDfgUvUM9p3WsjuaeAC3UqjH4 f45W9LSwaFazV9qd4tF+YQDL+317j/IKaDwTOuaGmwgwi7qSDa9Mqb+M0 zetvnz2t5oxaD9Zn5Tq9iiDKUYfSWGYxzNxks4dZQV5ok696I/OwjmqFq zkQK8A7gEvbB7hOnrqp7N1QJMLhKKbdtEhJYnQGMrR4xV+MHhfrM3UtO9 cd4ZeBzMoYcS7wfc+ORz5bh/wjqVm8+2aTYhOIIdtNgzA/h3/OhD1kkn4 Ad6GWcN6sPSMu32ysNo5QXFwA4CjLBgNl7rkl9qw3R/N5wnuHzoM64QoL A==; X-CSE-ConnectionGUID: EvZWWKHeTiaYKw00owUi9A== X-CSE-MsgGUID: YB8LuXfYRoCq8pwj9Rtbwg== X-IronPort-AV: E=McAfee;i="6800,10657,11790"; a="90317865" X-IronPort-AV: E=Sophos;i="6.23,242,1770624000"; d="scan'208";a="90317865" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2026 15:21:06 -0700 X-CSE-ConnectionGUID: xwnwQz7xT/uSvBARSnanpQ== X-CSE-MsgGUID: MA3esNiMR9ajXvvTubmeXg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,242,1770624000"; d="scan'208";a="244564550" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by orviesa005.jf.intel.com with ESMTP; 18 May 2026 15:21:06 -0700 From: Sohil Mehta To: Dave Hansen , Borislav Petkov , x86@kernel.org Cc: Thomas Gleixner , Ingo Molnar , "H . Peter Anvin" , Josh Poimboeuf , Richard Weinberger , Andrew Cooper , Tony Luck , Sohil Mehta , "Ahmed S . Darwish" , linux-kernel@vger.kernel.org Subject: [PATCH v3 2/3] x86/cpu/intel: Remove the F00F bug workaround notice Date: Mon, 18 May 2026 15:17:17 -0700 Message-ID: <20260518221718.3303288-3-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260518221718.3303288-1-sohil.mehta@intel.com> References: <20260518221718.3303288-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The F00F bug workaround announcement goes through a lot of effort to print the kernel notice exactly once. CPU bugs with workarounds typically don't require user notifications. If needed, the presence of the F00F bug can be determined through /proc/cpuinfo. Remove the notice and the surrounding logic to print it once. Signed-off-by: Sohil Mehta Reviewed-by: Ahmed S. Darwish --- v3: - Get rid of the notice instead of simplifying it. (Ahmed) v2: - New patch --- arch/x86/kernel/cpu/intel.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index e957c5a1501c..329ab1a90f5e 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -388,23 +388,15 @@ __setup("forcepae", forcepae_setup); =20 static void intel_workarounds(struct cpuinfo_x86 *c) { -#ifdef CONFIG_X86_F00F_BUG /* * All models of Pentium and Pentium with MMX technology CPUs * have the F0 0F bug, which lets nonprivileged users lock up the - * system. Announce that the fault handler will be checking for it. + * system. The fault handler always checks for it. * The Quark is also family 5, but does not have the same bug. */ - if (c->x86_vfm >=3D INTEL_FAM5_START && c->x86_vfm < INTEL_QUARK_X1000) { - static int f00f_workaround_enabled; - + if ((IS_ENABLED(CONFIG_X86_F00F_BUG)) && + (c->x86_vfm >=3D INTEL_FAM5_START && c->x86_vfm < INTEL_QUARK_X1000)) set_cpu_bug(c, X86_BUG_F00F); - if (!f00f_workaround_enabled) { - pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n"); - f00f_workaround_enabled =3D 1; - } - } -#endif =20 /* * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until --=20 2.43.0 From nobody Mon May 25 04:34:30 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3238D3AB293 for ; Mon, 18 May 2026 22:21:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779142871; cv=none; b=qii6ibWBhoIJ1KMUuphcsAGaGIzNmalYcVO+FEXyx1+eRjHuY3M67LjJEFviEZ90KfgT4tqYJyxl6qhoKwhq1cOmvy9YjFj0ZvDPLZbUAXy709iELrrQRBK7J5j8A5SkDHm3KeutBHubGKZT32/NB8V9KxpquWW8Da7oXp4MPUs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779142871; c=relaxed/simple; bh=5vcQOwcI8UydaSanIHiEgv1spygCi6hpr4FipFcJtlM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iE0isY21q/AH872UdNWlKLXFcigsbUTr3ntAs2buo9hZnkNJG/2z5dwcCEtbm9yIfBRmDru8oimuVXcHasK9v400Xk8neraGUww4pfHwlWp8k6fDe68E1tUZfCveQO+wpc4ThG3AALsrBrenGNIzYlbhJwHjQsTEchd3d7+JhLQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ZrR2Hlq7; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ZrR2Hlq7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779142869; x=1810678869; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5vcQOwcI8UydaSanIHiEgv1spygCi6hpr4FipFcJtlM=; b=ZrR2Hlq78hz3thC/MgkLJ2mP4z8n8xqz9e9XOrSA6A2DInqQso+6esZ9 XaaLXhx+ATvtpzdASa6xw1XQq0EeXiHVeUIXzB1q7OQZKlitxvtkV0Jia DFEifodPfGxqxWBvTFFAqKwLOYNRXdAusKBt7IzeqbyR3y/bIO2HxlTJg O8iABNOuGeK+Woep/Oyb5OPPZI/GxIRD/0keUOpPbnZ+enPLkKvtgDEeo X+IK9WhFJcVRWmDCL9LdEvIumfcLc5VnD2t6a5iOLy1lqg4lpDea+UOpR LM2dUV1seNVOWotTpvqc1DyAb/sa05QgpAXMgE7Gwgu5RDP8uzso01qew g==; X-CSE-ConnectionGUID: UicIVfslT+OrLKPY2JEnDQ== X-CSE-MsgGUID: BMH8lF3DSIOgOlSZ7du6XQ== X-IronPort-AV: E=McAfee;i="6800,10657,11790"; a="90317873" X-IronPort-AV: E=Sophos;i="6.23,242,1770624000"; d="scan'208";a="90317873" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2026 15:21:07 -0700 X-CSE-ConnectionGUID: 4p/+LG72QTmtjwU3m5gm4Q== X-CSE-MsgGUID: G51MuBRPRxyVg4aJo1rOMw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,242,1770624000"; d="scan'208";a="244564553" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by orviesa005.jf.intel.com with ESMTP; 18 May 2026 15:21:06 -0700 From: Sohil Mehta To: Dave Hansen , Borislav Petkov , x86@kernel.org Cc: Thomas Gleixner , Ingo Molnar , "H . Peter Anvin" , Josh Poimboeuf , Richard Weinberger , Andrew Cooper , Tony Luck , Sohil Mehta , "Ahmed S . Darwish" , linux-kernel@vger.kernel.org Subject: [PATCH v3 3/3] x86/cpufeature: Remove clear_cpu_bug() Date: Mon, 18 May 2026 15:17:18 -0700 Message-ID: <20260518221718.3303288-4-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260518221718.3303288-1-sohil.mehta@intel.com> References: <20260518221718.3303288-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Richard Weinberger X86_BUG_F00F was the last remaining user of clear_cpu_bug(). With no users left, remove this helper. Signed-off-by: Richard Weinberger Signed-off-by: Sohil Mehta Reviewed-by: Ahmed S. Darwish --- v3: - Picked up Ahmed's review tag. v2: - Improve commit message --- arch/x86/include/asm/cpufeature.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufe= ature.h index 3ddc1d33399b..90680f978d43 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -125,7 +125,6 @@ static __always_inline bool _static_cpu_has(u16 bit) =20 #define cpu_has_bug(c, bit) cpu_has(c, (bit)) #define set_cpu_bug(c, bit) set_cpu_cap(c, (bit)) -#define clear_cpu_bug(c, bit) clear_cpu_cap(c, (bit)) =20 #define static_cpu_has_bug(bit) static_cpu_has((bit)) #define boot_cpu_has_bug(bit) cpu_has_bug(&boot_cpu_data, (bit)) --=20 2.43.0