From nobody Mon May 25 04:34:29 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A96E438F253; Mon, 18 May 2026 19:12:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779131555; cv=none; b=n4CJyGWtNpcJUHizxBMF2Dwb6TVuQ5Yj/JA4/GXGnWqyX7V9BvR3a1CsBWPO7HM+V4EFGrku4VDdLPOiAsX1SIQfs0IWW4ZCwVR1p2vyO/mczcJu+tdD5ailmuBgRaBlOlQvzetz3w8zPCDVfz1cHLyt7VHgO+TRKq7EanLwZLk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779131555; c=relaxed/simple; bh=qrUC0CR45vX2T8T3l6xZMm4+i/QGJtJXpk+nHDir1Ck=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XKD2BMLezDQi3WKG0pdL5usaxemFABV73Bw9SXYQgLrnL10T7xSlIAsMAm3mswSZouHKzJ2MzAfyIrouaA926tTso5mzb8nj+EHqrgjWihIViaMo/ZOpHyNsvxMqNnvd1K/Yqt00kxwatzqT0Qmdcat34jlBYF3roxj4Poz7Pdc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YI72NuF4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YI72NuF4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3C9CAC2BCC6; Mon, 18 May 2026 19:12:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779131555; bh=qrUC0CR45vX2T8T3l6xZMm4+i/QGJtJXpk+nHDir1Ck=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YI72NuF4o6Kv+z31uWnwShRerVfS3H1gPA5NxJTGJESKQqxNgt8xRiWc9rFowIQZ7 r+kgSFji+7aUr6Owc73XXHPh2LKCbXgEwaJAlOrnAO5kKEcSOVwpow/AojMy71mmXn jP27KesUFrmX+rc6w553ojn+chXTetaoknLF/tA+5guhxEMYK/aqDwgDovEYQHWIgD W6zbh01wW8tirSjCDtdAULKTgwpQ6oQsA82RXGxGj1pr4q3mtkJoQbFDWRx4D02Ksd mMz1Y5v8a6nfEW4Jt7ZTfAMiEuiVdoWXLF1VXNIs6h7sWO3UhOJOAqZ0niod9PZNp0 povHzSKROQJtg== From: Bjorn Helgaas To: linux-pci@vger.kernel.org Cc: "Rafael J . Wysocki" , Lukas Wunner , Marco Nenciarini , Michal Winiarski , Ilpo Jarvinen , Eric Chanudet , Jean Guyader , Alex Williamson , Sinan Kaya , Mario Limonciello , Mika Westerberg , linux-kernel@vger.kernel.org, Bjorn Helgaas Subject: [PATCH v2 1/2] PCI: Log device readiness timeouts as errors Date: Mon, 18 May 2026 14:12:18 -0500 Message-ID: <20260518191220.636213-2-bhelgaas@google.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260518191220.636213-1-bhelgaas@google.com> References: <20260518191220.636213-1-bhelgaas@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" pci_dev_wait() waits for a device to be Configuration-Ready after a reset, such as a Function-Level Reset (FLR), a soft reset during a D3hot-> D0uninitialized transition when No_Soft_Reset =3D=3D 0), or a power-up sequ= ence from D3cold->D0uninitialized. If pci_dev_wait() returns success, the device is guaranteed to respond to configuration requests with Successful Completion status. If it times out, device is completely non-responsive. Upgrade the log level from pci_warn() to pci_err() to reflect this failure state. Signed-off-by: Bjorn Helgaas Reviewed-by: Rafael J. Wysocki (Intel) --- drivers/pci/pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 8f7cfcc00090..5a9af0bb2c71 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1253,8 +1253,8 @@ static int pci_dev_wait(struct pci_dev *dev, char *re= set_type, int timeout) } =20 if (delay > timeout) { - pci_warn(dev, "not ready %dms after %s; giving up\n", - delay - 1, reset_type); + pci_err(dev, "not ready %dms after %s; giving up\n", + delay - 1, reset_type); return -ENOTTY; } =20 --=20 2.51.0 From nobody Mon May 25 04:34:29 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D436138F629; Mon, 18 May 2026 19:12:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779131560; cv=none; b=oM/Z9yLEpK5uC7xeIiaiaUriwS0vksA+rV62nLBw0jCQtAjp0GQIzsnb/grzuBw7cKg2IYMcRc661zrS9vsByjYja6i5zPhlYYNa2DBemwSDDDKU2p+JVeYun9IRf5bm13Wo2tThweMzvj/28igTxDdGaDTvhHtBNDFyDlVfKzQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779131560; c=relaxed/simple; bh=OVGv8aD9oXyZXd/JxYCzbnzBbcXTfxSshxXccMPVbbY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=knqChj7BmHZcvwlRX3yVLVzz99hoRzVftVtHJPu5Otk3sPCRiLN+0n/mTfWB77FgrH8lPJu0yzrJDPc9bLKfj8aw3nGGrC7smBf73wsr9x23oNfGuMcAlx8QLnnarwefrJHcJq6qDe8mps98Ryx4yPJq4s5MNyq61awn0h7jOrE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Txn5EHUf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Txn5EHUf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 55FDBC2BCB7; Mon, 18 May 2026 19:12:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779131560; bh=OVGv8aD9oXyZXd/JxYCzbnzBbcXTfxSshxXccMPVbbY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Txn5EHUfjGTcjZQHQhg1k0bOY2zDFe/gk8VFc1MhWr8MjUswp99fTOaHfz+SQSd7L TGMbCl/Fyru7jVgWu9sH63Yjn3Mst0E4vvKMqblmX8gwiM151DOfXZAhHyODsWpZIJ kRtNeAxJAYQEqs+UiyN3zbKhDoLz6RzPKy/5uRmTT7BOWbQe/zZn+vPMC91j4q43VE rAlSMrrBL7gl37TXiD8LkRN4894rCl7qXDMcE9Om8jY9NBVi18NxigW1NLi6cvotiO oNwFm/fu2keXpgTcvvJsELUjUKNuQ4EFk5ACnHKTArCbJz0FRl/EDmU7fojtmpcu7A yeYY+Ag+D1XXA== From: Bjorn Helgaas To: linux-pci@vger.kernel.org Cc: "Rafael J . Wysocki" , Lukas Wunner , Marco Nenciarini , Michal Winiarski , Ilpo Jarvinen , Eric Chanudet , Jean Guyader , Alex Williamson , Sinan Kaya , Mario Limonciello , Mika Westerberg , linux-kernel@vger.kernel.org, Bjorn Helgaas , Bjorn Helgaas Subject: [PATCH v2 2/2] PCI: Wait for device readiness after D3hot -> D0uninitialized transition Date: Mon, 18 May 2026 14:12:19 -0500 Message-ID: <20260518191220.636213-3-bhelgaas@google.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260518191220.636213-1-bhelgaas@google.com> References: <20260518191220.636213-1-bhelgaas@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Bjorn Helgaas For a device that advertises No_Soft_Reset =3D=3D 0, a transition from D3ho= t to D0uninitialized is a soft reset, and the resulting internal device state is undefined. Per PCIe r7.0, sec 2.3.1, a transition from D3hot to D0uninitialized mandates a minimum 10 ms delay before accessing the device. Following this delay, the device is permitted to respond to initial configuration requests with a Request Retry Status (RRS) completion status if it needs more time to initialize. Call pci_dev_wait() after pci_power_up() performs a D3hot->D0uninitialized transition to ensure the device is ready to accept config accesses, as is done after the similar transition in pci_pm_reset(). If the device is already ready, this is essentially a no-op except for one additional config read. Signed-off-by: Bjorn Helgaas Reviewed-by: Rafael J. Wysocki (Intel) --- drivers/pci/pci.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 5a9af0bb2c71..8228d2782f95 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1300,7 +1300,18 @@ int pci_power_up(struct pci_dev *dev) bool need_restore; pci_power_t state; u16 pmcsr; + int ret; =20 + /* + * When setting power state to D0, platform_pci_set_power_state() + * ensures main power is on. If it puts the device in D0, it also + * completes any required delays after the transition; if it leaves + * the device in D1, D2, or D3hot, we use the PM Capability to + * transition to D0. + * + * In all cases, the device is either Configuration-Ready or + * inaccessible upon return. + */ platform_pci_set_power_state(dev, PCI_D0); =20 if (!dev->pm_cap) { @@ -1341,10 +1352,19 @@ int pci_power_up(struct pci_dev *dev) pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, 0); =20 /* Mandatory transition delays; see PCI PM 1.2. */ - if (state =3D=3D PCI_D3hot) + if (state =3D=3D PCI_D3hot) { pci_dev_d3_sleep(dev); - else if (state =3D=3D PCI_D2) + if (!(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) { + ret =3D pci_dev_wait(dev, "power up D3hot->D0uninitialized", + PCIE_RESET_READY_POLL_MS); + if (ret) { + dev->current_state =3D PCI_D3cold; + return -EIO; + } + } + } else if (state =3D=3D PCI_D2) { udelay(PCI_PM_D2_DELAY); + } =20 end: dev->current_state =3D PCI_D0; --=20 2.51.0