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charset="utf-8" Add common virtual memory memory management types: `PAGE_SIZE` constant, `VirtualAddress` bitfield type, `Vfn` (Virtual Frame Number) type. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm.rs | 66 +++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/drivers/gpu/nova-core/mm.rs b/drivers/gpu/nova-core/mm.rs index 08d74710f790..b23667a55ecd 100644 --- a/drivers/gpu/nova-core/mm.rs +++ b/drivers/gpu/nova-core/mm.rs @@ -42,6 +42,7 @@ macro_rules! impl_pfn_bounded { num::Bounded, pci, prelude::*, + sizes::SZ_4K, sync::Arc, // }; =20 @@ -99,6 +100,9 @@ pub(crate) fn run_mm_selftests( Ok(()) } =20 +/// Page size in bytes (4 KiB). +pub(crate) const PAGE_SIZE: usize =3D SZ_4K; + bitfield! { /// Physical VRAM address in GPU video memory. pub(crate) struct VramAddress(u64) { @@ -207,6 +211,29 @@ fn into_vram_range(self) -> Range { } } =20 +bitfield! { + /// Virtual address in GPU address space. + pub(crate) struct VirtualAddress(u64) { + /// Offset within 4KB page. + 11:0 offset; + /// Virtual frame number. + 63:12 frame_number =3D> Vfn; + } +} + +impl VirtualAddress { + /// Create a new virtual address from a raw value. + pub(crate) const fn new(addr: u64) -> Self { + Self::from_raw(addr) + } +} + +impl From for VirtualAddress { + fn from(vfn: Vfn) -> Self { + Self::zeroed().with_frame_number(vfn) + } +} + /// Physical Frame Number. /// /// Represents a physical page in VRAM. @@ -245,3 +272,42 @@ fn from(pfn: Pfn) -> Self { } =20 impl_pfn_bounded!(52); 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Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by BY5PR12MB4276.namprd12.prod.outlook.com (2603:10b6:a03:20f::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.24; Mon, 18 May 2026 18:11:33 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%6]) with mapi id 15.21.0025.012; Mon, 18 May 2026 18:11:33 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Miguel Ojeda , Boqun Feng , Gary Guo , Bjorn Roy Baron , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Dave Airlie , Daniel Almeida , dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, nova-gpu@lists.linux.dev, Nikola Djukic , David Airlie , Boqun Feng , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Balbir Singh , Philipp Stanner , alexeyi@nvidia.com, Eliot Courtney , joel@joelfernandes.org, linux-doc@vger.kernel.org, Joel Fernandes Subject: [PATCH v1 02/16] gpu: nova-core: mm: Add buddy allocator and TLB to GpuMm Date: Mon, 18 May 2026 14:11:11 -0400 Message-Id: <20260518181126.2493572-3-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260518181126.2493572-1-joelagnelf@nvidia.com> References: <20260518181126.2493572-1-joelagnelf@nvidia.com> Content-Type: text/plain; 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PRAMIN was added in an earlier commit; this completes the centralized ownership model with accessor methods for each component. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/Kconfig | 1 + drivers/gpu/nova-core/gpu.rs | 22 ++++- drivers/gpu/nova-core/gsp/commands.rs | 1 - drivers/gpu/nova-core/mm.rs | 27 ++++++ drivers/gpu/nova-core/mm/tlb.rs | 130 ++++++++++++++++++++++++++ drivers/gpu/nova-core/regs.rs | 65 +++++++++++++ 6 files changed, 244 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/nova-core/mm/tlb.rs diff --git a/drivers/gpu/nova-core/Kconfig b/drivers/gpu/nova-core/Kconfig index abf10e82647b..8eebb430856a 100644 --- a/drivers/gpu/nova-core/Kconfig +++ b/drivers/gpu/nova-core/Kconfig @@ -5,6 +5,7 @@ config NOVA_CORE depends on RUST depends on !CPU_BIG_ENDIAN select AUXILIARY_BUS + select GPU_BUDDY select RUST_FW_LOADER_ABSTRACTIONS default n help diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index aa047fe91054..f789d956cc49 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -4,11 +4,16 @@ device, devres::Devres, fmt, + gpu::buddy::GpuBuddyParams, io::Io, num::Bounded, pci, prelude::*, - sizes::SizeConstants, + ptr::Alignment, + sizes::{ + SizeConstants, + SZ_4K, // + }, sync::Arc, // }; =20 @@ -305,6 +310,13 @@ pub(crate) fn new<'a>( gsp_static_info: gsp .boot(pdev, bar, spec.chipset, gsp_falcon, sec2_falcon) .inspect(|info| { + dev_info!( + pdev.as_ref(), + "Using FB region: {:#x}..{:#x}\n", + info.usable_fb_region.start, + info.usable_fb_region.end + ); + dev_info!( pdev.as_ref(), "Total physical VRAM: {} MiB\n", @@ -314,14 +326,22 @@ pub(crate) fn new<'a>( =20 // Create GPU memory manager owning memory management resource= s. mm: { + let usable_vram =3D &gsp_static_info.usable_fb_region; + // PRAMIN covers all physical VRAM (including GSP-reserved= areas // above the usable region, e.g. the BAR1 page directory). let pramin_vram_region =3D (0..gsp_static_info.total_fb_en= d).into_vram_range(); + let buddy_params =3D GpuBuddyParams { + base_offset: usable_vram.start, + size: usable_vram.end - usable_vram.start, + chunk_size: Alignment::new::(), + }; Arc::pin_init( GpuMm::new( devres_bar.clone(), pdev.as_ref(), spec.chipset, + buddy_params, pramin_vram_region, )?, GFP_KERNEL, diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/= gsp/commands.rs index 172411d7b475..5abd7950320b 100644 --- a/drivers/gpu/nova-core/gsp/commands.rs +++ b/drivers/gpu/nova-core/gsp/commands.rs @@ -194,7 +194,6 @@ fn init(&self) -> impl Init { pub(crate) struct GetGspStaticInfoReply { gpu_name: [u8; 64], /// Usable FB (VRAM) region for driver memory allocation. - #[expect(dead_code)] pub(crate) usable_fb_region: Range, /// End of VRAM. pub(crate) total_fb_end: u64, diff --git a/drivers/gpu/nova-core/mm.rs b/drivers/gpu/nova-core/mm.rs index b23667a55ecd..ea415a88b221 100644 --- a/drivers/gpu/nova-core/mm.rs +++ b/drivers/gpu/nova-core/mm.rs @@ -32,6 +32,7 @@ macro_rules! impl_pfn_bounded { } =20 pub(crate) mod pramin; +pub(super) mod tlb; =20 use core::ops::Range; =20 @@ -39,6 +40,10 @@ macro_rules! impl_pfn_bounded { bitfield, device, devres::Devres, + gpu::buddy::{ + GpuBuddy, + GpuBuddyParams, // + }, num::Bounded, pci, prelude::*, @@ -51,14 +56,21 @@ macro_rules! impl_pfn_bounded { gpu::Chipset, // }; =20 +pub(crate) use tlb::Tlb; + /// GPU Memory Manager - owns all core MM components. /// /// Provides centralized ownership of memory management resources: +/// - [`GpuBuddy`] allocator for VRAM page table allocation. /// - [`pramin::Pramin`] for direct VRAM access. +/// - [`Tlb`] manager for translation buffer flush operations. #[pin_data] pub(crate) struct GpuMm { + buddy: GpuBuddy, #[pin] pramin: pramin::Pramin, + #[pin] + tlb: Tlb, } =20 impl GpuMm { @@ -70,19 +82,34 @@ pub(crate) fn new( bar: Arc>, dev: &device::Device, chipset: Chipset, + buddy_params: GpuBuddyParams, pramin_vram_region: Range, ) -> Result> { + let buddy =3D GpuBuddy::new(buddy_params)?; + let tlb_init =3D Tlb::new(bar.clone()); let pramin_init =3D pramin::Pramin::new(bar, dev, chipset, pramin_= vram_region)?; =20 Ok(pin_init!(Self { + buddy, pramin <- pramin_init, + tlb <- tlb_init, })) } =20 + /// Access the [`GpuBuddy`] allocator. + pub(crate) fn buddy(&self) -> &GpuBuddy { + &self.buddy + } + /// Access the [`pramin::Pramin`]. pub(crate) fn pramin(&self) -> &pramin::Pramin { &self.pramin } + + /// Access the [`Tlb`] manager. + pub(crate) fn tlb(&self) -> &Tlb { + &self.tlb + } } =20 /// Run MM subsystem self-tests during probe. diff --git a/drivers/gpu/nova-core/mm/tlb.rs b/drivers/gpu/nova-core/mm/tlb= .rs new file mode 100644 index 000000000000..1c4f8944a01b --- /dev/null +++ b/drivers/gpu/nova-core/mm/tlb.rs @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! TLB (Translation Lookaside Buffer) flush support for GPU MMU. +//! +//! After modifying page table entries, the GPU's TLB must be flushed to +//! ensure the new mappings take effect. This module provides TLB flush +//! functionality for virtual memory managers. +//! +//! # Examples +//! +//! ```ignore +//! use crate::mm::tlb::Tlb; +//! +//! fn page_table_update( +//! dev: &device::Device, +//! tlb: &Tlb, +//! pdb_addr: VramAddress, +//! ) -> Result<()> { +//! // ... modify page tables ... +//! +//! // Flush TLB to make changes visible (polls for completion). +//! tlb.flush(dev, pdb_addr)?; +//! +//! Ok(()) +//! } +//! ``` + +use kernel::{ + device, + devres::Devres, + io::poll::read_poll_timeout, + io::Io, + new_mutex, + prelude::*, + sync::{ + Arc, + Mutex, // + }, + time::Delta, // +}; + +use crate::{ + bounded_enum, + driver::Bar0, + mm::VramAddress, + regs, // +}; + +bounded_enum! { + /// TLB invalidation acknowledgment scope. + /// + /// Controls how far the hardware waits for the invalidation to propag= ate + /// before clearing the `trigger` bit of `NV_TLB_FLUSH_CTRL`. + #[derive(Debug, Copy, Clone, PartialEq, Eq)] + pub(crate) enum TlbAckMode with TryFrom> { + /// Fire-and-forget: no acknowledgment required. + None =3D 0, + /// Wait for acknowledgment from all consumers, including remote G= PUs + /// reachable over NVLink. + /// + /// Globally is strictly required only during unmap or permission + /// tightening, because the backing memory may be reassigned after= the + /// flush returns and a stale TLB entry could let the GPU access f= reed + /// memory. For new mapping or relaxing permissions, a stale entry= would + /// merely cause a redundant fault and retry, so [`TlbAckMode::Non= e`] + /// would suffice. + Globally =3D 1, + /// Wait for acknowledgment from consumers within the local NVLink + /// fabric node only; skip cross-node ack. + Intranode =3D 2, + } +} + +/// TLB manager for GPU translation buffer operations. +#[pin_data] +pub(crate) struct Tlb { + bar: Arc>, + /// TLB flush serialization lock: This lock is designed to be acquired= during + /// the DMA fence signalling critical path. It should NEVER be held ac= ross any + /// reclaimable CPU memory allocations because the memory reclaim path= can + /// call `dma_fence_wait()` (when implemented), which would deadlock i= f lock held. + #[pin] + lock: Mutex<()>, +} + +impl Tlb { + /// Create a new TLB manager. + pub(super) fn new(bar: Arc>) -> impl PinInit { + pin_init!(Self { + bar, + lock <- new_mutex!((), "tlb_flush"), + }) + } + + /// Flush the GPU TLB for a specific page directory base. + /// + /// This invalidates all TLB entries associated with the given PDB add= ress. + /// Must be called after modifying page table entries to ensure the GP= U sees + /// the updated mappings. + pub(super) fn flush( + &self, + dev: &device::Device, + pdb_addr: VramAddress, + ) -> Result { + let _guard =3D self.lock.lock(); + let bar =3D self.bar.access(dev)?; + + // Write PDB address. + bar.write_reg(regs::NV_TLB_FLUSH_PDB_LO::from_pdb_addr(pdb_addr.ra= w())); + bar.write_reg(regs::NV_TLB_FLUSH_PDB_HI::from_pdb_addr(pdb_addr.ra= w())); + + // Trigger flush. + bar.write_reg( + regs::NV_TLB_FLUSH_CTRL::zeroed() + .with_all_va(true) + .with_ack(TlbAckMode::None) + .with_trigger(true), + ); + + // Poll for completion. + read_poll_timeout( + || Ok(bar.read(regs::NV_TLB_FLUSH_CTRL)), + |ctrl: ®s::NV_TLB_FLUSH_CTRL| !ctrl.trigger(), + Delta::ZERO, + Delta::from_secs(2), + )?; + + Ok(()) + } +} diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index fb42d96a59b2..277eb1a064f7 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -37,6 +37,7 @@ }, mm::{ pramin::Bar0WindowTarget, + tlb::TlbAckMode, VramAddress, // }, }; @@ -659,3 +660,67 @@ pub(crate) fn pramin_window_write_base( } } } + +// MMU TLB + +register! { + /// TLB flush register: PDB address lower bits. + pub(crate) NV_TLB_FLUSH_PDB_LO(u32) @ 0x00b830a0 { + /// PDB address bits [39:8]. + 31:0 pdb_lo =3D> u32; + } + + /// TLB flush register: PDB address higher bits. + pub(crate) NV_TLB_FLUSH_PDB_HI(u32) @ 0x00b830a4 { + /// PDB address bits [47:40]. + 7:0 pdb_hi =3D> u8; + } + + /// TLB flush control register. + pub(crate) NV_TLB_FLUSH_CTRL(u32) @ 0x00b830b0 { + /// Invalidate every VA in the PDB selected by `NV_TLB_FLUSH_PDB_L= O/HI`. + 0:0 all_va =3D> bool; + /// Invalidate TLBs for all PDBs (ignores `NV_TLB_FLUSH_PDB_LO/HI`= ). + 1:1 all_pdb =3D> bool; + /// Restrict the flush to the HUB MMU's TLBs; skip broadcasting to= the + /// per-GPC L2 TLBs. + /// + /// The GPU MMU has a two-level TLB hierarchy: + /// 1. The *HUB MMU* sits at the top and serves memory requests fr= om + /// "host-side" engines: the host/channel interface, copy engin= es, + /// display, and BAR1/BAR2 accesses. + /// 2. Each GPC (Graphics Processing Cluster =E2=80=94 the block t= hat houses + /// shader cores / SMs) has its own L2 TLB that serves requests= from + /// the compute and graphics engines inside the cluster. + /// + /// When set, only the HUB TLBs are invalidated. This is a perform= ance + /// optimization for flushes that only affect HUB-side mappings (e= .g. + /// BAR1/BAR2 windows), where fanning the invalidation out to every + /// GPC's L2 TLB would be wasted work. Must be false when flushing + /// mappings that may be cached by compute/graphics engines. + 2:2 hubtlb_only =3D> bool; + /// Invalidation acknowledgment scope. See [`TlbAckMode`] for deta= ils. + 8:7 ack ?=3D> TlbAckMode; + /// Write 1 to kick off the flush. Hardware clears this bit when t= he + /// flush completes; reads as 1 while the flush is in progress. + 31:31 trigger =3D> bool; + } +} + +impl NV_TLB_FLUSH_PDB_LO { + /// Create a register value from a PDB address. + /// + /// Extracts bits [39:8] of the address and shifts it right by 8 bits. + pub(crate) fn from_pdb_addr(addr: u64) -> Self { + Self::zeroed().with_pdb_lo(((addr >> 8) & 0xFFFF_FFFF) as u32) + } +} + +impl NV_TLB_FLUSH_PDB_HI { + /// Create a register value from a PDB address. + /// + /// Extracts bits [47:40] of the address and shifts it right by 40 bit= s. + pub(crate) fn from_pdb_addr(addr: u64) -> Self { + Self::zeroed().with_pdb_hi(((addr >> 40) & 0xFF) as u8) + } +} --=20 2.34.1 From nobody Mon May 25 04:34:26 2026 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013052.outbound.protection.outlook.com [40.107.201.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D672538E8BF; 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charset="utf-8" Add common page table types shared between MMU v2 and v3. These types are hardware-agnostic and used by both MMU versions. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm.rs | 1 + drivers/gpu/nova-core/mm/pagetable.rs | 158 ++++++++++++++++++++++++++ 2 files changed, 159 insertions(+) create mode 100644 drivers/gpu/nova-core/mm/pagetable.rs diff --git a/drivers/gpu/nova-core/mm.rs b/drivers/gpu/nova-core/mm.rs index ea415a88b221..66cc33389159 100644 --- a/drivers/gpu/nova-core/mm.rs +++ b/drivers/gpu/nova-core/mm.rs @@ -31,6 +31,7 @@ macro_rules! impl_pfn_bounded { }; } =20 +pub(super) mod pagetable; pub(crate) mod pramin; pub(super) mod tlb; =20 diff --git a/drivers/gpu/nova-core/mm/pagetable.rs b/drivers/gpu/nova-core/= mm/pagetable.rs new file mode 100644 index 000000000000..ed0f3d731c63 --- /dev/null +++ b/drivers/gpu/nova-core/mm/pagetable.rs @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Common page table types shared between MMU v2 and v3. +//! +//! This module provides foundational types used by both MMU versions: +//! - Page table level hierarchy +//! - Memory aperture types for PDEs and PTEs + +#![expect(dead_code)] + +use kernel::num::Bounded; + +use crate::gpu::Architecture; + +/// Extracts the page table index at a given level from a virtual address. +pub(super) trait VaLevelIndex { + /// Return the page table index at `level` for this virtual address. + fn level_index(&self, level: u64) -> u64; +} + +/// MMU version enumeration. +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub(crate) enum MmuVersion { + /// MMU v2 for Turing/Ampere/Ada. + V2, + /// MMU v3 for Hopper and later. + V3, +} + +impl From for MmuVersion { + fn from(arch: Architecture) -> Self { + match arch { + Architecture::Turing | Architecture::Ampere | Architecture::Ad= a =3D> Self::V2, + Architecture::Hopper | Architecture::BlackwellGB10x | Architec= ture::BlackwellGB20x =3D> { + Self::V3 + } + } + } +} + +/// Page Table Level hierarchy for MMU v2/v3. +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub(super) enum PageTableLevel { + /// Level 0 - Page Directory Base (root). + Pdb, + /// Level 1 - Intermediate page directory. + L1, + /// Level 2 - Intermediate page directory. + L2, + /// Level 3 - Intermediate page directory or dual PDE (version-depende= nt). + L3, + /// Level 4 - PTE level for v2, intermediate page directory for v3. + L4, + /// Level 5 - PTE level used for MMU v3 only. + L5, +} + +impl PageTableLevel { + /// Number of entries per page table (512 for 4KB pages). + pub(super) const ENTRIES_PER_TABLE: usize =3D 512; + + /// Get the next level in the hierarchy. + pub(super) const fn next(&self) -> Option { + match self { + Self::Pdb =3D> Some(Self::L1), + Self::L1 =3D> Some(Self::L2), + Self::L2 =3D> Some(Self::L3), + Self::L3 =3D> Some(Self::L4), + Self::L4 =3D> Some(Self::L5), + Self::L5 =3D> None, + } + } + + /// Convert level to index. + pub(super) const fn as_index(&self) -> u64 { + match self { + Self::Pdb =3D> 0, + Self::L1 =3D> 1, + Self::L2 =3D> 2, + Self::L3 =3D> 3, + Self::L4 =3D> 4, + Self::L5 =3D> 5, + } + } +} + +/// Memory aperture for Page Table Entries (`PTE`s). +/// +/// Determines which memory region the `PTE` points to. +#[repr(u8)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)] +pub(super) enum AperturePte { + /// Local video memory (VRAM). + #[default] + VideoMemory =3D 0, + /// Peer GPU's video memory. + PeerMemory =3D 1, + /// System memory with cache coherence. + SystemCoherent =3D 2, + /// System memory without cache coherence. + SystemNonCoherent =3D 3, +} + +// TODO[FPRI]: Replace with `#[derive(FromPrimitive)]` when available. +impl From> for AperturePte { + fn from(val: Bounded) -> Self { + match *val { + 0 =3D> Self::VideoMemory, + 1 =3D> Self::PeerMemory, + 2 =3D> Self::SystemCoherent, + 3 =3D> Self::SystemNonCoherent, + _ =3D> Self::VideoMemory, + } + } +} + +// TODO[FPRI]: Replace with `#[derive(ToPrimitive)]` when available. +impl From for Bounded { + fn from(val: AperturePte) -> Self { + Bounded::from_expr(val as u64 & 0x3) + } +} + +/// Memory aperture for Page Directory Entries (`PDE`s). +/// +/// Note: For `PDE`s, `Invalid` (0) means the entry is not valid. +#[repr(u8)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)] +pub(super) enum AperturePde { + /// Invalid/unused entry. + #[default] + Invalid =3D 0, + /// Page table is in video memory. + VideoMemory =3D 1, + /// Page table is in system memory with coherence. + SystemCoherent =3D 2, + /// Page table is in system memory without coherence. + SystemNonCoherent =3D 3, +} + +// TODO[FPRI]: Replace with `#[derive(FromPrimitive)]` when available. +impl From> for AperturePde { + fn from(val: Bounded) -> Self { + match *val { + 1 =3D> Self::VideoMemory, + 2 =3D> Self::SystemCoherent, + 3 =3D> Self::SystemNonCoherent, + _ =3D> Self::Invalid, + } + } +} + +// TODO[FPRI]: Replace with `#[derive(ToPrimitive)]` when available. +impl From for Bounded { + fn from(val: AperturePde) -> Self { + Bounded::from_expr(val as u64 & 0x3) + } +} --=20 2.34.1 From nobody Mon May 25 04:34:26 2026 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011013.outbound.protection.outlook.com [40.93.194.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 595E034A76E; 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charset="utf-8" Introduce a trait for GPU Page Table Entries (PTEs). New `read()`/`write()` helpers are provided that go through a `PraminWindow`). The forthcoming MMU v2, v3 PTE structs will each implement `PteOps`, allowing the later page-table walker and mapper to call PTE operations. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm/pagetable.rs | 38 +++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/gpu/nova-core/mm/pagetable.rs b/drivers/gpu/nova-core/= mm/pagetable.rs index ed0f3d731c63..a92add82eb10 100644 --- a/drivers/gpu/nova-core/mm/pagetable.rs +++ b/drivers/gpu/nova-core/mm/pagetable.rs @@ -8,9 +8,16 @@ =20 #![expect(dead_code)] =20 +use kernel::prelude::*; + use kernel::num::Bounded; =20 use crate::gpu::Architecture; +use crate::mm::{ + pramin, + Pfn, + VramAddress, // +}; =20 /// Extracts the page table index at a given level from a virtual address. pub(super) trait VaLevelIndex { @@ -84,6 +91,37 @@ pub(super) const fn as_index(&self) -> u64 { } } =20 +// Trait abstractions for page table operations. + +/// Operations on Page Table Entries (`PTE`s). +pub(super) trait PteOps: Copy + core::fmt::Debug + Into { + /// Create a `PTE` from a raw `u64` value. + fn from_raw(val: u64) -> Self; + + /// Create an invalid `PTE`. + fn invalid() -> Self; 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charset="utf-8" Introduce a trait for GPU Page Directory Entries (PDEs). Default `read()`/`write()` helpers via a `PraminWindow` are provided. The forthcoming MMU v2, v3 PDE structs will each implement `PdeOps`, allowing the later page-table walker and mapper to call PDE operations. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm/pagetable.rs | 37 +++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/gpu/nova-core/mm/pagetable.rs b/drivers/gpu/nova-core/= mm/pagetable.rs index a92add82eb10..1c94b3afa8b2 100644 --- a/drivers/gpu/nova-core/mm/pagetable.rs +++ b/drivers/gpu/nova-core/mm/pagetable.rs @@ -122,6 +122,43 @@ fn write(&self, window: &mut pramin::PraminWindow<'_>,= addr: VramAddress) -> Res } } =20 +/// Operations on Page Directory Entries (`PDE`s). +pub(super) trait PdeOps: Copy + core::fmt::Debug + Into { + /// Create a `PDE` from a raw `u64` value. + fn from_raw(val: u64) -> Self; + + /// Create a valid `PDE` pointing to a page table in the given apertur= e. + fn new(aperture: AperturePde, table_pfn: Pfn) -> Self; + + /// Create an invalid `PDE`. + fn invalid() -> Self; + + /// Check if this `PDE` is valid. + fn is_valid(&self) -> bool; + + /// Get the memory aperture of this `PDE`. + fn aperture(&self) -> AperturePde; + + /// Get the VRAM address of the page table. + fn table_vram_address(&self) -> VramAddress; + + /// Read a `PDE` from VRAM. + fn read(window: &mut pramin::PraminWindow<'_>, addr: VramAddress) -> R= esult { + let val =3D window.try_read64(addr)?; + Ok(Self::from_raw(val)) + } + + /// Write this `PDE` to VRAM. + fn write(&self, window: &mut pramin::PraminWindow<'_>, addr: VramAddre= ss) -> Result { + window.try_write64(addr, (*self).into()) + } + + /// Check if this `PDE` is valid and points to video memory. + fn is_valid_vram(&self) -> bool { + self.is_valid() && self.aperture() =3D=3D AperturePde::VideoMemory + } +} + /// Memory aperture for Page Table Entries (`PTE`s). /// /// Determines which memory region the `PTE` points to. --=20 2.34.1 From nobody Mon May 25 04:34:26 2026 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013052.outbound.protection.outlook.com [40.107.201.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B562838AC90; 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charset="utf-8" Introduce a trait for 128-bit Dual Page Directory Entries. The `read()`/`write()` helpers issue two 64-bit accesses through a `PraminWindow` to load/store the 128-bit value. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm/pagetable.rs | 34 +++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/gpu/nova-core/mm/pagetable.rs b/drivers/gpu/nova-core/= mm/pagetable.rs index 1c94b3afa8b2..7ea090024d91 100644 --- a/drivers/gpu/nova-core/mm/pagetable.rs +++ b/drivers/gpu/nova-core/mm/pagetable.rs @@ -159,6 +159,40 @@ fn is_valid_vram(&self) -> bool { } } =20 +/// Operations on Dual Page Directory Entries (128-bit `DualPde`s). +pub(super) trait DualPdeOps: Copy + core::fmt::Debug { + /// Create a `DualPde` from raw 128-bit value (two `u64`s). + fn from_raw(big: u64, small: u64) -> Self; + + /// Create a `DualPde` with only the small page table pointer set. + fn new_small(table_pfn: Pfn) -> Self; + + /// Check if the small page table pointer is valid. + fn has_small(&self) -> bool; + + /// Get the small page table VRAM address. + fn small_vram_address(&self) -> VramAddress; + + /// Get the raw `u64` value of the big PDE. + fn big_raw_u64(&self) -> u64; + + /// Get the raw `u64` value of the small PDE. + fn small_raw_u64(&self) -> u64; + + /// Read a dual PDE (128-bit) from VRAM. + fn read(window: &mut pramin::PraminWindow<'_>, addr: VramAddress) -> R= esult { + let lo =3D window.try_read64(addr)?; + let hi =3D window.try_read64(addr + 8)?; + Ok(Self::from_raw(lo, hi)) + } + + /// Write this dual PDE (128-bit) to VRAM. + fn write(&self, window: &mut pramin::PraminWindow<'_>, addr: VramAddre= ss) -> Result { + window.try_write64(addr, self.big_raw_u64())?; + window.try_write64(addr + 8, self.small_raw_u64()) + } +} + /// Memory aperture for Page Table Entries (`PTE`s). /// /// Determines which memory region the `PTE` points to. --=20 2.34.1 From nobody Mon May 25 04:34:26 2026 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013052.outbound.protection.outlook.com [40.107.201.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86C6D390CAC; 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charset="utf-8" Add page table entry and directory structures for MMU version 2 used by Hopper and later GPUs. The `Pte`, `Pde`, and `DualPde` types each implement the `PteOps`, `PdeOps`, and `DualPdeOps` traits introduced earlier in the series, providing the version-agnostic API used by the forthcoming page-table walker and mapper. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm/pagetable.rs | 2 + drivers/gpu/nova-core/mm/pagetable/ver2.rs | 271 +++++++++++++++++++++ 2 files changed, 273 insertions(+) create mode 100644 drivers/gpu/nova-core/mm/pagetable/ver2.rs diff --git a/drivers/gpu/nova-core/mm/pagetable.rs b/drivers/gpu/nova-core/= mm/pagetable.rs index 7ea090024d91..df041fc89390 100644 --- a/drivers/gpu/nova-core/mm/pagetable.rs +++ b/drivers/gpu/nova-core/mm/pagetable.rs @@ -8,6 +8,8 @@ =20 #![expect(dead_code)] =20 +pub(super) mod ver2; + use kernel::prelude::*; =20 use kernel::num::Bounded; diff --git a/drivers/gpu/nova-core/mm/pagetable/ver2.rs b/drivers/gpu/nova-= core/mm/pagetable/ver2.rs new file mode 100644 index 000000000000..089e5cc2bfc3 --- /dev/null +++ b/drivers/gpu/nova-core/mm/pagetable/ver2.rs @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! MMU v2 page table types for Turing, Ampere and Ada GPUs. +//! +//! This module defines MMU version 2 specific types (Turing, Ampere and A= da GPUs). +//! +//! Bit field layouts derived from the NVIDIA OpenRM documentation: +//! `open-gpu-kernel-modules/src/common/inc/swref/published/turing/tu102/d= ev_mmu.h` + +#![allow(dead_code)] + +use kernel::bitfield; +use kernel::num::Bounded; +use pin_init::Zeroable; + +use super::{ + AperturePde, + AperturePte, + DualPdeOps, + PageTableLevel, + PdeOps, + PteOps, + VaLevelIndex, // +}; +use crate::mm::{ + Pfn, + VirtualAddress, + VramAddress, // +}; + +// Bounded to version 2 Pfn bitfield conversions: +// 25 bits for video memory frame numbers (bits 32:8). +impl_pfn_bounded!(25); +// 46 bits for system memory frame numbers (bits 53:8). +impl_pfn_bounded!(46); + +bitfield! { + /// MMU v2 49-bit virtual address layout. + pub(super) struct VirtualAddressV2(u64) { + /// Page offset [11:0]. + 11:0 offset; + /// PT index [20:12]. + 20:12 pt_idx; + /// PDE0 index [28:21]. + 28:21 pde0_idx; + /// PDE1 index [37:29]. + 37:29 pde1_idx; + /// PDE2 index [46:38]. + 46:38 pde2_idx; + /// PDE3 index [48:47]. + 48:47 pde3_idx; + } +} + +impl VirtualAddressV2 { + /// Create a [`VirtualAddressV2`] from a [`VirtualAddress`]. + pub(super) fn new(va: VirtualAddress) -> Self { + Self::from_raw(va.into_raw()) + } +} + +impl VaLevelIndex for VirtualAddressV2 { + fn level_index(&self, level: u64) -> u64 { + match level { + 0 =3D> *self.pde3_idx(), + 1 =3D> *self.pde2_idx(), + 2 =3D> *self.pde1_idx(), + 3 =3D> *self.pde0_idx(), + 4 =3D> *self.pt_idx(), + _ =3D> 0, + } + } +} + +/// `PDE` levels for MMU v2 (5-level hierarchy: `PDB` -> `L1` -> `L2` -> `= L3` -> `L4`). +pub(super) const PDE_LEVELS: &[PageTableLevel] =3D &[ + PageTableLevel::Pdb, + PageTableLevel::L1, + PageTableLevel::L2, + PageTableLevel::L3, +]; + +/// `PTE` level for MMU v2. +pub(super) const PTE_LEVEL: PageTableLevel =3D PageTableLevel::L4; + +/// Dual `PDE` level for MMU v2 (128-bit entries). +pub(super) const DUAL_PDE_LEVEL: PageTableLevel =3D PageTableLevel::L3; + +// Page Table Entry (PTE) for MMU v2 - 64-bit entry at level 4. +bitfield! { + /// Page Table Entry for MMU v2. + pub(in crate::mm) struct Pte(u64) { + /// Entry is valid. + 0:0 valid; + /// Memory aperture type. + 2:1 aperture =3D> AperturePte; + /// Volatile (bypass L2 cache). + 3:3 volatile; + /// Encryption enabled (Confidential Computing). + 4:4 encrypted; + /// Privileged access only. + 5:5 privilege; + /// Write protection. + 6:6 read_only; + /// Atomic operations disabled. + 7:7 atomic_disable; + /// Frame number for system memory. + 53:8 frame_number_sys =3D> Pfn; + /// Frame number for video memory. + 32:8 frame_number_vid =3D> Pfn; + /// Peer GPU ID for peer memory (0-7). + 35:33 peer_id; + /// Compression tag line bits. + 53:36 comptagline; + /// Surface kind/format. + 63:56 kind; + } +} + +impl PteOps for Pte { + fn from_raw(val: u64) -> Self { + Self::from_raw(val) + } + + fn invalid() -> Self { + Self::zeroed() + } + + fn new(aperture: AperturePte, pfn: Pfn, writable: bool) -> Self { + let base =3D Self::zeroed() + .with_valid(true) + .with_aperture(aperture) + .with_read_only(!writable); + match aperture { + AperturePte::VideoMemory =3D> base.with_frame_number_vid(pfn), + // Sysmem PTEs use VOL=3D1 to bypass L2 for cache coherency. + AperturePte::SystemCoherent =3D> base.with_frame_number_sys(pf= n).with_volatile(true), + AperturePte::PeerMemory | AperturePte::SystemNonCoherent =3D> { + kernel::pr_warn!("MMU v2 PTE aperture {:?} not supported\n= ", aperture); + Self::invalid() + } + } + } + + fn is_valid(&self) -> bool { + self.valid().into_bool() + } + + fn frame_number(&self) -> Pfn { + match self.aperture() { + AperturePte::VideoMemory =3D> self.frame_number_vid(), + _ =3D> self.frame_number_sys(), + } + } +} + +// Page Directory Entry (PDE) for MMU v2 - 64-bit entry at levels 0-2. +bitfield! { + /// Page Directory Entry for MMU v2. + pub(in crate::mm) struct Pde(u64) { + /// Valid bit (inverted logic). + 0:0 valid_inverted; + /// Memory aperture type. + 2:1 aperture =3D> AperturePde; + /// Volatile (bypass L2 cache). + 3:3 volatile; + /// Disable Address Translation Services. + 5:5 no_ats; + /// Table frame number for system memory. + 53:8 table_frame_sys =3D> Pfn; + /// Table frame number for video memory. + 32:8 table_frame_vid =3D> Pfn; + /// Peer GPU ID (0-7). + 35:33 peer_id; + } +} + +impl PdeOps for Pde { + fn from_raw(val: u64) -> Self { + Self::from_raw(val) + } + + fn new(aperture: AperturePde, table_pfn: Pfn) -> Self { + let base =3D Self::zeroed() + .with_valid_inverted(false) // 0 =3D valid + .with_aperture(aperture); + match aperture { + AperturePde::VideoMemory =3D> base.with_table_frame_vid(table_= pfn), + // Sysmem PTEs use VOL=3D1 to bypass L2 for cache coherency. + AperturePde::SystemCoherent =3D> base.with_table_frame_sys(tab= le_pfn).with_volatile(true), + AperturePde::Invalid | AperturePde::SystemNonCoherent =3D> { + kernel::pr_warn!("MMU v2 PDE aperture {:?} not supported\n= ", aperture); + Self::invalid() + } + } + } + + fn invalid() -> Self { + Self::zeroed() + .with_valid_inverted(true) + .with_aperture(AperturePde::Invalid) + } + + fn is_valid(&self) -> bool { + !self.valid_inverted().into_bool() && self.aperture() !=3D Apertur= ePde::Invalid + } + + fn aperture(&self) -> AperturePde { + Pde::aperture(*self) + } + + fn table_vram_address(&self) -> VramAddress { + debug_assert!( + Pde::aperture(*self) =3D=3D AperturePde::VideoMemory, + "table_vram_address called on non-VRAM PDE (aperture: {:?})", + Pde::aperture(*self) + ); + VramAddress::from(self.table_frame_vid()) + } +} + +/// Dual `PDE` at Level 3 - 128-bit entry of Large/Small Page Table pointe= rs. +/// +/// The dual `PDE` supports both large (64KB) and small (4KB) page tables. +#[repr(C)] +#[derive(Debug, Clone, Copy)] +pub(in crate::mm) struct DualPde { + /// Large/Big Page Table pointer (lower 64 bits). + pub(super) big: Pde, + /// Small Page Table pointer (upper 64 bits). + pub(super) small: Pde, +} + +impl DualPde { + /// Check if the big page table pointer is valid. + fn has_big(&self) -> bool { + PdeOps::is_valid(&self.big) + } +} + +impl DualPdeOps for DualPde { + fn from_raw(big: u64, small: u64) -> Self { + Self { + big: PdeOps::from_raw(big), + small: PdeOps::from_raw(small), + } + } + + fn new_small(table_pfn: Pfn) -> Self { + Self { + big: PdeOps::from_raw(0), + small: PdeOps::new(AperturePde::VideoMemory, table_pfn), + } + } + + fn has_small(&self) -> bool { + PdeOps::is_valid(&self.small) + } + + fn small_vram_address(&self) -> VramAddress { + PdeOps::table_vram_address(&self.small) + } + + fn big_raw_u64(&self) -> u64 { + self.big.into_raw() + } + + fn small_raw_u64(&self) -> u64 { + self.small.into_raw() + } +} --=20 2.34.1 From nobody Mon May 25 04:34:26 2026 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013052.outbound.protection.outlook.com [40.107.201.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC454392C2C; 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charset="utf-8" Add page table entry and directory structures for MMU version 3 used by Hopper and later GPUs. The `Pte`, `Pde`, and `DualPde` types each implement the `PteOps`, `PdeOps`, and `DualPdeOps` traits introduced earlier in the series, providing the version-agnostic API used by the forthcoming page-table walker and mapper. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm/pagetable.rs | 1 + drivers/gpu/nova-core/mm/pagetable/ver3.rs | 421 +++++++++++++++++++++ 2 files changed, 422 insertions(+) create mode 100644 drivers/gpu/nova-core/mm/pagetable/ver3.rs diff --git a/drivers/gpu/nova-core/mm/pagetable.rs b/drivers/gpu/nova-core/= mm/pagetable.rs index df041fc89390..3cc546f94fdb 100644 --- a/drivers/gpu/nova-core/mm/pagetable.rs +++ b/drivers/gpu/nova-core/mm/pagetable.rs @@ -9,6 +9,7 @@ #![expect(dead_code)] =20 pub(super) mod ver2; +pub(super) mod ver3; =20 use kernel::prelude::*; =20 diff --git a/drivers/gpu/nova-core/mm/pagetable/ver3.rs b/drivers/gpu/nova-= core/mm/pagetable/ver3.rs new file mode 100644 index 000000000000..805be90df45d --- /dev/null +++ b/drivers/gpu/nova-core/mm/pagetable/ver3.rs @@ -0,0 +1,421 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! MMU v3 page table types for Hopper and later GPUs. +//! +//! This module defines MMU version 3 specific types (Hopper and later GPU= s). +//! +//! Key differences from MMU v2: +//! - Unified 40-bit address field for all apertures (v2 had separate sys/= vid fields). +//! - PCF (Page Classification Field) replaces separate privilege/RO/atomi= c/cache bits. +//! - KIND field is 4 bits (not 8). +//! - IS_PTE bit in PDE to support large pages directly. +//! - No COMPTAGLINE field (compression handled differently in v3). +//! - No separate ENCRYPTED bit. +//! +//! Bit field layouts derived from the NVIDIA OpenRM documentation: +//! `open-gpu-kernel-modules/src/common/inc/swref/published/hopper/gh100/d= ev_mmu.h` + +#![allow(dead_code)] + +use kernel::bitfield; +use kernel::num::Bounded; +use kernel::prelude::*; +use pin_init::Zeroable; + +use super::{ + AperturePde, + AperturePte, + DualPdeOps, + PageTableLevel, + PdeOps, + PteOps, + VaLevelIndex, // +}; +use crate::mm::{ + Pfn, + VirtualAddress, + VramAddress, // +}; + +// Bounded to version 3 Pfn conversion. +impl_pfn_bounded!(40); + +bitfield! { + /// MMU v3 57-bit virtual address layout. + pub(super) struct VirtualAddressV3(u64) { + /// Page offset [11:0]. + 11:0 offset; + /// PT index [20:12]. + 20:12 pt_idx; + /// PDE0 index [28:21]. + 28:21 pde0_idx; + /// PDE1 index [37:29]. + 37:29 pde1_idx; + /// PDE2 index [46:38]. + 46:38 pde2_idx; + /// PDE3 index [55:47]. + 55:47 pde3_idx; + /// PDE4 index [56]. + 56:56 pde4_idx; + } +} + +impl VirtualAddressV3 { + /// Create a [`VirtualAddressV3`] from a [`VirtualAddress`]. + pub(super) fn new(va: VirtualAddress) -> Self { + Self::from_raw(va.into_raw()) + } +} + +impl VaLevelIndex for VirtualAddressV3 { + fn level_index(&self, level: u64) -> u64 { + match level { + 0 =3D> *self.pde4_idx(), + 1 =3D> *self.pde3_idx(), + 2 =3D> *self.pde2_idx(), + 3 =3D> *self.pde1_idx(), + 4 =3D> *self.pde0_idx(), + 5 =3D> *self.pt_idx(), + _ =3D> 0, + } + } +} + +/// PDE levels for MMU v3 (6-level hierarchy). +pub(super) const PDE_LEVELS: &[PageTableLevel] =3D &[ + PageTableLevel::Pdb, + PageTableLevel::L1, + PageTableLevel::L2, + PageTableLevel::L3, + PageTableLevel::L4, +]; + +/// PTE level for MMU v3. +pub(super) const PTE_LEVEL: PageTableLevel =3D PageTableLevel::L5; + +/// Dual PDE level for MMU v3 (128-bit entries). +pub(super) const DUAL_PDE_LEVEL: PageTableLevel =3D PageTableLevel::L4; + +bitfield! { + /// Page Classification Field for PTEs (5 bits) in MMU v3. + pub(in crate::mm) struct PtePcf(u8) { + /// Bypass L2 cache (0=3Dcached, 1=3Dbypass). + 0:0 uncached; + /// Access counting disabled (0=3Denabled, 1=3Ddisabled). + 1:1 acd; + /// Read-only access (0=3Dread-write, 1=3Dread-only). + 2:2 read_only; + /// Atomics disabled (0=3Denabled, 1=3Ddisabled). + 3:3 no_atomic; + /// Privileged access only (0=3Dregular, 1=3Dprivileged). + 4:4 privileged; + } +} + +impl PtePcf { + /// Create PCF for read-write mapping (cached, no atomics, regular mod= e). + fn rw() -> Self { + Self::zeroed().with_no_atomic(true) + } + + /// Create PCF for read-only mapping (cached, no atomics, regular mode= ). + fn ro() -> Self { + Self::zeroed().with_read_only(true).with_no_atomic(true) + } + + /// Get the raw `u8` value. + fn raw_u8(&self) -> u8 { + self.into_raw() + } +} + +impl From> for PtePcf { + fn from(val: Bounded) -> Self { + Self::from_raw(u8::from(val)) + } +} + +impl From for Bounded { + fn from(pcf: PtePcf) -> Self { + Bounded::from_expr(u64::from(pcf.into_raw()) & 0x1F) + } +} + +bitfield! { + /// Page Classification Field for PDEs (3 bits) in MMU v3. + /// + /// Controls Address Translation Services (ATS) and caching. + pub(in crate::mm) struct PdePcf(u8) { + /// Bypass L2 cache (0=3Dcached, 1=3Dbypass). + 0:0 uncached; + /// ATS disabled (0=3Denabled, 1=3Ddisabled). + 1:1 no_ats; + } +} + +impl PdePcf { + /// Create PCF for cached mapping with ATS enabled (default). + fn cached() -> Self { + Self::zeroed() + } + + /// Get the raw `u8` value. + fn raw_u8(&self) -> u8 { + self.into_raw() + } +} + +impl From> for PdePcf { + fn from(val: Bounded) -> Self { + Self::from_raw(u8::from(val)) + } +} + +impl From for Bounded { + fn from(pcf: PdePcf) -> Self { + Bounded::from_expr(u64::from(pcf.into_raw()) & 0x7) + } +} + +bitfield! { + /// Page Table Entry for MMU v3. + pub(in crate::mm) struct Pte(u64) { + /// Entry is valid. + 0:0 valid; + /// Memory aperture type. + 2:1 aperture =3D> AperturePte; + /// Page Classification Field. + 7:3 pcf =3D> PtePcf; + /// Surface kind (4 bits, 0x0=3Dpitch, 0xF=3Dinvalid). + 11:8 kind; + /// Physical frame number (for all apertures). + 51:12 frame_number =3D> Pfn; + /// Peer GPU ID for peer memory (0-7). + 63:61 peer_id; + } +} + +impl PteOps for Pte { + fn from_raw(val: u64) -> Self { + Self::from_raw(val) + } + + fn invalid() -> Self { + Self::zeroed() + } + + fn new(aperture: AperturePte, pfn: Pfn, writable: bool) -> Self { + let pcf =3D match (aperture, writable) { + (AperturePte::VideoMemory, true) =3D> PtePcf::rw(), + (AperturePte::VideoMemory, false) =3D> PtePcf::ro(), + // Sysmem PTEs use uncached+no_atomic PCF for cache coherency. + (AperturePte::SystemCoherent, true) =3D> PtePcf::zeroed() + .with_uncached(true) + .with_no_atomic(true), + (AperturePte::SystemCoherent, false) =3D> PtePcf::zeroed() + .with_uncached(true) + .with_no_atomic(true) + .with_read_only(true), + (AperturePte::PeerMemory | AperturePte::SystemNonCoherent, _) = =3D> { + kernel::pr_warn!("MMU v3 PTE aperture {:?} not supported\n= ", aperture); + return Self::invalid(); + } + }; + Self::zeroed() + .with_valid(true) + .with_aperture(aperture) + .with_pcf(pcf) + .with_frame_number(pfn) + } + + fn is_valid(&self) -> bool { + self.valid().into_bool() + } + + fn frame_number(&self) -> Pfn { + Pte::frame_number(*self) + } +} + +bitfield! { + /// Page Directory Entry for MMU v3 (Hopper+). + /// + /// ## Note + /// + /// v3 uses a unified 40-bit address field (v2 had separate sys/vid ad= dress fields). + pub(in crate::mm) struct Pde(u64) { + /// Entry is a PTE (0=3DPDE, 1=3Dlarge page PTE). + 0:0 is_pte; + /// Memory aperture type. + 2:1 aperture =3D> AperturePde; + /// Page Classification Field (3 bits for PDE). + 5:3 pcf =3D> PdePcf; + /// Table frame number (40-bit unified address). + 51:12 table_frame =3D> Pfn; + } +} + +impl PdeOps for Pde { + fn from_raw(val: u64) -> Self { + Self::from_raw(val) + } + + fn new(aperture: AperturePde, table_pfn: Pfn) -> Self { + match aperture { + AperturePde::VideoMemory =3D> Self::zeroed() + .with_is_pte(false) + .with_aperture(aperture) + .with_table_frame(table_pfn), + AperturePde::Invalid + | AperturePde::SystemCoherent + | AperturePde::SystemNonCoherent =3D> { + kernel::pr_warn!("MMU v3 PDE aperture {:?} not supported\n= ", aperture); + Self::invalid() + } + } + } + + fn invalid() -> Self { + Self::zeroed().with_aperture(AperturePde::Invalid) + } + + fn is_valid(&self) -> bool { + Pde::aperture(*self) !=3D AperturePde::Invalid + } + + fn aperture(&self) -> AperturePde { + Pde::aperture(*self) + } + + fn table_vram_address(&self) -> VramAddress { + debug_assert!( + Pde::aperture(*self) =3D=3D AperturePde::VideoMemory, + "table_vram_address called on non-VRAM PDE (aperture: {:?})", + Pde::aperture(*self) + ); + VramAddress::from(self.table_frame()) + } +} + +bitfield! { + /// Big Page Table pointer in Dual PDE (MMU v3). + /// + /// 64-bit lower word of the 128-bit Dual PDE. + pub(super) struct DualPdeBig(u64) { + /// Entry is a PTE (for large pages). + 0:0 is_pte; + /// Memory aperture type. + 2:1 aperture =3D> AperturePde; + /// Page Classification Field. + 5:3 pcf =3D> PdePcf; + /// Table frame (table address 256-byte aligned). + 51:8 table_frame; + } +} + +impl DualPdeBig { + /// Create an invalid big page table pointer. + fn invalid() -> Self { + Self::zeroed().with_aperture(AperturePde::Invalid) + } + + /// Create a valid big PDE pointing to a page table in the given apert= ure. + fn new(aperture: AperturePde, table_addr: VramAddress) -> Result= { + // Big page table addresses must be 256-byte aligned (shift 8). + if table_addr.raw() & 0xFF !=3D 0 { + return Err(EINVAL); + } + let table_frame =3D Bounded::from_expr(table_addr.raw() >> 8); + match aperture { + AperturePde::VideoMemory =3D> Ok(Self::zeroed() + .with_is_pte(false) + .with_aperture(aperture) + .with_table_frame(table_frame)), + AperturePde::Invalid + | AperturePde::SystemCoherent + | AperturePde::SystemNonCoherent =3D> { + kernel::pr_warn!("MMU v3 DualPdeBig aperture {:?} not supp= orted\n", aperture); + Ok(Self::invalid()) + } + } + } + + /// Check if this big PDE is valid. + fn is_valid(&self) -> bool { + self.aperture() !=3D AperturePde::Invalid + } + + /// Get the VRAM address of the big page table. + fn table_vram_address(&self) -> VramAddress { + debug_assert!( + self.aperture() =3D=3D AperturePde::VideoMemory, + "table_vram_address called on non-VRAM DualPdeBig (aperture: {= :?})", + self.aperture() + ); + VramAddress::new(*self.table_frame() << 8) + } +} + +/// Dual PDE at Level 4 for MMU v3 - 128-bit entry. +/// +/// Contains both big (64KB) and small (4KB) page table pointers: +/// - Lower 64 bits: Big Page Table pointer. +/// - Upper 64 bits: Small Page Table pointer. +/// +/// ## Note +/// +/// The big and small page table pointers have different address layouts: +/// - Big address =3D field value << 8 (256-byte alignment). +/// - Small address =3D field value << 12 (4KB alignment). +/// +/// This is why `DualPdeBig` is a separate type from `Pde`. +#[repr(C)] +#[derive(Debug, Clone, Copy)] +pub(in crate::mm) struct DualPde { + /// Big Page Table pointer. + pub(super) big: DualPdeBig, + /// Small Page Table pointer. + pub(super) small: Pde, +} + +// SAFETY: Both `DualPdeBig` and `Pde` fields are `Zeroable` (bitfield typ= es are Zeroable). +unsafe impl Zeroable for DualPde {} + +impl DualPde { + /// Check if the big page table pointer is valid. + fn has_big(&self) -> bool { + self.big.is_valid() + } +} + +impl DualPdeOps for DualPde { + fn from_raw(big: u64, small: u64) -> Self { + Self { + big: DualPdeBig::from_raw(big), + small: PdeOps::from_raw(small), + } + } + + fn new_small(table_pfn: Pfn) -> Self { + Self { + big: DualPdeBig::invalid(), + small: PdeOps::new(AperturePde::VideoMemory, table_pfn), + } + } + + fn has_small(&self) -> bool { + PdeOps::is_valid(&self.small) + } + + fn small_vram_address(&self) -> VramAddress { + PdeOps::table_vram_address(&self.small) + } + + fn big_raw_u64(&self) -> u64 { + self.big.into_raw() + } + + fn small_raw_u64(&self) -> u64 { + self.small.into_raw() + } +} --=20 2.34.1 From nobody Mon May 25 04:34:26 2026 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013052.outbound.protection.outlook.com [40.107.201.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C7AE3932E6; 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charset="utf-8" Introduce `MmuConfig`, the trait that ties the entry-operation traits (`PteOps`, `PdeOps`, `DualPdeOps`) together with the version-specific constants and helpers. `MmuV2` and `MmuV3` are zero-sized marker structs that implement `MmuConfig` for Turing/Ampere/Ada and Hopper/Blackwell respectively. Dispatch is fully resolved at compile time through these markers, so version-specific code is selected without runtime overhead and without wrapper enums. This enables version-agnostic page-table operations while keeping version-specific implementation details encapsulated in the `ver2` and `ver3` modules. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm/pagetable.rs | 109 ++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/drivers/gpu/nova-core/mm/pagetable.rs b/drivers/gpu/nova-core/= mm/pagetable.rs index 3cc546f94fdb..38f4f0c6e8ce 100644 --- a/drivers/gpu/nova-core/mm/pagetable.rs +++ b/drivers/gpu/nova-core/mm/pagetable.rs @@ -19,6 +19,7 @@ use crate::mm::{ pramin, Pfn, + VirtualAddress, VramAddress, // }; =20 @@ -196,6 +197,114 @@ fn write(&self, window: &mut pramin::PraminWindow<'_>= , addr: VramAddress) -> Res } } =20 +/// MMU configuration trait -- encodes version-specific constants and type= s. +pub(super) trait MmuConfig: 'static { + /// Page Table Entry type. + type Pte: PteOps; + /// Page Directory Entry type. + type Pde: PdeOps; + /// Dual Page Directory Entry type (128-bit). + type DualPde: DualPdeOps; + + /// PDE levels (excluding PTE level) for page table walking. + const PDE_LEVELS: &'static [PageTableLevel]; + /// PTE level for this MMU version. + const PTE_LEVEL: PageTableLevel; + /// Dual PDE level (128-bit entries) for this MMU version. + const DUAL_PDE_LEVEL: PageTableLevel; + + /// Get the number of entries per page table page for a given level. + fn entries_per_page(level: PageTableLevel) -> usize; + + /// Extract the page table index at `level` from `va`. + fn level_index(va: VirtualAddress, level: u64) -> u64; + + /// Get the entry size in bytes for a given level. + fn entry_size(level: PageTableLevel) -> usize { + if level =3D=3D Self::DUAL_PDE_LEVEL { + 16 // 128-bit dual PDE + } else { + 8 // 64-bit PDE/PTE + } + } + + /// Compute upper bound on page table pages needed for `num_virt_pages= `. + /// + /// Walks from PTE level up through PDE levels, accumulating the tree. + fn pt_pages_upper_bound(num_virt_pages: usize) -> usize { + let mut total =3D 0; + + // PTE pages at the leaf level. + let pte_epp =3D Self::entries_per_page(Self::PTE_LEVEL); + let mut pages_at_level =3D num_virt_pages.div_ceil(pte_epp); + total +=3D pages_at_level; + + // Walk PDE levels bottom-up (reverse of PDE_LEVELS). + for &level in Self::PDE_LEVELS.iter().rev() { + let epp =3D Self::entries_per_page(level); + + // How many pages at this level do we need to point to + // the previous pages_at_level? + pages_at_level =3D pages_at_level.div_ceil(epp); + total +=3D pages_at_level; + } + + total + } +} + +/// Marker struct for MMU v2 (Turing/Ampere/Ada). +pub(super) struct MmuV2; + +impl MmuConfig for MmuV2 { + type Pte =3D ver2::Pte; + type Pde =3D ver2::Pde; + type DualPde =3D ver2::DualPde; + + const PDE_LEVELS: &'static [PageTableLevel] =3D ver2::PDE_LEVELS; + const PTE_LEVEL: PageTableLevel =3D ver2::PTE_LEVEL; + const DUAL_PDE_LEVEL: PageTableLevel =3D ver2::DUAL_PDE_LEVEL; + + fn entries_per_page(level: PageTableLevel) -> usize { + // TODO: Calculate these values from the bitfield dynamically + // instead of hardcoding them. + match level { + PageTableLevel::Pdb =3D> 4, // PD3 root: bits [48:47] =3D 2 b= its + PageTableLevel::L3 =3D> 256, // PD0 dual: bits [28:21] =3D 8 b= its + _ =3D> 512, // PD2, PD1, PT: 9 bits each + } + } + + fn level_index(va: VirtualAddress, level: u64) -> u64 { + ver2::VirtualAddressV2::new(va).level_index(level) + } +} + +/// Marker struct for MMU v3 (Hopper and later). +pub(super) struct MmuV3; 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charset="utf-8" Add the page table walker implementation that traverses the page table hierarchy for both MMU v2 (5-level) and MMU v3 (6-level) to resolve virtual addresses to physical addresses or find PTE locations. Currently only v2 has been tested (nova-core currently boots pre-hopper) with some initial preparatory work done for v3. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm/pagetable.rs | 1 + drivers/gpu/nova-core/mm/pagetable/walk.rs | 258 +++++++++++++++++++++ 2 files changed, 259 insertions(+) create mode 100644 drivers/gpu/nova-core/mm/pagetable/walk.rs diff --git a/drivers/gpu/nova-core/mm/pagetable.rs b/drivers/gpu/nova-core/= mm/pagetable.rs index 38f4f0c6e8ce..5e192679f27c 100644 --- a/drivers/gpu/nova-core/mm/pagetable.rs +++ b/drivers/gpu/nova-core/mm/pagetable.rs @@ -10,6 +10,7 @@ =20 pub(super) mod ver2; pub(super) mod ver3; +pub(super) mod walk; =20 use kernel::prelude::*; =20 diff --git a/drivers/gpu/nova-core/mm/pagetable/walk.rs b/drivers/gpu/nova-= core/mm/pagetable/walk.rs new file mode 100644 index 000000000000..a5f6c461f96a --- /dev/null +++ b/drivers/gpu/nova-core/mm/pagetable/walk.rs @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Page table walker implementation for NVIDIA GPUs. +//! +//! This module provides page table walking functionality for MMU v2 and v= 3. +//! The walker traverses the page table hierarchy to resolve virtual addre= sses +//! to physical addresses or to find PTE locations. +//! +//! # Page Table Hierarchy +//! +//! ## MMU v2 (Turing/Ampere/Ada) - 5 levels +//! +//! ```text +//! +-------+ +-------+ +-------+ +---------+ +-------+ +//! | PDB |---->| L1 |---->| L2 |---->| L3 Dual |---->| L4 | +//! | (L0) | | | | | | PDE | | (PTE) | +//! +-------+ +-------+ +-------+ +---------+ +-------+ +//! 64-bit 64-bit 64-bit 128-bit 64-bit +//! PDE PDE PDE (big+small) PTE +//! ``` +//! +//! ## MMU v3 (Hopper+) - 6 levels +//! +//! ```text +//! +-------+ +-------+ +-------+ +-------+ +---------= + +-------+ +//! | PDB |---->| L1 |---->| L2 |---->| L3 |---->| L4 Dual = |---->| L5 | +//! | (L0) | | | | | | | | PDE = | | (PTE) | +//! +-------+ +-------+ +-------+ +-------+ +---------= + +-------+ +//! 64-bit 64-bit 64-bit 64-bit 128-bit = 64-bit +//! PDE PDE PDE PDE (big+small= ) PTE +//! ``` +//! +//! # Result of a page table walk +//! +//! The walker returns a [`WalkResult`] indicating the outcome. + +use core::marker::PhantomData; + +use kernel::{ + device, + prelude::*, // +}; + +use super::{ + DualPdeOps, + MmuConfig, + MmuV2, + MmuV3, + MmuVersion, + PageTableLevel, + PdeOps, + PteOps, // +}; +use crate::{ + mm::{ + pramin, + GpuMm, + Pfn, + Vfn, + VirtualAddress, + VramAddress, // + }, + num::{ + IntoSafeCast, // + }, +}; + +/// Result of walking to a PTE. +#[derive(Debug, Clone, Copy)] +pub(in crate::mm) enum WalkResult { + /// Intermediate page tables are missing (only returned in lookup mode= ). + PageTableMissing, + /// PTE exists but is invalid (page not mapped). + Unmapped { pte_addr: VramAddress }, + /// PTE exists and is valid (page is mapped). + Mapped { pte_addr: VramAddress, pfn: Pfn }, +} + +/// Result of walking PDE levels only. +/// +/// Returned by [`PtWalkInner::walk_pde_levels()`] to indicate whether all= PDE +/// levels resolved or a PDE is missing. +#[derive(Debug, Clone, Copy)] +pub(in crate::mm) enum WalkPdeResult { + /// All PDE levels resolved -- returns PTE page table address. + Complete { + /// VRAM address of the PTE-level page table. + pte_table: VramAddress, + }, + /// A PDE is missing and no prepared page was provided by the closure. + Missing { + /// PDE slot address in the parent page table (where to install). + install_addr: VramAddress, + /// The page table level that is missing. + level: PageTableLevel, + }, +} + +/// Page table walker. +pub(in crate::mm) struct PtWalkInner { + pdb_addr: VramAddress, + _phantom: PhantomData, +} + +impl PtWalkInner { + /// Calculate the VRAM address of an entry within a page table. + fn entry_addr(table: VramAddress, level: PageTableLevel, index: u64) -= > VramAddress { + let entry_size: u64 =3D M::entry_size(level).into_safe_cast(); + table + index * entry_size + } + + /// Create a new page table walker. + pub(super) fn new(pdb_addr: VramAddress) -> Self { + Self { + pdb_addr, + _phantom: PhantomData, + } + } + + /// Walk PDE levels with closure-based resolution for missing PDEs. + /// + /// Traverses all PDE levels for the MMU version. At each level, reads= the PDE. + /// If valid, extracts the child table address and continues. If missi= ng, calls + /// `resolve_prepared(install_addr)` to resolve the missing PDE. + pub(super) fn walk_pde_levels( + &self, + window: &mut pramin::PraminWindow<'_>, + vfn: Vfn, + resolve_prepared: impl Fn(VramAddress) -> Option, + ) -> Result { + let va =3D VirtualAddress::from(vfn); + let mut cur_table =3D self.pdb_addr; + + for &level in M::PDE_LEVELS { + let idx =3D M::level_index(va, level.as_index()); + let install_addr =3D Self::entry_addr(cur_table, level, idx); + + if level =3D=3D M::DUAL_PDE_LEVEL { + // 128-bit dual PDE with big+small page table pointers. + let dpde =3D M::DualPde::read(window, install_addr)?; + if dpde.has_small() { + cur_table =3D dpde.small_vram_address(); + continue; + } + } else { + // Regular 64-bit PDE. Use `is_valid_vram()` because + // `table_vram_address()` only reads the VRAM frame-number + // bitfield; system-memory PDEs store the address in a + // different (wider) field and would be silently truncated. + let pde =3D M::Pde::read(window, install_addr)?; + if pde.is_valid_vram() { + cur_table =3D pde.table_vram_address(); + continue; + } + } + + // PDE missing in HW. Ask caller for resolution. + if let Some(prepared_addr) =3D resolve_prepared(install_addr) { + cur_table =3D prepared_addr; + continue; + } + + return Ok(WalkPdeResult::Missing { + install_addr, + level, + }); + } + + Ok(WalkPdeResult::Complete { + pte_table: cur_table, + }) + } + + /// Walk to PTE for lookup only (no allocation). + /// + /// Returns [`WalkResult::PageTableMissing`] if intermediate tables do= n't exist. + pub(super) fn walk_to_pte_lookup( + &self, + dev: &device::Device, + mm: &GpuMm, + vfn: Vfn, + ) -> Result { + let mut window =3D mm.pramin().get_window(dev)?; + self.walk_to_pte_lookup_with_window(&mut window, vfn) + } + + /// Walk to PTE using a caller-provided PRAMIN window (lookup only). + pub(super) fn walk_to_pte_lookup_with_window( + &self, + window: &mut pramin::PraminWindow<'_>, + vfn: Vfn, + ) -> Result { + match self.walk_pde_levels(window, vfn, |_| None)? { + WalkPdeResult::Complete { pte_table } =3D> { + Self::read_pte_at_level(window, vfn, pte_table) + } + WalkPdeResult::Missing { .. } =3D> Ok(WalkResult::PageTableMis= sing), + } + } + + /// Read the PTE at the PTE level given the PTE table address. + fn read_pte_at_level( + window: &mut pramin::PraminWindow<'_>, + vfn: Vfn, + pte_table: VramAddress, + ) -> Result { + let va =3D VirtualAddress::from(vfn); + let pte_level =3D M::PTE_LEVEL; + let pte_idx =3D M::level_index(va, pte_level.as_index()); + let pte_addr =3D Self::entry_addr(pte_table, pte_level, pte_idx); + let pte =3D M::Pte::read(window, pte_addr)?; + + if pte.is_valid() { + return Ok(WalkResult::Mapped { + pte_addr, + pfn: pte.frame_number(), + }); + } + Ok(WalkResult::Unmapped { pte_addr }) + } +} + +macro_rules! pt_walk_dispatch { + ($self:expr, $method:ident ( $($arg:expr),* $(,)? )) =3D> { + match $self { + PtWalk::V2(inner) =3D> inner.$method($($arg),*), + PtWalk::V3(inner) =3D> inner.$method($($arg),*), + } + }; +} + +/// Page table walker dispatch. +pub(in crate::mm) enum PtWalk { + /// MMU v2 (Turing/Ampere/Ada). + V2(PtWalkInner), + /// MMU v3 (Hopper+). + V3(PtWalkInner), +} + +impl PtWalk { + /// Create a new page table walker for the given MMU version. + pub(in crate::mm) fn new(pdb_addr: VramAddress, version: MmuVersion) -= > Self { + match version { + MmuVersion::V2 =3D> Self::V2(PtWalkInner::::new(pdb_add= r)), + MmuVersion::V3 =3D> Self::V3(PtWalkInner::::new(pdb_add= r)), + } + } + + /// Walk to PTE for lookup. + pub(in crate::mm) fn walk_to_pte( + &self, + dev: &device::Device, + mm: &GpuMm, + vfn: Vfn, + ) -> Result { + pt_walk_dispatch!(self, walk_to_pte_lookup(dev, mm, vfn)) + } +} --=20 2.34.1 From nobody Mon May 25 04:34:26 2026 Received: from CH1PR05CU001.outbound.protection.outlook.com (mail-northcentralusazon11010024.outbound.protection.outlook.com [52.101.193.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5812B38F92F; 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charset="utf-8" Add the Virtual Memory Manager (VMM) infrastructure for GPU address space management. Each Vmm instance manages a single address space identified by its Page Directory Base (PDB) address, used for Channel, BAR1 and BAR2 mappings. Mapping APIs and virtual address range tracking are added in later commits. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm.rs | 1 + drivers/gpu/nova-core/mm/vmm.rs | 64 +++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 drivers/gpu/nova-core/mm/vmm.rs diff --git a/drivers/gpu/nova-core/mm.rs b/drivers/gpu/nova-core/mm.rs index 66cc33389159..502c7fdceba2 100644 --- a/drivers/gpu/nova-core/mm.rs +++ b/drivers/gpu/nova-core/mm.rs @@ -34,6 +34,7 @@ macro_rules! impl_pfn_bounded { pub(super) mod pagetable; pub(crate) mod pramin; pub(super) mod tlb; +pub(super) mod vmm; =20 use core::ops::Range; =20 diff --git a/drivers/gpu/nova-core/mm/vmm.rs b/drivers/gpu/nova-core/mm/vmm= .rs new file mode 100644 index 000000000000..3e18adc23b68 --- /dev/null +++ b/drivers/gpu/nova-core/mm/vmm.rs @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Virtual Memory Manager for NVIDIA GPU page table management. +//! +//! The [`Vmm`] provides high-level page mapping and unmapping operations = for GPU +//! virtual address spaces (Channels, BAR1, BAR2). It wraps the page table= walker +//! and handles TLB flushing after modifications. + +use kernel::{ + device, + gpu::buddy::AllocatedBlocks, + prelude::*, // +}; + +use crate::mm::{ + pagetable::{ + walk::{PtWalk, WalkResult}, + MmuVersion, // + }, + GpuMm, + Pfn, + Vfn, + VramAddress, // +}; + +/// Virtual Memory Manager for a GPU address space. +/// +/// Each [`Vmm`] instance manages a single address space identified by its= Page +/// Directory Base (`PDB`) address. The [`Vmm`] is used for Channel, BAR1 = and +/// BAR2 mappings. +pub(crate) struct Vmm { + /// Page Directory Base address for this address space. + pdb_addr: VramAddress, + /// MMU version used for page table layout. + mmu_version: MmuVersion, + /// Page table allocations required for mappings. + page_table_allocs: KVec>>, +} + +impl Vmm { + /// Create a new [`Vmm`] for the given Page Directory Base address. + pub(crate) fn new(pdb_addr: VramAddress, mmu_version: MmuVersion) -> R= esult { + Ok(Self { + pdb_addr, + mmu_version, + page_table_allocs: KVec::new(), + }) + } + + /// Read the [`Pfn`] for a mapped [`Vfn`] if one is mapped. + pub(super) fn read_mapping( + &self, + dev: &device::Device, + mm: &GpuMm, + vfn: Vfn, + ) -> Result> { + let walker =3D PtWalk::new(self.pdb_addr, self.mmu_version); + + match walker.walk_to_pte(dev, mm, vfn)? { + WalkResult::Mapped { pfn, .. } =3D> Ok(Some(pfn)), + WalkResult::Unmapped { .. } | WalkResult::PageTableMissing =3D= > Ok(None), + } + } +} --=20 2.34.1 From nobody Mon May 25 04:34:26 2026 Received: from CH1PR05CU001.outbound.protection.outlook.com (mail-northcentralusazon11010011.outbound.protection.outlook.com [52.101.193.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF5F639022C; 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charset="utf-8" Add virtual address range tracking to the VMM using a maple tree allocator. This enables contiguous virtual address range allocation for mappings. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm/vmm.rs | 83 +++++++++++++++++++++++++++++---- 1 file changed, 74 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/nova-core/mm/vmm.rs b/drivers/gpu/nova-core/mm/vmm= .rs index 3e18adc23b68..05ff77c5f888 100644 --- a/drivers/gpu/nova-core/mm/vmm.rs +++ b/drivers/gpu/nova-core/mm/vmm.rs @@ -9,18 +9,27 @@ use kernel::{ device, gpu::buddy::AllocatedBlocks, + maple_tree::MapleTreeAlloc, prelude::*, // }; =20 -use crate::mm::{ - pagetable::{ - walk::{PtWalk, WalkResult}, - MmuVersion, // +use core::ops::Range; + +use crate::{ + mm::{ + pagetable::{ + walk::{PtWalk, WalkResult}, + MmuVersion, // + }, + GpuMm, + Pfn, + Vfn, + VramAddress, + PAGE_SIZE, // + }, + num::{ + IntoSafeCast, // }, - GpuMm, - Pfn, - Vfn, - VramAddress, // }; =20 /// Virtual Memory Manager for a GPU address space. @@ -35,18 +44,74 @@ pub(crate) struct Vmm { mmu_version: MmuVersion, /// Page table allocations required for mappings. page_table_allocs: KVec>>, + /// Maple tree allocator for virtual address range tracking. + virt_alloc: Pin>>, + /// Total number of pages in the virtual address space. + va_pages: usize, } =20 impl Vmm { /// Create a new [`Vmm`] for the given Page Directory Base address. - pub(crate) fn new(pdb_addr: VramAddress, mmu_version: MmuVersion) -> R= esult { + /// + /// The [`Vmm`] will manage a virtual address space of `va_size` bytes. + pub(crate) fn new( + pdb_addr: VramAddress, + mmu_version: MmuVersion, + va_size: u64, + ) -> Result { + let page_size: u64 =3D PAGE_SIZE.into_safe_cast(); + let va_pages: usize =3D (va_size / page_size).into_safe_cast(); + let virt_alloc =3D KBox::pin_init(MapleTreeAlloc::<()>::new(), GFP= _KERNEL)?; + Ok(Self { pdb_addr, mmu_version, page_table_allocs: KVec::new(), + virt_alloc, + va_pages, }) } =20 + /// Allocate a contiguous virtual frame number range. + /// + /// # Arguments + /// + /// - `num_pages`: Number of pages to allocate. + /// - `va_range`: `None` =3D allocate anywhere, `Some(range)` =3D cons= train allocation to the given + /// range. + fn alloc_vfn_range(&self, num_pages: usize, va_range: Option>) -> Result { + let page_size: u64 =3D PAGE_SIZE.into_safe_cast(); + + let start_vfn =3D match va_range { + Some(r) =3D> { + let num_pages_u64: u64 =3D num_pages.into_safe_cast(); + let size =3D num_pages_u64.checked_mul(page_size).ok_or(EO= VERFLOW)?; + let range_size =3D r.end.checked_sub(r.start).ok_or(EOVERF= LOW)?; + if range_size !=3D size { + return Err(EINVAL); + } + let start_vfn: usize =3D (r.start / page_size).into_safe_c= ast(); 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charset="utf-8" Add the page table mapping and unmapping API to the Virtual Memory Manager, implementing a two-phase prepare/execute model suitable for use both inside and outside the DMA fence signalling critical path. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm/pagetable.rs | 1 + drivers/gpu/nova-core/mm/pagetable/map.rs | 367 ++++++++++++++++++++++ drivers/gpu/nova-core/mm/vmm.rs | 270 ++++++++++++++-- 3 files changed, 619 insertions(+), 19 deletions(-) create mode 100644 drivers/gpu/nova-core/mm/pagetable/map.rs diff --git a/drivers/gpu/nova-core/mm/pagetable.rs b/drivers/gpu/nova-core/= mm/pagetable.rs index 5e192679f27c..042584e5178b 100644 --- a/drivers/gpu/nova-core/mm/pagetable.rs +++ b/drivers/gpu/nova-core/mm/pagetable.rs @@ -8,6 +8,7 @@ =20 #![expect(dead_code)] =20 +pub(super) mod map; pub(super) mod ver2; pub(super) mod ver3; pub(super) mod walk; diff --git a/drivers/gpu/nova-core/mm/pagetable/map.rs b/drivers/gpu/nova-c= ore/mm/pagetable/map.rs new file mode 100644 index 000000000000..b0678a36d406 --- /dev/null +++ b/drivers/gpu/nova-core/mm/pagetable/map.rs @@ -0,0 +1,367 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Page table mapping operations for NVIDIA GPUs. + +use core::marker::PhantomData; + +use kernel::{ + device, + gpu::buddy::{ + AllocatedBlocks, + GpuBuddyAllocFlags, + GpuBuddyAllocMode, // + }, + prelude::*, + ptr::Alignment, + rbtree::{RBTree, RBTreeNode}, + sizes::SZ_4K, // +}; + +use super::{ + walk::{ + PtWalkInner, + WalkPdeResult, + WalkResult, // + }, + AperturePde, + AperturePte, + DualPdeOps, + MmuConfig, + MmuV2, + MmuV3, + MmuVersion, + PageTableLevel, + PdeOps, + PteOps, // +}; +use crate::{ + mm::{ + GpuMm, + Pfn, + Vfn, + VramAddress, + PAGE_SIZE, // + }, + num::{ + IntoSafeCast, // + }, +}; + +/// A pre-allocated and zeroed page table page. +/// +/// Created during the mapping prepare phase and consumed during the execu= te phase. +/// Stored in an [`RBTree`] keyed by the PDE slot address (`install_addr`). +pub(in crate::mm) struct PreparedPtPage { + /// The allocated and zeroed page table page. + pub(in crate::mm) alloc: Pin>, + /// Page table level -- needed to determine if this PT page is for a d= ual PDE. + pub(in crate::mm) level: PageTableLevel, +} + +/// Page table mapper. +pub(in crate::mm) struct PtMapInner { + walker: PtWalkInner, + pdb_addr: VramAddress, + _phantom: PhantomData, +} + +impl PtMapInner { + /// Create a new [`PtMapInner`]. + pub(super) fn new(pdb_addr: VramAddress) -> Self { + Self { + walker: PtWalkInner::::new(pdb_addr), + pdb_addr, + _phantom: PhantomData, + } + } + + /// Allocate and zero a physical page table page. + fn alloc_and_zero_page( + dev: &device::Device, + mm: &GpuMm, + level: PageTableLevel, + ) -> Result { + let blocks =3D KBox::pin_init( + mm.buddy().alloc_blocks( + GpuBuddyAllocMode::Simple, + SZ_4K.into_safe_cast(), + Alignment::new::(), + GpuBuddyAllocFlags::default(), + ), + GFP_KERNEL, + )?; + + let page_vram =3D VramAddress::new(blocks.iter().next().ok_or(ENOM= EM)?.offset()); + + // Zero via PRAMIN. + let mut window =3D mm.pramin().get_window(dev)?; + for off in (0..PAGE_SIZE).step_by(8) { + let off_u64: u64 =3D off.into_safe_cast(); + window.try_write64(page_vram + off_u64, 0)?; + } + + Ok(PreparedPtPage { + alloc: blocks, + level, + }) + } + + /// Ensure all intermediate page table pages exist for a single VFN. + /// + /// PRAMIN is released before each allocation and re-acquired after. M= emory + /// allocations are done outside of holding this lock to prevent deadl= ocks with + /// the fence signalling critical path. + fn ensure_single_pte_path( + &self, + dev: &device::Device, + mm: &GpuMm, + vfn: Vfn, + pt_pages: &mut RBTree, + ) -> Result { + let max_iter =3D 2 * M::PDE_LEVELS.len(); + + for _ in 0..max_iter { + let mut window =3D mm.pramin().get_window(dev)?; + + let result =3D self + .walker + .walk_pde_levels(&mut window, vfn, |install_addr| { + pt_pages + .get(&install_addr) + .and_then(|p| p.alloc.iter().next().map(|b| VramAd= dress::new(b.offset()))) + })?; + + match result { + WalkPdeResult::Complete { .. } =3D> { + return Ok(()); + } + WalkPdeResult::Missing { + install_addr, + level, + } =3D> { + // Drop PRAMIN before allocation. + drop(window); + let page =3D Self::alloc_and_zero_page(dev, mm, level)= ?; + let node =3D RBTreeNode::new(install_addr, page, GFP_K= ERNEL)?; + let old =3D pt_pages.insert(node); + if old.is_some() { + kernel::pr_warn_once!( + "VMM: duplicate install_addr in pt_pages (inte= rnal consistency error)\n" + ); + return Err(EIO); + } + } + } + } + + kernel::pr_warn!( + "VMM: ensure_pte_path: loop exhausted after {} iters (VFN {:?}= )\n", + max_iter, + vfn + ); + Err(EIO) + } + + /// Prepare page table resources for mapping `num_pages` pages startin= g at `vfn_start`. + /// + /// Reserves capacity in `page_table_allocs`, then walks the hierarchy + /// per-VFN to prepare pages for all missing PDEs. + pub(super) fn prepare_map( + &self, + dev: &device::Device, + mm: &GpuMm, + vfn_start: Vfn, + num_pages: usize, + page_table_allocs: &mut KVec>>, + pt_pages: &mut RBTree, + ) -> Result { + // Pre-reserve so install_mappings() can use push_within_capacity = (no alloc + // in fence signalling critical path). + let pt_upper_bound =3D M::pt_pages_upper_bound(num_pages); + page_table_allocs.reserve(pt_upper_bound, GFP_KERNEL)?; + + // Walk the hierarchy per-VFN to prepare pages for all missing PDE= s. + for i in 0..num_pages { + let i_u64: u64 =3D i.into_safe_cast(); + let vfn =3D Vfn::new(vfn_start.raw() + i_u64); + self.ensure_single_pte_path(dev, mm, vfn, pt_pages)?; + } + Ok(()) + } + + /// Install prepared PDEs and write PTEs, then flush TLB. + /// + /// Drains `pt_pages` and moves allocations into `page_table_allocs`. + #[expect(clippy::too_many_arguments)] + pub(super) fn install_mappings( + &self, + dev: &device::Device, + mm: &GpuMm, + pt_pages: &mut RBTree, + page_table_allocs: &mut KVec>>, + vfn_start: Vfn, + pfns: &[Pfn], + writable: bool, + ) -> Result { + let mut window =3D mm.pramin().get_window(dev)?; + + // Drain prepared PT pages, install all pending PDEs. + let mut cursor =3D pt_pages.cursor_front_mut(); + while let Some(c) =3D cursor { + let (next, node) =3D c.remove_current(); + let (install_addr, page) =3D node.to_key_value(); + let page_vram =3D VramAddress::new(page.alloc.iter().next().ok= _or(ENOMEM)?.offset()); + + if page.level =3D=3D M::DUAL_PDE_LEVEL { + let new_dpde =3D M::DualPde::new_small(Pfn::from(page_vram= )); + new_dpde.write(&mut window, install_addr)?; + } else { + let new_pde =3D M::Pde::new(AperturePde::VideoMemory, Pfn:= :from(page_vram)); + new_pde.write(&mut window, install_addr)?; + } + + page_table_allocs + .push_within_capacity(page.alloc) + .map_err(|_| ENOMEM)?; + + cursor =3D next; + } + + // Write PTEs (all PDEs now installed in HW). + for (i, &pfn) in pfns.iter().enumerate() { + let i_u64: u64 =3D i.into_safe_cast(); + let vfn =3D Vfn::new(vfn_start.raw() + i_u64); + let result =3D self + .walker + .walk_to_pte_lookup_with_window(&mut window, vfn)?; + + match result { + WalkResult::Unmapped { pte_addr } | WalkResult::Mapped { p= te_addr, .. } =3D> { + let pte =3D M::Pte::new(AperturePte::VideoMemory, pfn,= writable); + pte.write(&mut window, pte_addr)?; + } + WalkResult::PageTableMissing =3D> { + kernel::pr_warn_once!("VMM: page table missing for VFN= {vfn:?}\n"); + return Err(EIO); + } + } + } + + drop(window); + + // Flush TLB. + mm.tlb().flush(dev, self.pdb_addr) + } + + /// Invalidate PTEs for a range and flush TLB. + pub(super) fn invalidate_ptes( + &self, + dev: &device::Device, + mm: &GpuMm, + vfn_start: Vfn, + num_pages: usize, + ) -> Result { + let invalid_pte =3D M::Pte::invalid(); + + let mut window =3D mm.pramin().get_window(dev)?; + for i in 0..num_pages { + let i_u64: u64 =3D i.into_safe_cast(); + let vfn =3D Vfn::new(vfn_start.raw() + i_u64); + let result =3D self + .walker + .walk_to_pte_lookup_with_window(&mut window, vfn)?; + + match result { + WalkResult::Mapped { pte_addr, .. } | WalkResult::Unmapped= { pte_addr } =3D> { + invalid_pte.write(&mut window, pte_addr)?; + } + WalkResult::PageTableMissing =3D> { + continue; + } + } + } + drop(window); + + mm.tlb().flush(dev, self.pdb_addr) + } +} + +macro_rules! pt_map_dispatch { + ($self:expr, $method:ident ( $($arg:expr),* $(,)? )) =3D> { + match $self { + PtMap::V2(inner) =3D> inner.$method($($arg),*), + PtMap::V3(inner) =3D> inner.$method($($arg),*), + } + }; +} + +/// Page table mapper dispatch. +pub(in crate::mm) enum PtMap { + /// MMU v2 (Turing/Ampere/Ada). + V2(PtMapInner), + /// MMU v3 (Hopper+). + V3(PtMapInner), +} + +impl PtMap { + /// Create a new page table mapper for the given MMU version. + pub(in crate::mm) fn new(pdb_addr: VramAddress, version: MmuVersion) -= > Self { + match version { + MmuVersion::V2 =3D> Self::V2(PtMapInner::::new(pdb_addr= )), + MmuVersion::V3 =3D> Self::V3(PtMapInner::::new(pdb_addr= )), + } + } + + /// Prepare page table resources for a mapping. + pub(in crate::mm) fn prepare_map( + &self, + dev: &device::Device, + mm: &GpuMm, + vfn_start: Vfn, + num_pages: usize, + page_table_allocs: &mut KVec>>, + pt_pages: &mut RBTree, + ) -> Result { + pt_map_dispatch!( + self, + prepare_map(dev, mm, vfn_start, num_pages, page_table_allocs, = pt_pages) + ) + } + + /// Install prepared PDEs and write PTEs, then flush TLB. + #[expect(clippy::too_many_arguments)] + pub(in crate::mm) fn install_mappings( + &self, + dev: &device::Device, + mm: &GpuMm, + pt_pages: &mut RBTree, + page_table_allocs: &mut KVec>>, + vfn_start: Vfn, + pfns: &[Pfn], + writable: bool, + ) -> Result { + pt_map_dispatch!( + self, + install_mappings( + dev, + mm, + pt_pages, + page_table_allocs, + vfn_start, + pfns, + writable + ) + ) + } + + /// Invalidate PTEs for a range and flush TLB. + pub(in crate::mm) fn invalidate_ptes( + &self, + dev: &device::Device, + mm: &GpuMm, + vfn_start: Vfn, + num_pages: usize, + ) -> Result { + pt_map_dispatch!(self, invalidate_ptes(dev, mm, vfn_start, num_pag= es)) + } +} diff --git a/drivers/gpu/nova-core/mm/vmm.rs b/drivers/gpu/nova-core/mm/vmm= .rs index 05ff77c5f888..1cceea759f6a 100644 --- a/drivers/gpu/nova-core/mm/vmm.rs +++ b/drivers/gpu/nova-core/mm/vmm.rs @@ -3,22 +3,31 @@ //! Virtual Memory Manager for NVIDIA GPU page table management. //! //! The [`Vmm`] provides high-level page mapping and unmapping operations = for GPU -//! virtual address spaces (Channels, BAR1, BAR2). It wraps the page table= walker -//! and handles TLB flushing after modifications. +//! virtual address spaces (Channels, BAR1, BAR2). =20 use kernel::{ device, gpu::buddy::AllocatedBlocks, maple_tree::MapleTreeAlloc, - prelude::*, // + prelude::*, + rbtree::RBTree, // }; =20 -use core::ops::Range; +use core::{ + cell::Cell, + ops::Range, // +}; =20 use crate::{ mm::{ pagetable::{ - walk::{PtWalk, WalkResult}, + map::{ + PtMap, // + }, + walk::{ + PtWalk, + WalkResult, // + }, MmuVersion, // }, GpuMm, @@ -32,22 +41,108 @@ }, }; =20 +/// Multi-page prepared mapping -- VA range allocated, ready for execute. +/// +/// Produced by [`Vmm::prepare_map()`], consumed by [`Vmm::execute_map()`]. +/// The VA space allocation is tracked in the [`Vmm`]'s maple tree and fre= ed +/// on error or via [`Vmm::unmap_pages()`]. +/// +/// Dropping without calling [`Vmm::execute_map()`] logs a warning and lea= ks +/// the VA range in the maple tree. +pub(crate) struct PreparedMapping { + vfn_start: Vfn, + num_pages: usize, + /// Logs a warning if dropped without executing. + _drop_guard: MustExecuteGuard, +} + +/// Result of a mapping operation -- tracks the active mapped range. +/// +/// Returned by [`Vmm::execute_map()`] and [`Vmm::map_pages()`]. +/// Callers must call [`Vmm::unmap_pages()`] before dropping to invalidate +/// PTEs and free the VA range. Dropping without unmapping logs a warning +/// and leaks the VA range in the maple tree. +pub(crate) struct MappedRange { + pub(super) vfn_start: Vfn, + pub(super) num_pages: usize, + /// Logs a warning if dropped without unmapping. + _drop_guard: MustUnmapGuard, +} + +/// Guard that logs a warning if a [`PreparedMapping`] is dropped without +/// being consumed by [`Vmm::execute_map()`]. +struct MustExecuteGuard { + armed: Cell, +} + +impl MustExecuteGuard { + const fn new() -> Self { + Self { + armed: Cell::new(true), + } + } + + fn disarm(&self) { + self.armed.set(false); + } +} + +impl Drop for MustExecuteGuard { + fn drop(&mut self) { + if self.armed.get() { + kernel::pr_warn!("PreparedMapping dropped without calling exec= ute_map()\n"); + } + } +} + +/// Guard that logs a warning if a [`MappedRange`] is dropped without +/// calling [`Vmm::unmap_pages()`]. +struct MustUnmapGuard { + armed: Cell, +} + +impl MustUnmapGuard { + const fn new() -> Self { + Self { + armed: Cell::new(true), + } + } + + fn disarm(&self) { + self.armed.set(false); + } +} + +impl Drop for MustUnmapGuard { + fn drop(&mut self) { + if self.armed.get() { + kernel::pr_warn!("MappedRange dropped without calling unmap_pa= ges()\n"); + } + } +} + /// Virtual Memory Manager for a GPU address space. /// /// Each [`Vmm`] instance manages a single address space identified by its= Page -/// Directory Base (`PDB`) address. The [`Vmm`] is used for Channel, BAR1 = and -/// BAR2 mappings. +/// Directory Base (`PDB`) address. Used for Channel, BAR1 and BAR2 mappin= gs. pub(crate) struct Vmm { /// Page Directory Base address for this address space. pdb_addr: VramAddress, - /// MMU version used for page table layout. - mmu_version: MmuVersion, + /// Page table walker for reading existing mappings. + pt_walk: PtWalk, + /// Page table mapper for prepare/execute operations. + pt_map: PtMap, /// Page table allocations required for mappings. page_table_allocs: KVec>>, /// Maple tree allocator for virtual address range tracking. virt_alloc: Pin>>, /// Total number of pages in the virtual address space. va_pages: usize, + /// Prepared PT pages pending PDE installation, keyed by `install_addr= `. + /// + /// Populated during prepare phase and drained in execute phase. Share= d by all + /// pending maps, preventing races on the same PDE slot. + pt_pages: RBTree, } =20 impl Vmm { @@ -65,20 +160,16 @@ pub(crate) fn new( =20 Ok(Self { pdb_addr, - mmu_version, + pt_walk: PtWalk::new(pdb_addr, mmu_version), + pt_map: PtMap::new(pdb_addr, mmu_version), page_table_allocs: KVec::new(), virt_alloc, va_pages, + pt_pages: RBTree::new(), }) } =20 /// Allocate a contiguous virtual frame number range. - /// - /// # Arguments - /// - /// - `num_pages`: Number of pages to allocate. - /// - `va_range`: `None` =3D allocate anywhere, `Some(range)` =3D cons= train allocation to the given - /// range. fn alloc_vfn_range(&self, num_pages: usize, va_range: Option>) -> Result { let page_size: u64 =3D PAGE_SIZE.into_safe_cast(); =20 @@ -119,11 +210,152 @@ pub(super) fn read_mapping( mm: &GpuMm, vfn: Vfn, ) -> Result> { - let walker =3D PtWalk::new(self.pdb_addr, self.mmu_version); - - match walker.walk_to_pte(dev, mm, vfn)? { + match self.pt_walk.walk_to_pte(dev, mm, vfn)? { WalkResult::Mapped { pfn, .. } =3D> Ok(Some(pfn)), WalkResult::Unmapped { .. } | WalkResult::PageTableMissing =3D= > Ok(None), } } + + /// Prepare resources for mapping `num_pages` pages. + /// + /// Allocates a contiguous VA range, then walks the hierarchy per-VFN = to prepare pages + /// for all missing PDEs. Returns a [`PreparedMapping`] with the VA al= location. + /// + /// If `va_range` is not `None`, the VA range is constrained to the gi= ven range. Safe + /// to call outside the fence signalling critical path. + pub(crate) fn prepare_map( + &mut self, + dev: &device::Device, + mm: &GpuMm, + num_pages: usize, + va_range: Option>, + ) -> Result { + if num_pages =3D=3D 0 { + return Err(EINVAL); + } + + // Allocate contiguous VA range. + let vfn_start =3D self.alloc_vfn_range(num_pages, va_range)?; + + if let Err(e) =3D self.pt_map.prepare_map( + dev, + mm, + vfn_start, + num_pages, + &mut self.page_table_allocs, + &mut self.pt_pages, + ) { + self.free_vfn(vfn_start); + return Err(e); + } + + Ok(PreparedMapping { + vfn_start, + num_pages, + _drop_guard: MustExecuteGuard::new(), + }) + } + + /// Execute a prepared multi-page mapping. + /// + /// Installs all prepared PDEs and writes PTEs into the page table, th= en flushes TLB. + pub(crate) fn execute_map( + &mut self, + dev: &device::Device, + mm: &GpuMm, + prepared: PreparedMapping, + pfns: &[Pfn], + writable: bool, + ) -> Result { + if pfns.len() !=3D prepared.num_pages { + self.free_vfn(prepared.vfn_start); + return Err(EINVAL); + } + + let PreparedMapping { + vfn_start, + num_pages, + _drop_guard, + } =3D prepared; + _drop_guard.disarm(); + + if let Err(e) =3D self.pt_map.install_mappings( + dev, + mm, + &mut self.pt_pages, + &mut self.page_table_allocs, + vfn_start, + pfns, + writable, + ) { + self.free_vfn(vfn_start); + return Err(e); + } + + Ok(MappedRange { + vfn_start, + num_pages, + _drop_guard: MustUnmapGuard::new(), + }) + } + + /// Map pages doing prepare and execute in the same call. + /// + /// This is a convenience wrapper for callers outside the fence signal= ling critical + /// path (e.g., BAR mappings). For DRM usecases, [`Vmm::prepare_map()`= ] and + /// [`Vmm::execute_map()`] will be called separately. + pub(crate) fn map_pages( + &mut self, + dev: &device::Device, + mm: &GpuMm, + pfns: &[Pfn], + va_range: Option>, + writable: bool, + ) -> Result { + if pfns.is_empty() { + return Err(EINVAL); + } + + // Check if provided VA range is sufficient (if provided). + if let Some(ref range) =3D va_range { + let required: u64 =3D pfns + .len() + .checked_mul(PAGE_SIZE) + .ok_or(EOVERFLOW)? + .into_safe_cast(); + let available =3D range.end.checked_sub(range.start).ok_or(EIN= VAL)?; + if available < required { + return Err(EINVAL); + } + } + + let prepared =3D self.prepare_map(dev, mm, pfns.len(), va_range)?; + self.execute_map(dev, mm, prepared, pfns, writable) + } + + /// Unmap all pages in a [`MappedRange`] with a single TLB flush. + pub(crate) fn unmap_pages( + &mut self, + dev: &device::Device, + mm: &GpuMm, + range: MappedRange, + ) -> Result { + let result =3D self + .pt_map + .invalidate_ptes(dev, mm, range.vfn_start, range.num_pages); + + // TODO: Internal page table pages (PDE, PTE pages) are still kept= around. + // This is by design as repeated maps/unmaps will be fast. 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Mon, 18 May 2026 18:11:53 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%6]) with mapi id 15.21.0025.012; Mon, 18 May 2026 18:11:53 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Miguel Ojeda , Boqun Feng , Gary Guo , Bjorn Roy Baron , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Dave Airlie , Daniel Almeida , dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, nova-gpu@lists.linux.dev, Nikola Djukic , David Airlie , Boqun Feng , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Balbir Singh , Philipp Stanner , alexeyi@nvidia.com, Eliot Courtney , joel@joelfernandes.org, linux-doc@vger.kernel.org, Joel Fernandes Subject: [PATCH v1 14/16] gpu: nova-core: Add BAR1 aperture type and size constant Date: Mon, 18 May 2026 14:11:23 -0400 Message-Id: <20260518181126.2493572-15-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260518181126.2493572-1-joelagnelf@nvidia.com> References: <20260518181126.2493572-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MN2PR08CA0008.namprd08.prod.outlook.com (2603:10b6:208:239::13) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|CH3PR12MB8727:EE_ X-MS-Office365-Filtering-Correlation-Id: 29722ee5-4a47-4ced-559e-08deb508ef7a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|1800799024|11063799003|22082099003|56012099003|18002099003|3023799003; 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charset="utf-8" Add BAR1_SIZE constant and Bar1 type alias for the 256MB BAR1 aperture. These are prerequisites for BAR1 memory access functionality. Co-developed-by: Zhi Wang Signed-off-by: Zhi Wang Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/driver.rs | 2 ++ drivers/gpu/nova-core/gsp/commands.rs | 4 ++++ drivers/gpu/nova-core/gsp/fw/commands.rs | 8 ++++++++ 3 files changed, 14 insertions(+) diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver= .rs index 77746d6949d7..b14d4b599783 100644 --- a/drivers/gpu/nova-core/driver.rs +++ b/drivers/gpu/nova-core/driver.rs @@ -47,6 +47,8 @@ pub(crate) struct NovaCore { const GPU_DMA_BITS: u32 =3D 47; =20 pub(crate) type Bar0 =3D pci::Bar; +#[expect(dead_code)] +pub(crate) type Bar1 =3D pci::Bar; =20 kernel::pci_device_table!( PCI_TABLE, diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/= gsp/commands.rs index 5abd7950320b..bee7539eff60 100644 --- a/drivers/gpu/nova-core/gsp/commands.rs +++ b/drivers/gpu/nova-core/gsp/commands.rs @@ -193,6 +193,9 @@ fn init(&self) -> impl Init { /// The reply from the GSP to the [`GetGspStaticInfo`] command. pub(crate) struct GetGspStaticInfoReply { gpu_name: [u8; 64], + /// BAR1 Page Directory Entry base address. + #[expect(dead_code)] + pub(crate) bar1_pde_base: u64, /// Usable FB (VRAM) region for driver memory allocation. pub(crate) usable_fb_region: Range, /// End of VRAM. @@ -212,6 +215,7 @@ fn read( =20 Ok(GetGspStaticInfoReply { gpu_name: msg.gpu_name_str(), + bar1_pde_base: msg.bar1_pde_base(), usable_fb_region: msg.usable_fb_regions_iter().next().ok_or(EN= ODEV)?, total_fb_end, }) diff --git a/drivers/gpu/nova-core/gsp/fw/commands.rs b/drivers/gpu/nova-co= re/gsp/fw/commands.rs index ea663079d95c..13418b494a73 100644 --- a/drivers/gpu/nova-core/gsp/fw/commands.rs +++ b/drivers/gpu/nova-core/gsp/fw/commands.rs @@ -127,6 +127,14 @@ impl GspStaticConfigInfo { self.0.gpuNameString } =20 + /// Returns the BAR1 Page Directory Entry base address. + /// + /// This is the root page table address for BAR1 virtual memory, + /// set up by GSP-RM firmware. + pub(crate) fn bar1_pde_base(&self) -> u64 { + self.0.bar1PdeBase + } + /// Returns an iterator over valid FB regions from GSP firmware data. fn fb_regions( &self, --=20 2.34.1 From nobody Mon May 25 04:34:26 2026 Received: from DM1PR04CU001.outbound.protection.outlook.com (mail-centralusazon11010011.outbound.protection.outlook.com [52.101.61.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB3CA38A29A; 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Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by CH3PR12MB8727.namprd12.prod.outlook.com (2603:10b6:610:173::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.23; Mon, 18 May 2026 18:11:54 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%6]) with mapi id 15.21.0025.012; Mon, 18 May 2026 18:11:54 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Miguel Ojeda , Boqun Feng , Gary Guo , Bjorn Roy Baron , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Dave Airlie , Daniel Almeida , dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, nova-gpu@lists.linux.dev, Nikola Djukic , David Airlie , Boqun Feng , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Balbir Singh , Philipp Stanner , alexeyi@nvidia.com, Eliot Courtney , joel@joelfernandes.org, linux-doc@vger.kernel.org, Joel Fernandes Subject: [PATCH v1 15/16] gpu: nova-core: mm: Add BAR1 user interface Date: Mon, 18 May 2026 14:11:24 -0400 Message-Id: <20260518181126.2493572-16-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260518181126.2493572-1-joelagnelf@nvidia.com> References: <20260518181126.2493572-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BL1PR13CA0322.namprd13.prod.outlook.com (2603:10b6:208:2c1::27) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|CH3PR12MB8727:EE_ X-MS-Office365-Filtering-Correlation-Id: 6177a3c8-3037-4ead-1436-08deb508f034 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|1800799024|11063799003|22082099003|56012099003|18002099003|3023799003; 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charset="utf-8" Add the BAR1 user interface for CPU access to GPU virtual memory through the BAR1 aperture. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/driver.rs | 22 ++- drivers/gpu/nova-core/gpu.rs | 41 +++++- drivers/gpu/nova-core/gsp/commands.rs | 1 - drivers/gpu/nova-core/mm.rs | 1 + drivers/gpu/nova-core/mm/bar_user.rs | 194 ++++++++++++++++++++++++++ 5 files changed, 255 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/nova-core/mm/bar_user.rs diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver= .rs index b14d4b599783..207ba164cf4e 100644 --- a/drivers/gpu/nova-core/driver.rs +++ b/drivers/gpu/nova-core/driver.rs @@ -2,10 +2,12 @@ =20 use kernel::{ auxiliary, + device::Bound, device::Core, devres::Devres, dma::Device, dma::DmaMask, + io::resource, pci, pci::{ Class, @@ -47,9 +49,27 @@ pub(crate) struct NovaCore { const GPU_DMA_BITS: u32 =3D 47; =20 pub(crate) type Bar0 =3D pci::Bar; -#[expect(dead_code)] pub(crate) type Bar1 =3D pci::Bar; =20 +/// Returns the Linux PCI resource index that holds BAR1 for an NVIDIA GPU. +/// +/// On Maxwell through Ada, BAR0 is a 32-bit memory BAR occupying a single +/// Linux PCI resource slot, so BAR1 lives at index 1. Starting with Black= well +/// (and on some Ampere GA100 / Hopper SKUs) BAR0 is a 64-bit memory BAR t= hat +/// consumes two consecutive resource slots: index 0 holds the low 32 bits= and +/// index 1 holds the high 32 bits (with no `flags` / or size of its own), +/// shifting BAR1 to index 2. +pub(crate) fn bar1_resource_index(pdev: &pci::Device) -> Result { + // Probe the `IORESOURCE_MEM_64` flag of BAR0 as a robust way of expos= ing + // if BAR0 and hence BAR1 is 64-bit. + let flags0 =3D pdev.resource_flags(0)?; + if flags0.contains(resource::Flags::IORESOURCE_MEM_64) { + Ok(2) + } else { + Ok(1) + } +} + kernel::pci_device_table!( PCI_TABLE, MODULE_PCI_TABLE, diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index f789d956cc49..b0eebe6406e5 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -19,7 +19,10 @@ =20 use crate::{ bounded_enum, - driver::Bar0, + driver::{ + Bar0, + Bar1, // + }, falcon::{ gsp::Gsp as GspFalcon, sec2::Sec2 as Sec2Falcon, @@ -31,8 +34,11 @@ Gsp, // }, mm::{ + bar_user::BarUser, + pagetable::MmuVersion, GpuMm, - IntoVramRange, // + IntoVramRange, + VramAddress, // }, regs, }; @@ -145,6 +151,11 @@ pub(crate) const fn arch(self) -> Architecture { pub(crate) const fn needs_fwsec_bootloader(self) -> bool { matches!(self.arch(), Architecture::Turing) || matches!(self, Self= ::GA100) } + + /// Returns the MMU version for this chipset. + pub(crate) fn mmu_version(self) -> MmuVersion { + MmuVersion::from(self.arch()) + } } =20 // TODO @@ -263,6 +274,8 @@ pub(crate) struct Gpu { spec: Spec, /// MMIO mapping of PCI BAR 0 bar: Arc>, + /// MMIO mapping of PCI BAR 1. + bar1: Arc>, /// System memory page required for flushing all pending GPU-side memo= ry writes done through /// PCIE into system memory, via sysmembar (A GPU-initiated HW memory-= barrier operation). sysmem_flush: SysmemFlush, @@ -276,6 +289,8 @@ pub(crate) struct Gpu { #[pin] gsp: Gsp, gsp_static_info: GetGspStaticInfoReply, + /// BAR1 user interface for CPU access to GPU virtual memory. + bar_user: Arc, } =20 impl Gpu { @@ -348,6 +363,28 @@ pub(crate) fn new<'a>( )? }, =20 + bar1: { + let bar1_idx =3D crate::driver::bar1_resource_index(pdev)?; + Arc::pin_init(pdev.iomap_region(bar1_idx, c"nova-core/bar1= "), GFP_KERNEL)? + }, + + // Create BAR1 user interface for CPU access to GPU virtual me= mory. + bar_user: { + let pdb_addr =3D VramAddress::new(gsp_static_info.bar1_pde= _base); + let bar1_idx =3D crate::driver::bar1_resource_index(pdev)?; + let bar1_size =3D pdev.resource_len(bar1_idx)?; + Arc::pin_init( + BarUser::new( + pdb_addr, + spec.chipset, + bar1_size, + mm.clone(), + bar1.clone(), + )?, + GFP_KERNEL, + )? + }, + bar: devres_bar, }) } diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/= gsp/commands.rs index bee7539eff60..301c95686efd 100644 --- a/drivers/gpu/nova-core/gsp/commands.rs +++ b/drivers/gpu/nova-core/gsp/commands.rs @@ -194,7 +194,6 @@ fn init(&self) -> impl Init { pub(crate) struct GetGspStaticInfoReply { gpu_name: [u8; 64], /// BAR1 Page Directory Entry base address. - #[expect(dead_code)] pub(crate) bar1_pde_base: u64, /// Usable FB (VRAM) region for driver memory allocation. pub(crate) usable_fb_region: Range, diff --git a/drivers/gpu/nova-core/mm.rs b/drivers/gpu/nova-core/mm.rs index 502c7fdceba2..4741ef60593b 100644 --- a/drivers/gpu/nova-core/mm.rs +++ b/drivers/gpu/nova-core/mm.rs @@ -31,6 +31,7 @@ macro_rules! impl_pfn_bounded { }; } =20 +pub(crate) mod bar_user; pub(super) mod pagetable; pub(crate) mod pramin; pub(super) mod tlb; diff --git a/drivers/gpu/nova-core/mm/bar_user.rs b/drivers/gpu/nova-core/m= m/bar_user.rs new file mode 100644 index 000000000000..bb9742c036b7 --- /dev/null +++ b/drivers/gpu/nova-core/mm/bar_user.rs @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! BAR1 user interface for CPU access to GPU virtual memory. Used for USE= RD +//! for GPU work submission, and applications to access GPU buffers via mm= ap(). + +use kernel::{ + device, + devres::Devres, + io::Io, + new_mutex, + prelude::*, + sync::{ + Arc, + Mutex, // + }, +}; + +use crate::{ + driver::Bar1, + gpu::Chipset, + mm::{ + vmm::{ + MappedRange, + Vmm, // + }, + GpuMm, + Pfn, + Vfn, + VirtualAddress, + VramAddress, + PAGE_SIZE, // + }, + num::IntoSafeCast, +}; + +/// BAR1 user interface for virtual memory mappings. +/// +/// Owns the [`Vmm`] for the BAR1 address space. +#[pin_data] +pub(crate) struct BarUser { + #[pin] + vmm: Mutex, + mm: Arc, + bar1: Arc>, +} + +impl BarUser { + /// Create a pin-initializer for [`BarUser`]. + pub(crate) fn new( + pdb_addr: VramAddress, + chipset: Chipset, + va_size: u64, + mm: Arc, + bar1: Arc>, + ) -> Result> { + let vmm =3D Vmm::new(pdb_addr, chipset.mmu_version(), va_size)?; + Ok(pin_init!(Self { + vmm <- new_mutex!(vmm, "bar_user_vmm"), + mm, + bar1, + })) + } + + /// Map physical pages to a contiguous BAR1 virtual range. + pub(crate) fn map( + self: &Arc, + dev: &device::Device, + pfns: &[Pfn], + writable: bool, + ) -> Result { + if pfns.is_empty() { + return Err(EINVAL); + } + let mut vmm =3D self.vmm.lock(); + let mapped =3D vmm.map_pages(dev, &self.mm, pfns, None, writable)?; + + Ok(BarUserAccess { + bar_user: self.clone(), + mapped: Some(mapped), + }) + } +} + +/// Access object for a mapped BAR1 region. +pub(crate) struct BarUserAccess { + bar_user: Arc, + /// [`BarUserAccess::release`] [`Option::take`]s this; `Some` at + /// drop time means `release()` was never called. + mapped: Option, +} + +impl BarUserAccess { + /// Tear down the BAR1 mapping using a caller-supplied bound device. + pub(crate) fn release(mut self, dev: &device::Device) -= > Result { + let mapped =3D self.mapped.take().ok_or(EINVAL)?; + let mut vmm =3D self.bar_user.vmm.lock(); + vmm.unmap_pages(dev, &self.bar_user.mm, mapped)?; + Ok(()) + } + + /// Returns the active mapping. + fn mapped(&self) -> &MappedRange { + // `mapped` is only `None` after `take()` in `release`; hence unwr= ap() + // cannot panic here. + self.mapped.as_ref().unwrap() + } + + /// Get the base virtual address of this mapping. + pub(crate) fn base(&self) -> VirtualAddress { + VirtualAddress::from(self.mapped().vfn_start) + } + + /// Get the total size of the mapped region in bytes. + pub(crate) fn size(&self) -> usize { + self.mapped().num_pages * PAGE_SIZE + } + + /// Get the starting virtual frame number. + pub(crate) fn vfn_start(&self) -> Vfn { + self.mapped().vfn_start + } + + /// Get the number of pages in this mapping. + pub(crate) fn num_pages(&self) -> usize { + self.mapped().num_pages + } + + /// Translate an offset within this mapping to a BAR1 aperture offset. + fn bar_offset(&self, offset: usize) -> Result { + if offset >=3D self.size() { + return Err(EINVAL); + } + + let base_vfn: usize =3D self.mapped().vfn_start.raw().into_safe_ca= st(); + let base =3D base_vfn.checked_mul(PAGE_SIZE).ok_or(EOVERFLOW)?; + base.checked_add(offset).ok_or(EOVERFLOW) + } + + // Fallible accessors with runtime bounds checking. + + /// Read a 32-bit value at the given offset. + pub(crate) fn try_read32( + &self, + dev: &device::Device, + offset: usize, + ) -> Result { + let off =3D self.bar_offset(offset)?; + self.bar_user.bar1.access(dev)?.try_read32(off) + } + + /// Write a 32-bit value at the given offset. + pub(crate) fn try_write32( + &self, + dev: &device::Device, + value: u32, + offset: usize, + ) -> Result { + let off =3D self.bar_offset(offset)?; + self.bar_user.bar1.access(dev)?.try_write32(value, off) + } + + /// Read a 64-bit value at the given offset. + pub(crate) fn try_read64( + &self, + dev: &device::Device, + offset: usize, + ) -> Result { + let off =3D self.bar_offset(offset)?; + self.bar_user.bar1.access(dev)?.try_read64(off) + } + + /// Write a 64-bit value at the given offset. + pub(crate) fn try_write64( + &self, + dev: &device::Device, + value: u64, + offset: usize, + ) -> Result { + let off =3D self.bar_offset(offset)?; + self.bar_user.bar1.access(dev)?.try_write64(value, off) + } +} + +impl Drop for BarUserAccess { + fn drop(&mut self) { + if self.mapped.is_some() { + kernel::pr_warn!( + "BarUserAccess dropped without calling release(). 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Mon, 18 May 2026 18:11:55 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%6]) with mapi id 15.21.0025.012; Mon, 18 May 2026 18:11:55 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Miguel Ojeda , Boqun Feng , Gary Guo , Bjorn Roy Baron , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Dave Airlie , Daniel Almeida , dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, nova-gpu@lists.linux.dev, Nikola Djukic , David Airlie , Boqun Feng , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Balbir Singh , Philipp Stanner , alexeyi@nvidia.com, Eliot Courtney , joel@joelfernandes.org, linux-doc@vger.kernel.org, Joel Fernandes Subject: [PATCH v1 16/16] gpu: nova-core: mm: Add BAR1 memory management self-tests Date: Mon, 18 May 2026 14:11:25 -0400 Message-Id: <20260518181126.2493572-17-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260518181126.2493572-1-joelagnelf@nvidia.com> References: <20260518181126.2493572-1-joelagnelf@nvidia.com> Content-Type: text/plain; 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This results in testing the Vmm, GPU buddy allocator and BAR1 region all of which should function correctly for the tests to pass. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/gpu.rs | 8 +- drivers/gpu/nova-core/mm.rs | 12 +- drivers/gpu/nova-core/mm/bar_user.rs | 253 ++++++++++++++++++++++++++ drivers/gpu/nova-core/mm/pagetable.rs | 33 ++++ 4 files changed, 303 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index b0eebe6406e5..6ed486503957 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -405,7 +405,13 @@ pub(crate) fn run_selftests( self: Pin<&mut Self>, pdev: &pci::Device, ) -> Result { - crate::mm::run_mm_selftests(pdev, &self.mm, self.spec.chipset)?; + crate::mm::run_mm_selftests( + pdev, + &self.mm, + &self.bar1, + self.gsp_static_info.bar1_pde_base, + self.spec.chipset, + )?; Ok(()) } } diff --git a/drivers/gpu/nova-core/mm.rs b/drivers/gpu/nova-core/mm.rs index 4741ef60593b..ed77162db848 100644 --- a/drivers/gpu/nova-core/mm.rs +++ b/drivers/gpu/nova-core/mm.rs @@ -55,7 +55,10 @@ macro_rules! impl_pfn_bounded { }; =20 use crate::{ - driver::Bar0, + driver::{ + Bar0, + Bar1, // + }, gpu::Chipset, // }; =20 @@ -122,10 +125,15 @@ pub(crate) fn tlb(&self) -> &Tlb { pub(crate) fn run_mm_selftests( pdev: &pci::Device, mm: &Arc, + bar1: &Arc>, + bar1_pde_base: u64, chipset: Chipset, ) -> Result { #[cfg(CONFIG_NOVA_MM_SELFTESTS)] - pramin::run_self_test(pdev.as_ref(), mm.pramin(), chipset)?; + { + pramin::run_self_test(pdev.as_ref(), mm.pramin(), chipset)?; + bar_user::run_self_test(pdev.as_ref(), mm, bar1, bar1_pde_base, ch= ipset)?; + } =20 Ok(()) } diff --git a/drivers/gpu/nova-core/mm/bar_user.rs b/drivers/gpu/nova-core/m= m/bar_user.rs index bb9742c036b7..96e1389dcbe9 100644 --- a/drivers/gpu/nova-core/mm/bar_user.rs +++ b/drivers/gpu/nova-core/mm/bar_user.rs @@ -192,3 +192,256 @@ fn drop(&mut self) { // identifying the leaked VA range. } } + +/// Run MM subsystem self-tests during probe. +/// +/// Tests page table infrastructure and `BAR1` MMIO access using the `BAR1` +/// address space. Uses the `GpuMm`'s buddy allocator to allocate page tab= les +/// and test pages as needed. +#[cfg(CONFIG_NOVA_MM_SELFTESTS)] +pub(crate) fn run_self_test( + pdev: &device::Device, + mm: &Arc, + bar1_devres: &Arc>, + bar1_pdb: u64, + chipset: Chipset, +) -> Result { + use kernel::gpu::buddy::{ + GpuBuddyAllocFlags, + GpuBuddyAllocMode, // + }; + use kernel::ptr::Alignment; + use kernel::sizes::{ + SZ_16K, + SZ_32K, + SZ_4K, + SZ_64K, // + }; + + // Test patterns. + const PATTERN_PRAMIN: u32 =3D 0xDEAD_BEEF; + const PATTERN_BAR1: u32 =3D 0xCAFE_BABE; + + let dev =3D pdev; + let bar1: &Bar1 =3D bar1_devres.access(pdev)?; + dev_info!(dev, "MM: Starting self-test...\n"); + + let pdb_addr =3D VramAddress::new(bar1_pdb); + + // Check if initial page tables are in VRAM. + if crate::mm::pagetable::check_pdb_valid(pdev, mm.pramin(), pdb_addr, = chipset).is_err() { + dev_info!(dev, "MM: Self-test SKIPPED - no valid VRAM page tables\= n"); + return Ok(()); + } + + // Set up a test page from the buddy allocator. + let test_page_blocks =3D KBox::pin_init( + mm.buddy().alloc_blocks( + GpuBuddyAllocMode::Simple, + SZ_4K.into_safe_cast(), + Alignment::new::(), + GpuBuddyAllocFlags::default(), + ), + GFP_KERNEL, + )?; + let test_vram_offset =3D test_page_blocks.iter().next().ok_or(ENOMEM)?= .offset(); + let test_vram =3D VramAddress::new(test_vram_offset); + let test_pfn =3D Pfn::from(test_vram); + + // Create a VMM of size 64K to track virtual memory mappings. + let mut vmm =3D Vmm::new(pdb_addr, chipset.mmu_version(), SZ_64K.into_= safe_cast())?; + + // Create a test mapping. + let mapped =3D vmm.map_pages(pdev, mm, &[test_pfn], None, true)?; + let test_vfn =3D mapped.vfn_start; + + // Pre-compute test addresses for the PRAMIN to BAR1 read test. + let vfn_offset: usize =3D test_vfn.raw().into_safe_cast(); + let bar1_base_offset =3D vfn_offset.checked_mul(PAGE_SIZE).ok_or(EOVER= FLOW)?; + let bar1_read_offset: usize =3D bar1_base_offset + 0x100; + let vram_read_addr =3D test_vram + 0x100; + + // Test 1: Write via PRAMIN, read via BAR1. + { + let mut window =3D mm.pramin().get_window(pdev)?; + window.try_write32(vram_read_addr, PATTERN_PRAMIN)?; + } + + // Read back via BAR1 aperture. + let bar1_value =3D bar1.try_read32(bar1_read_offset)?; + + let test1_passed =3D if bar1_value =3D=3D PATTERN_PRAMIN { + true + } else { + dev_err!( + dev, + "MM: Test 1 FAILED - Expected {:#010x}, got {:#010x}\n", + PATTERN_PRAMIN, + bar1_value + ); + false + }; + + // Cleanup - invalidate PTE. + vmm.unmap_pages(pdev, mm, mapped)?; + + // Test 2: Two-phase prepare/execute API. + let prepared =3D vmm.prepare_map(pdev, mm, 1, None)?; + let mapped2 =3D vmm.execute_map(pdev, mm, prepared, &[test_pfn], true)= ?; + let readback =3D vmm.read_mapping(pdev, mm, mapped2.vfn_start)?; + let test2_passed =3D if readback =3D=3D Some(test_pfn) { + true + } else { + dev_err!(dev, "MM: Test 2 FAILED - Two-phase map readback mismatch= \n"); + false + }; + vmm.unmap_pages(pdev, mm, mapped2)?; + + // Test 3: Range-constrained allocation with a hole =E2=80=94 exercise= s block.size()-driven + // BAR1 mapping. A 4K hole is punched at base+16K, then a single 32K a= llocation + // is requested within [base, base+36K). The buddy allocator must spli= t around the + // hole, returning multiple blocks (expected: {16K, 4K, 8K, 4K} =3D 32= K total). + // Each block is mapped into BAR1 and verified via PRAMIN read-back. + // + // Address layout (base =3D 0x10000): + // [ 16K ] [HOLE 4K] [4K] [ 8K ] [4K] + // 0x10000 0x14000 0x15000 0x16000 0x18000 0x19000 + let range_base: u64 =3D SZ_64K.into_safe_cast(); + let sz_4k: u64 =3D SZ_4K.into_safe_cast(); + let sz_16k: u64 =3D SZ_16K.into_safe_cast(); + let sz_32k_4k: u64 =3D (SZ_32K + SZ_4K).into_safe_cast(); + + // Punch a 4K hole at base+16K so the subsequent 32K allocation must s= plit. + let _hole =3D KBox::pin_init( + mm.buddy().alloc_blocks( + GpuBuddyAllocMode::Range(range_base + sz_16k..range_base + sz_= 16k + sz_4k), + SZ_4K.into_safe_cast(), + Alignment::new::(), + GpuBuddyAllocFlags::default(), + ), + GFP_KERNEL, + )?; + + // Allocate 32K within [base, base+36K). The hole forces the allocator= to return + // split blocks whose sizes are determined by buddy alignment. + let blocks =3D KBox::pin_init( + mm.buddy().alloc_blocks( + GpuBuddyAllocMode::Range(range_base..range_base + sz_32k_4k), + SZ_32K.into_safe_cast(), + Alignment::new::(), + GpuBuddyAllocFlags::default(), + ), + GFP_KERNEL, + )?; + + let mut test3_passed =3D true; + let mut total_size =3D 0usize; + + for block in blocks.iter() { + total_size +=3D IntoSafeCast::::into_safe_cast(block.size()= ); + + // Map all pages of this block. + let page_size: u64 =3D PAGE_SIZE.into_safe_cast(); + let num_pages: usize =3D (block.size() / page_size).into_safe_cast= (); + + let mut pfns =3D KVec::new(); + for j in 0..num_pages { + let j_u64: u64 =3D j.into_safe_cast(); + pfns.push( + Pfn::from(VramAddress::new( + block.offset() + j_u64.checked_mul(page_size).ok_or(EO= VERFLOW)?, + )), + GFP_KERNEL, + )?; + } + + let mapped =3D vmm.map_pages(pdev, mm, &pfns, None, true)?; + let bar1_base_vfn: usize =3D mapped.vfn_start.raw().into_safe_cast= (); + let bar1_base =3D bar1_base_vfn.checked_mul(PAGE_SIZE).ok_or(EOVER= FLOW)?; + + for j in 0..num_pages { + let page_bar1_off =3D bar1_base + j * PAGE_SIZE; + let j_u64: u64 =3D j.into_safe_cast(); + let page_phys =3D block.offset() + + j_u64 + .checked_mul(PAGE_SIZE.into_safe_cast()) + .ok_or(EOVERFLOW)?; + + bar1.try_write32(PATTERN_BAR1, page_bar1_off)?; + + let pramin_val =3D { + let mut window =3D mm.pramin().get_window(pdev)?; + window.try_read32(VramAddress::new(page_phys))? + }; + + if pramin_val !=3D PATTERN_BAR1 { + dev_err!( + dev, + "MM: Test 3 FAILED block offset {:#x} page {} (val=3D{= :#x})\n", + block.offset(), + j, + pramin_val + ); + test3_passed =3D false; + } + } + + vmm.unmap_pages(pdev, mm, mapped)?; + } + + // Verify aggregate: all returned block sizes must sum to allocation s= ize. + if total_size !=3D SZ_32K { + dev_err!( + dev, + "MM: Test 3 FAILED - total size {} !=3D expected {}\n", + total_size, + SZ_32K + ); + test3_passed =3D false; + } + + // Release Tests 1-3's Vmm before Test 4 constructs a fresh BarUser on + // the same PDB. + drop(vmm); + + // Test 4: Exercise `BarUser::map()` end-to-end. + let bar_user =3D Arc::pin_init( + BarUser::new( + pdb_addr, + chipset, + SZ_64K.into_safe_cast(), + mm.clone(), + bar1_devres.clone(), + )?, + GFP_KERNEL, + )?; + let access =3D bar_user.map(pdev, &[test_pfn], true)?; + + // Write pattern via PRAMIN, read via BarUserAccess. + { + let mut window =3D mm.pramin().get_window(pdev)?; + window.try_write32(test_vram, PATTERN_BAR1)?; + } + + let readback =3D access.try_read32(pdev, 0)?; + let test4_passed =3D if readback =3D=3D PATTERN_BAR1 { + true + } else { + dev_err!( + dev, + "MM: Test 4 FAILED - Expected {:#010x}, got {:#010x}\n", + PATTERN_BAR1, + readback + ); + false + }; + access.release(pdev)?; + + if test1_passed && test2_passed && test3_passed && test4_passed { + dev_info!(dev, "MM: All self-tests PASSED\n"); + Ok(()) + } else { + dev_err!(dev, "MM: Self-tests FAILED\n"); + Err(EIO) + } +} diff --git a/drivers/gpu/nova-core/mm/pagetable.rs b/drivers/gpu/nova-core/= mm/pagetable.rs index 042584e5178b..fb573f07b4cf 100644 --- a/drivers/gpu/nova-core/mm/pagetable.rs +++ b/drivers/gpu/nova-core/mm/pagetable.rs @@ -17,6 +17,9 @@ =20 use kernel::num::Bounded; =20 +#[cfg(CONFIG_NOVA_MM_SELFTESTS)] +use kernel::device; + use crate::gpu::Architecture; use crate::mm::{ pramin, @@ -379,3 +382,33 @@ fn from(val: AperturePde) -> Self { Bounded::from_expr(val as u64 & 0x3) } } + +/// Check if the PDB has valid, VRAM-backed page tables. +#[cfg(CONFIG_NOVA_MM_SELFTESTS)] +fn check_pdb_inner( + dev: &device::Device, + pramin: &pramin::Pramin, + pdb_addr: VramAddress, +) -> Result { + let mut window =3D pramin.get_window(dev)?; + let raw =3D window.try_read64(pdb_addr)?; + + if !M::Pde::from_raw(raw).is_valid_vram() { + return Err(ENOENT); + } + Ok(()) +} + +/// Check if the PDB has valid, VRAM-backed page tables, dispatching by MM= U version. +#[cfg(CONFIG_NOVA_MM_SELFTESTS)] +pub(super) fn check_pdb_valid( + dev: &device::Device, + pramin: &pramin::Pramin, + pdb_addr: VramAddress, + chipset: crate::gpu::Chipset, +) -> Result { + match MmuVersion::from(chipset.arch()) { + MmuVersion::V2 =3D> check_pdb_inner::(dev, pramin, pdb_addr= ), + MmuVersion::V3 =3D> check_pdb_inner::(dev, pramin, pdb_addr= ), + } +} --=20 2.34.1