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Mon, 18 May 2026 08:53:32 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Lorenzo Pieralisi , Manivannan Sadhasivam , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Rob Herring , Claudiu Beznea , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 1/4] dt-bindings: PCI: renesas,r9a08g045-pcie: Add RZ/V2H(P) support Date: Mon, 18 May 2026 16:53:21 +0100 Message-ID: <20260518155324.168948-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260518155324.168948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260518155324.168948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add support for the PCIe controller found on the Renesas RZ/V2H(P) SoC. The RZ/V2H(P) controller is similar to the RZ/G3E variant but includes additional registers and configuration bits for PCIe lane control. It supports multilink operation configured as either a single x4 link or two independent x2 link controllers. Unlike earlier SoCs supported by this driver which only feature a single PCIe controller, the RZ/V2H(P) SoC implements two controllers. Both controllers rely on the system controller (`sysc`) for configuration, but the required registers reside at different offsets for each instance. To correctly identify the controller instance and map the corresponding system controller registers, make the "linux,pci-domain" and "num-lanes" properties mandatory for this SoC and restrict their values according to the hardware capabilities. Signed-off-by: Lad Prabhakar --- v1->v2: - Updated commit message. - Dropped un-necessary new line in schema. --- .../bindings/pci/renesas,r9a08g045-pcie.yaml | 21 +++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.y= aml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml index 90086909e921..149a2973b16e 100644 --- a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml @@ -14,7 +14,7 @@ description: | with PCIe Base Specification 4.0 and supports different link speeds depending on the SoC variant: - Gen2 (5 GT/s): RZ/G3S - - Gen3 (8 GT/s): RZ/G3E, RZ/V2N + - Gen3 (8 GT/s): RZ/G3E, RZ/V2H(P), RZ/V2N =20 properties: compatible: @@ -22,6 +22,7 @@ properties: - enum: - renesas,r9a08g045-pcie # RZ/G3S - renesas,r9a09g047-pcie # RZ/G3E + - renesas,r9a09g057-pcie # RZ/V2H(P) - items: - const: renesas,r9a09g056-pcie # RZ/V2N - const: renesas,r9a09g047-pcie @@ -220,7 +221,9 @@ allOf: properties: compatible: contains: - const: renesas,r9a09g047-pcie + enum: + - renesas,r9a09g047-pcie + - renesas,r9a09g057-pcie then: properties: interrupts: @@ -235,6 +238,20 @@ allOf: maxItems: 1 reset-names: maxItems: 1 + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-pcie + then: + properties: + linux,pci-domain: + enum: [0, 1] + num-lanes: + enum: [2, 4] + required: + - linux,pci-domain + - num-lanes =20 unevaluatedProperties: false =20 --=20 2.54.0 From nobody Mon May 25 05:14:39 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5190636F405 for ; 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Mon, 18 May 2026 08:53:33 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:2409:d26f:6d8b:b2cc]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48fe4c8344asm450054575e9.1.2026.05.18.08.53.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 08:53:33 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Lorenzo Pieralisi , Manivannan Sadhasivam , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Rob Herring , Claudiu Beznea , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 2/4] PCI: rzg3s-host: Use shared reset controls for power domain resets Date: Mon, 18 May 2026 16:53:22 +0100 Message-ID: <20260518155324.168948-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260518155324.168948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260518155324.168948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Switch to shared reset controls for PCIe power resets to prepare for RZ/V2H(P) support. On this platform, multiple PCIe controllers share the same reset line, requiring shared ownership of the reset control. Signed-off-by: Lad Prabhakar --- v1->v2: - Updated commit message. --- drivers/pci/controller/pcie-rzg3s-host.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/control= ler/pcie-rzg3s-host.c index d86e7516dcc2..a5192e4b58df 100644 --- a/drivers/pci/controller/pcie-rzg3s-host.c +++ b/drivers/pci/controller/pcie-rzg3s-host.c @@ -1276,9 +1276,9 @@ static int rzg3s_pcie_resets_prepare_and_get(struct r= zg3s_pcie_host *host) for (i =3D 0; i < data->num_cfg_resets; i++) host->cfg_resets[i].id =3D data->cfg_resets[i]; =20 - ret =3D devm_reset_control_bulk_get_exclusive(host->dev, - data->num_power_resets, - host->power_resets); + ret =3D devm_reset_control_bulk_get_shared(host->dev, + data->num_power_resets, + host->power_resets); if (ret) return ret; =20 --=20 2.54.0 From nobody Mon May 25 05:14:39 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CA823F8896 for ; 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Mon, 18 May 2026 08:53:34 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:2409:d26f:6d8b:b2cc]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48fe4c8344asm450054575e9.1.2026.05.18.08.53.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 08:53:34 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Lorenzo Pieralisi , Manivannan Sadhasivam , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Rob Herring , Claudiu Beznea , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 3/4] PCI: rzg3s-host: Prepare System Controller handling for multiple controllers Date: Mon, 18 May 2026 16:53:23 +0100 Message-ID: <20260518155324.168948-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260518155324.168948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260518155324.168948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Prepare the driver to handle multiple PCIe controllers with distinct System Controller (SYSC) register sets, as required by RZ/V2H(P). The current design stores a single sysc_info structure per SoC, which is insufficient for multi-controller configurations. Introduce controller identifiers and extend struct rzg3s_pcie_soc_data to hold a sysc_info array indexed per PCIe controller. Add a controller_id field to struct rzg3s_pcie_host and select the appropriate System Controller information during probe based on the hardware instance. Keep existing single-controller SoCs functionally unchanged while preparing the driver for RZ/V2H(P) multi-controller support. Signed-off-by: Lad Prabhakar --- v1->v2: - Renamed RZG3S_PCIE_CHANNEL_ID* to RZG3S_PCIE_CONTROLLER_ID* for clarity. - Updated commit message. --- drivers/pci/controller/pcie-rzg3s-host.c | 48 ++++++++++++++++-------- 1 file changed, 33 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/control= ler/pcie-rzg3s-host.c index a5192e4b58df..edb49af7429a 100644 --- a/drivers/pci/controller/pcie-rzg3s-host.c +++ b/drivers/pci/controller/pcie-rzg3s-host.c @@ -241,6 +241,18 @@ struct rzg3s_pcie_msi { int irq; }; =20 +/** + * enum rzg3s_pcie_controller_id - RZ/G3S PCIe controller IDs + * @RZG3S_PCIE_CONTROLLER_ID_0: PCIe controller 0 + * @RZG3S_PCIE_CONTROLLER_ID_1: PCIe controller 1 + * @RZG3S_PCIE_CONTROLLER_ID_MAX: Max PCIe controllers + */ +enum rzg3s_pcie_controller_id { + RZG3S_PCIE_CONTROLLER_ID_0, + RZG3S_PCIE_CONTROLLER_ID_1, + RZG3S_PCIE_CONTROLLER_ID_MAX, +}; + struct rzg3s_pcie_host; =20 /** @@ -253,7 +265,7 @@ struct rzg3s_pcie_host; * power-on * @cfg_resets: array with the resets that need to be de-asserted after * configuration - * @sysc_info: SYSC info + * @sysc_info: System Controller info for each controller * @num_power_resets: number of power resets * @num_cfg_resets: number of configuration resets */ @@ -264,7 +276,7 @@ struct rzg3s_pcie_soc_data { int (*config_deinit)(struct rzg3s_pcie_host *host); const char * const *power_resets; const char * const *cfg_resets; - struct rzg3s_sysc_info sysc_info; + struct rzg3s_sysc_info sysc_info[RZG3S_PCIE_CONTROLLER_ID_MAX]; u8 num_power_resets; u8 num_cfg_resets; }; @@ -296,6 +308,7 @@ struct rzg3s_pcie_port { * @hw_lock: lock for access to the HW resources * @intx_irqs: INTx interrupts * @max_link_speed: maximum supported link speed + * @controller_id: PCIe controller identifier, used for System Controller = access */ struct rzg3s_pcie_host { void __iomem *axi; @@ -311,6 +324,7 @@ struct rzg3s_pcie_host { raw_spinlock_t hw_lock; int intx_irqs[PCI_NUM_INTX]; int max_link_speed; + enum rzg3s_pcie_controller_id controller_id; }; =20 #define rzg3s_msi_to_host(_msi) container_of(_msi, struct rzg3s_pcie_host,= msi) @@ -1698,7 +1712,7 @@ static int rzg3s_pcie_probe(struct platform_device *p= dev) return -ENOMEM; =20 sysc =3D host->sysc; - sysc->info =3D &host->data->sysc_info; + sysc->info =3D &host->data->sysc_info[host->controller_id]; =20 host->axi =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(host->axi)) @@ -1891,10 +1905,12 @@ static const struct rzg3s_pcie_soc_data rzg3s_soc_d= ata =3D { .config_deinit =3D rzg3s_pcie_config_deinit, .init_phy =3D rzg3s_soc_pcie_init_phy, .sysc_info =3D { - .functions =3D { - [RZG3S_SYSC_FUNC_ID_RST_RSM_B] =3D { - .offset =3D 0xd74, - .mask =3D BIT(0), + [RZG3S_PCIE_CONTROLLER_ID_0] =3D { + .functions =3D { + [RZG3S_SYSC_FUNC_ID_RST_RSM_B] =3D { + .offset =3D 0xd74, + .mask =3D BIT(0), + }, }, }, }, @@ -1909,14 +1925,16 @@ static const struct rzg3s_pcie_soc_data rzg3e_soc_d= ata =3D { .config_post_init =3D rzg3e_pcie_config_post_init, .config_deinit =3D rzg3e_pcie_config_deinit, .sysc_info =3D { - .functions =3D { - [RZG3S_SYSC_FUNC_ID_L1_ALLOW] =3D { - .offset =3D 0x1020, - .mask =3D BIT(0), - }, - [RZG3S_SYSC_FUNC_ID_MODE] =3D { - .offset =3D 0x1024, - .mask =3D BIT(0), + [RZG3S_PCIE_CONTROLLER_ID_0] =3D { + .functions =3D { + [RZG3S_SYSC_FUNC_ID_L1_ALLOW] =3D { + .offset =3D 0x1020, + .mask =3D BIT(0), + }, + [RZG3S_SYSC_FUNC_ID_MODE] =3D { + .offset =3D 0x1024, + .mask =3D BIT(0), + }, }, }, }, --=20 2.54.0 From nobody Mon May 25 05:14:39 2026 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5B1748A2CE for ; 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Mon, 18 May 2026 08:53:35 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:2409:d26f:6d8b:b2cc]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48fe4c8344asm450054575e9.1.2026.05.18.08.53.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 08:53:35 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Lorenzo Pieralisi , Manivannan Sadhasivam , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Rob Herring , Claudiu Beznea , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 4/4] PCI: rzg3s-host: Add support for RZ/V2H(P) SoC Date: Mon, 18 May 2026 16:53:24 +0100 Message-ID: <20260518155324.168948-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260518155324.168948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260518155324.168948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add support for the RZ/V2H(P) SoC PCIe controllers to the rzg3s-host driver. The RZ/V2H(P) SoC features two independent PCIe controllers that share four physical lanes. The hardware supports two configuration modes: single x4 mode where the first controller uses all four lanes, or dual x2 mode where both controllers use two lanes each. Introduce a setup_lanes() function pointer to configure the PCIe lanes based on the hardware instance. Implement rzv2h_pcie_setup_lanes() to detect the configuration at boot time and program the lane mode via the system controller. Signed-off-by: Lad Prabhakar --- v1->v2: - Updated commit message. - Added locks to protect shared lane configuration state and prevent concurrent access issues during probe. - Added cleanup action to release lanes on driver removal. - Reconfigured RZG3S_SYSC_FUNC_ID_LINK_MASTER in resume path. - Renamed num_channels to num_pcie_controllers for clarity. --- drivers/pci/controller/pcie-rzg3s-host.c | 177 +++++++++++++++++++++++ 1 file changed, 177 insertions(+) diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/control= ler/pcie-rzg3s-host.c index edb49af7429a..1cd9f7c10357 100644 --- a/drivers/pci/controller/pcie-rzg3s-host.c +++ b/drivers/pci/controller/pcie-rzg3s-host.c @@ -179,6 +179,16 @@ /* Timeouts experimentally determined */ #define RZG3S_REQ_ISSUE_TIMEOUT_US 2500 =20 +/** + * enum rzg3s_sysc_link_mode - PCIe link configuration modes + * @RZG3S_SYSC_LINK_MODE_SINGLE_X4: Single port with x4 lanes + * @RZG3S_SYSC_LINK_MODE_DUAL_X2: Dual ports with x2 lanes each + */ +enum rzg3s_sysc_link_mode { + RZG3S_SYSC_LINK_MODE_SINGLE_X4 =3D 1, + RZG3S_SYSC_LINK_MODE_DUAL_X2 =3D 3, +}; + /** * struct rzg3s_sysc_function - System Controller function descriptor * @offset: Register offset from the System Controller base address @@ -194,12 +204,14 @@ struct rzg3s_sysc_function { * @RZG3S_SYSC_FUNC_ID_RST_RSM_B: RST_RSM_B SYSC function ID * @RZG3S_SYSC_FUNC_ID_L1_ALLOW: L1 allow SYSC function ID * @RZG3S_SYSC_FUNC_ID_MODE: Mode SYSC function ID + * @RZG3S_SYSC_FUNC_ID_LINK_MASTER: Link master SYSC function ID * @RZG3S_SYSC_FUNC_ID_MAX: Max SYSC function ID */ enum rzg3s_sysc_func_id { RZG3S_SYSC_FUNC_ID_RST_RSM_B, RZG3S_SYSC_FUNC_ID_L1_ALLOW, RZG3S_SYSC_FUNC_ID_MODE, + RZG3S_SYSC_FUNC_ID_LINK_MASTER, RZG3S_SYSC_FUNC_ID_MAX, }; =20 @@ -261,6 +273,7 @@ struct rzg3s_pcie_host; * @config_pre_init: Optional callback for SoC-specific pre-configuration * @config_post_init: Callback for SoC-specific post-configuration * @config_deinit: Callback for SoC-specific de-initialization + * @setup_lanes: Callback for setting up the number of lanes * @power_resets: array with the resets that need to be de-asserted after * power-on * @cfg_resets: array with the resets that need to be de-asserted after @@ -268,17 +281,20 @@ struct rzg3s_pcie_host; * @sysc_info: System Controller info for each controller * @num_power_resets: number of power resets * @num_cfg_resets: number of configuration resets + * @num_pcie_controllers: number of PCIe controllers */ struct rzg3s_pcie_soc_data { int (*init_phy)(struct rzg3s_pcie_host *host); void (*config_pre_init)(struct rzg3s_pcie_host *host); int (*config_post_init)(struct rzg3s_pcie_host *host); int (*config_deinit)(struct rzg3s_pcie_host *host); + int (*setup_lanes)(struct rzg3s_pcie_host *host); const char * const *power_resets; const char * const *cfg_resets; struct rzg3s_sysc_info sysc_info[RZG3S_PCIE_CONTROLLER_ID_MAX]; u8 num_power_resets; u8 num_cfg_resets; + u8 num_pcie_controllers; }; =20 /** @@ -309,6 +325,7 @@ struct rzg3s_pcie_port { * @intx_irqs: INTx interrupts * @max_link_speed: maximum supported link speed * @controller_id: PCIe controller identifier, used for System Controller = access + * @num_lanes: The number of lanes */ struct rzg3s_pcie_host { void __iomem *axi; @@ -325,10 +342,23 @@ struct rzg3s_pcie_host { int intx_irqs[PCI_NUM_INTX]; int max_link_speed; enum rzg3s_pcie_controller_id controller_id; + u8 num_lanes; }; =20 #define rzg3s_msi_to_host(_msi) container_of(_msi, struct rzg3s_pcie_host,= msi) =20 +/* + * RZ/V2H(P) supports a total of 4 lanes shared across two controllers. + * rzv2h_lane_lock serialises both the counter update and the SYSC + * register write so that concurrent async probes cannot race on the + * shared LINK_MASTER register (offset 0x1060). + * rzv2h_num_total_lanes tracks global lane usage to prevent + * over-allocation or invalid bifurcation modes. + */ +#define RZV2H_PCIE_MAX_LANES 4 +static DEFINE_SPINLOCK(rzv2h_lane_lock); +static u8 rzv2h_num_total_lanes; + static int rzg3s_sysc_config_func(struct rzg3s_sysc *sysc, enum rzg3s_sysc_func_id fid, u32 val) { @@ -1155,6 +1185,13 @@ static int rzg3s_pcie_config_init(struct rzg3s_pcie_= host *host) rzg3s_pcie_update_bits(host->pcie, PCI_CLASS_REVISION, mask, field_prep(mask, PCI_CLASS_BRIDGE_PCI_NORMAL)); =20 + if (host->num_lanes) { + rzg3s_pcie_update_bits(host->pcie + RZG3S_PCI_CFG_PCIEC, + PCI_EXP_LNKCAP, PCI_EXP_LNKCAP_MLW, + FIELD_PREP(PCI_EXP_LNKCAP_MLW, + host->num_lanes)); + } + /* Disable access control to the CFGU */ writel_relaxed(0, host->axi + RZG3S_PCI_PERM); =20 @@ -1687,6 +1724,72 @@ rzg3s_pcie_host_setup(struct rzg3s_pcie_host *host, return ret; } =20 +static int rzg3s_pcie_get_controller_id(struct rzg3s_pcie_host *host) +{ + struct device_node *np =3D host->dev->of_node; + u32 domain; + int ret; + + if (host->data->num_pcie_controllers =3D=3D 1) + return 0; + + ret =3D of_property_read_u32(np, "linux,pci-domain", &domain); + if (ret) + return ret; + + if (domain >=3D host->data->num_pcie_controllers || domain >=3D RZG3S_PCI= E_CONTROLLER_ID_MAX) + return -EINVAL; + + host->controller_id =3D domain; + + return 0; +} + +static int rzv2h_pcie_setup_lanes(struct rzg3s_pcie_host *host) +{ + struct device_node *np =3D host->dev->of_node; + u32 num_lanes; + int ret; + + ret =3D of_property_read_u32(np, "num-lanes", &num_lanes); + if (ret) + return ret; + + /* + * RZ/V2H(P) supports up to 4 lanes, but only in single x4 mode + * for the first controller. Dual x2 mode is supported with 2 + * lanes for both controllers. + */ + if (num_lanes !=3D 4 && num_lanes !=3D 2) + return -EINVAL; + + if (host->controller_id =3D=3D RZG3S_PCIE_CONTROLLER_ID_1 && num_lanes > = 2) + return -EINVAL; + + guard(spinlock)(&rzv2h_lane_lock); + if (rzv2h_num_total_lanes + num_lanes > RZV2H_PCIE_MAX_LANES) + return -EINVAL; + + ret =3D rzg3s_sysc_config_func(host->sysc, RZG3S_SYSC_FUNC_ID_LINK_MASTER, + num_lanes =3D=3D 2 ? + RZG3S_SYSC_LINK_MODE_DUAL_X2 : + RZG3S_SYSC_LINK_MODE_SINGLE_X4); + if (!ret) { + rzv2h_num_total_lanes +=3D num_lanes; + host->num_lanes =3D num_lanes; + } + + return ret; +} + +static void rzv2h_pcie_release_lanes(void *data) +{ + struct rzg3s_pcie_host *host =3D data; + + guard(spinlock)(&rzv2h_lane_lock); + rzv2h_num_total_lanes -=3D host->num_lanes; +} + static int rzg3s_pcie_probe(struct platform_device *pdev) { struct pci_host_bridge *bridge; @@ -1711,6 +1814,10 @@ static int rzg3s_pcie_probe(struct platform_device *= pdev) if (!host->sysc) return -ENOMEM; =20 + ret =3D rzg3s_pcie_get_controller_id(host); + if (ret) + return ret; + sysc =3D host->sysc; sysc->info =3D &host->data->sysc_info[host->controller_id]; =20 @@ -1740,6 +1847,16 @@ static int rzg3s_pcie_probe(struct platform_device *= pdev) if (ret) goto port_refclk_put; =20 + if (host->data->setup_lanes) { + ret =3D host->data->setup_lanes(host); + if (ret) + goto sysc_signal_restore; + + ret =3D devm_add_action_or_reset(dev, rzv2h_pcie_release_lanes, host); + if (ret) + goto sysc_signal_restore; + } + ret =3D rzg3s_pcie_resets_prepare_and_get(host); if (ret) goto sysc_signal_restore; @@ -1854,6 +1971,16 @@ static int rzg3s_pcie_resume_noirq(struct device *de= v) if (ret) return ret; =20 + if (host->num_lanes) { + ret =3D rzg3s_sysc_config_func(host->sysc, + RZG3S_SYSC_FUNC_ID_LINK_MASTER, + host->num_lanes =3D=3D 2 ? + RZG3S_SYSC_LINK_MODE_DUAL_X2 : + RZG3S_SYSC_LINK_MODE_SINGLE_X4); + if (ret) + goto assert_rst_rsm_b; + } + ret =3D rzg3s_pcie_power_resets_deassert(host); if (ret) goto assert_rst_rsm_b; @@ -1901,6 +2028,7 @@ static const struct rzg3s_pcie_soc_data rzg3s_soc_dat= a =3D { .num_power_resets =3D ARRAY_SIZE(rzg3s_soc_power_resets), .cfg_resets =3D rzg3s_soc_cfg_resets, .num_cfg_resets =3D ARRAY_SIZE(rzg3s_soc_cfg_resets), + .num_pcie_controllers =3D 1, .config_post_init =3D rzg3s_pcie_config_post_init, .config_deinit =3D rzg3s_pcie_config_deinit, .init_phy =3D rzg3s_soc_pcie_init_phy, @@ -1921,6 +2049,7 @@ static const char * const rzg3e_soc_power_resets[] = =3D { "aresetn" }; static const struct rzg3s_pcie_soc_data rzg3e_soc_data =3D { .power_resets =3D rzg3e_soc_power_resets, .num_power_resets =3D ARRAY_SIZE(rzg3e_soc_power_resets), + .num_pcie_controllers =3D 1, .config_pre_init =3D rzg3e_pcie_config_pre_init, .config_post_init =3D rzg3e_pcie_config_post_init, .config_deinit =3D rzg3e_pcie_config_deinit, @@ -1940,6 +2069,50 @@ static const struct rzg3s_pcie_soc_data rzg3e_soc_da= ta =3D { }, }; =20 +static const struct rzg3s_pcie_soc_data rzv2h_soc_data =3D { + .power_resets =3D rzg3e_soc_power_resets, + .num_power_resets =3D ARRAY_SIZE(rzg3e_soc_power_resets), + .num_pcie_controllers =3D 2, + .config_pre_init =3D rzg3e_pcie_config_pre_init, + .config_post_init =3D rzg3e_pcie_config_post_init, + .config_deinit =3D rzg3e_pcie_config_deinit, + .setup_lanes =3D rzv2h_pcie_setup_lanes, + .sysc_info =3D { + [RZG3S_PCIE_CONTROLLER_ID_0] =3D { + .functions =3D { + [RZG3S_SYSC_FUNC_ID_L1_ALLOW] =3D { + .offset =3D 0x1020, + .mask =3D BIT(0), + }, + [RZG3S_SYSC_FUNC_ID_MODE] =3D { + .offset =3D 0x1024, + .mask =3D BIT(0), + }, + [RZG3S_SYSC_FUNC_ID_LINK_MASTER] =3D { + .offset =3D 0x1060, + .mask =3D GENMASK(9, 8), + }, + }, + }, + [RZG3S_PCIE_CONTROLLER_ID_1] =3D { + .functions =3D { + [RZG3S_SYSC_FUNC_ID_L1_ALLOW] =3D { + .offset =3D 0x1050, + .mask =3D BIT(0), + }, + [RZG3S_SYSC_FUNC_ID_MODE] =3D { + .offset =3D 0x1054, + .mask =3D BIT(0), + }, + [RZG3S_SYSC_FUNC_ID_LINK_MASTER] =3D { + .offset =3D 0x1060, + .mask =3D GENMASK(9, 8), + }, + }, + }, + }, +}; + static const struct of_device_id rzg3s_pcie_of_match[] =3D { { .compatible =3D "renesas,r9a08g045-pcie", @@ -1949,6 +2122,10 @@ static const struct of_device_id rzg3s_pcie_of_match= [] =3D { .compatible =3D "renesas,r9a09g047-pcie", .data =3D &rzg3e_soc_data, }, + { + .compatible =3D "renesas,r9a09g057-pcie", + .data =3D &rzv2h_soc_data, + }, {} }; =20 --=20 2.54.0