From nobody Mon May 25 05:13:58 2026 Received: from canpmsgout07.his.huawei.com (canpmsgout07.his.huawei.com [113.46.200.222]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F74E2BEFED; Mon, 18 May 2026 14:31:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.222 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779114692; cv=none; b=EkVsJJwXVuxkiEQMd1W671zqP1/8EDOjGdblNs8hroDuEGrJ8tRFxQ8INEqWBsbk0yZFoFlSHNHinjRW3nJF/hgD+FIiqQ3PexsZ3BdKZWID2UiPhpw+jBS3MEU7nLAX8aw+Qsg4STnmRQ9puUbMoS30P5txgaoIOnJsk8J7lXk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779114692; c=relaxed/simple; bh=uVf9zRL9PyqxuBQA6mnbmZZrpKdygjMALPP7Y70YadQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=q/FvcX9pPQR7fHSFAjkAiwgg0HxwXEhkeAPtX6XB7DXhYC8q1vkuiFvXN2wl19OMQBbAjPs2+cfrxvgXiYA6jWckZPUIxrJnfVX2awCkIBlUnLUrYFpiEzIT/9oeqTYQX/FooxVAmAc6Vuryn2YMvlgfhzsQxOQlwJkQqELrXak= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=QdFgl+NQ; arc=none smtp.client-ip=113.46.200.222 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="QdFgl+NQ" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=nWnSzZFmk/tgwu3p4Z/clwa5y6lnFaYzZKwBB8r5jyg=; b=QdFgl+NQsGNoz5wUJjk235ncgSdSvuQ5PKeWNcx7apiqtEzn0yX7zpfqPLwE6cHUv3UqZhJNz NB1eAJaF3jom993bou7+3MwBhBGphb3AMAHjc12RzShwqIDTS68wt8l8KrjtNftTedjOr6TP3Lb iz/jtemMmsjoyfdcJAIBg0o= Received: from mail.maildlp.com (unknown [172.19.163.163]) by canpmsgout07.his.huawei.com (SkyGuard) with ESMTPS id 4gK0R13RcTzLlSx; Mon, 18 May 2026 22:23:41 +0800 (CST) Received: from kwepemr100008.china.huawei.com (unknown [7.202.195.119]) by mail.maildlp.com (Postfix) with ESMTPS id 560EB4056E; Mon, 18 May 2026 22:31:21 +0800 (CST) Received: from localhost.localdomain (10.50.163.32) by kwepemr100008.china.huawei.com (7.202.195.119) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.36; Mon, 18 May 2026 22:31:20 +0800 From: ZongYu Wu To: , CC: , , , , , , Subject: [PATCH 1/6] crypto: hisilicon/qm - allow VF devices to query hardware isolation status Date: Mon, 18 May 2026 22:29:51 +0800 Message-ID: <20260518142956.3593934-2-wuzongyu1@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260518142956.3593934-1-wuzongyu1@huawei.com> References: <20260518142956.3593934-1-wuzongyu1@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemr100008.china.huawei.com (7.202.195.119) Content-Type: text/plain; charset="utf-8" From: Zhushuai Yin The problem that the VF device cannot obtain the isolation status and isolation threshold of the device is resolved. The accelerator driver can query the device isolation status and threshold via the VF device using the fault query sysfs interface under uacce. Note that only the PF device supports isolation policy configuration, while the VF device is limited to read-only query operations. Signed-off-by: Zhushuai Yin Signed-off-by: Zongyu Wu --- drivers/crypto/hisilicon/hpre/hpre_main.c | 10 +- drivers/crypto/hisilicon/qm.c | 128 ++++++++++++++++++++-- drivers/crypto/hisilicon/sec2/sec_main.c | 10 +- drivers/crypto/hisilicon/zip/zip_main.c | 10 +- include/linux/hisi_acc_qm.h | 1 + 5 files changed, 129 insertions(+), 30 deletions(-) diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c b/drivers/crypto/his= ilicon/hpre/hpre_main.c index 357ab5e5887e..a484381f522a 100644 --- a/drivers/crypto/hisilicon/hpre/hpre_main.c +++ b/drivers/crypto/hisilicon/hpre/hpre_main.c @@ -1631,12 +1631,10 @@ static int hpre_probe(struct pci_dev *pdev, const s= truct pci_device_id *id) goto err_qm_del_list; } =20 - if (qm->uacce) { - ret =3D uacce_register(qm->uacce); - if (ret) { - pci_err(pdev, "failed to register uacce (%d)!\n", ret); - goto err_with_alg_register; - } + ret =3D hisi_qm_register_uacce(qm); + if (ret) { + pci_err(pdev, "failed to register uacce (%d)!\n", ret); + goto err_with_alg_register; } =20 if (qm->fun_type =3D=3D QM_HW_PF && vfs_num) { diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index 3ca47e2a9719..9cf52873a891 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -246,6 +246,10 @@ #define QM_QOS_MAX_CIR_U 6 #define QM_AUTOSUSPEND_DELAY 3000 =20 +/* qm isolation state mask */ +#define QM_ISOLATED_STATE BIT(31) +#define QM_ISOLATED_THRESHOLD_MASK GENMASK(15, 0) + /* abnormal status value for stopping queue */ #define QM_STOP_QUEUE_FAIL 1 #define QM_DUMP_SQC_FAIL 3 @@ -286,6 +290,20 @@ enum qm_alg_type { ALG_TYPE_1, }; =20 +/* + * Message format for QM_VF_GET_ISOLATE and QM_PF_SET_ISOLATE commands + * + * These commands use a 32-bit command field (cmd) and 32-bit data field (= data) + * + * Command behavior: + * - QM_VF_GET_ISOLATE: VF requests isolation status and threshold + * - QM_PF_SET_ISOLATE: PF sets isolation status and threshold + * + * Data field bit layout: + * - bit31 (MSB): Isolation status flag (1 =3D isolated, 0 =3D non-isolate= d) + * - bit15-0 (16 LSB): Isolation threshold value + * - bit30-16 (15 bits): Reserved + */ enum qm_ifc_cmd { QM_PF_FLR_PREPARE =3D 0x01, QM_PF_SRST_PREPARE, @@ -296,6 +314,8 @@ enum qm_ifc_cmd { QM_VF_START_FAIL, QM_PF_SET_QOS, QM_VF_GET_QOS, + QM_VF_GET_ISOLATE, + QM_PF_SET_ISOLATE, }; =20 enum qm_basic_type { @@ -1734,7 +1754,7 @@ static int qm_ping_single_vf(struct hisi_qm *qm, enum= qm_ifc_cmd cmd, u32 data, return ret; } =20 -static int qm_ping_all_vfs(struct hisi_qm *qm, enum qm_ifc_cmd cmd) +static int qm_ping_all_vfs(struct hisi_qm *qm, enum qm_ifc_cmd cmd, u32 da= ta) { struct device *dev =3D &qm->pdev->dev; u32 vfs_num =3D qm->vfs_num; @@ -1743,7 +1763,7 @@ static int qm_ping_all_vfs(struct hisi_qm *qm, enum q= m_ifc_cmd cmd) int ret; u32 i; =20 - ret =3D qm->ops->set_ifc_begin(qm, cmd, 0, QM_MB_PING_ALL_VFS); + ret =3D qm->ops->set_ifc_begin(qm, cmd, data, QM_MB_PING_ALL_VFS); if (ret) { dev_err(dev, "failed to send command(0x%x) to all vfs!\n", cmd); qm->ops->set_ifc_end(qm); @@ -2779,6 +2799,7 @@ static enum uacce_dev_state hisi_qm_get_isolate_state= (struct uacce_device *uacce static int hisi_qm_isolate_threshold_write(struct uacce_device *uacce, u32= num) { struct hisi_qm *qm =3D uacce->priv; + int ret; =20 /* Must be set by PF */ if (uacce->is_vf) @@ -2792,6 +2813,18 @@ static int hisi_qm_isolate_threshold_write(struct ua= cce_device *uacce, u32 num) =20 /* After the policy is updated, need to reset the hardware err list */ qm_hw_err_destroy(qm); + + if (!qm->vfs_num) { + mutex_unlock(&qm->isolate_data.isolate_lock); + return 0; + } + + /* Notify all VFs to update the isolation threshold. */ + if (test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps)) { + ret =3D qm_ping_all_vfs(qm, QM_PF_SET_ISOLATE, qm->isolate_data.err_thre= shold); + if (ret) + dev_err(&qm->pdev->dev, "failed to send command to all VFs set isolate!= \n"); + } mutex_unlock(&qm->isolate_data.isolate_lock); =20 return 0; @@ -2802,7 +2835,7 @@ static u32 hisi_qm_isolate_threshold_read(struct uacc= e_device *uacce) struct hisi_qm *qm =3D uacce->priv; struct hisi_qm *pf_qm; =20 - if (uacce->is_vf) { + if (uacce->is_vf && !test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps)) { pf_qm =3D pci_get_drvdata(pci_physfn(qm->pdev)); return pf_qm->isolate_data.err_threshold; } @@ -2889,7 +2922,10 @@ static int qm_alloc_uacce(struct hisi_qm *qm) return -EINVAL; } =20 - uacce->is_vf =3D pdev->is_virtfn; + if (qm->fun_type =3D=3D QM_HW_PF) + uacce->is_vf =3D false; + else + uacce->is_vf =3D true; uacce->priv =3D qm; =20 if (qm->ver =3D=3D QM_HW_V1) @@ -2918,6 +2954,25 @@ static int qm_alloc_uacce(struct hisi_qm *qm) return 0; } =20 +int hisi_qm_register_uacce(struct hisi_qm *qm) +{ + int ret; + + if (!qm->uacce) + return 0; + + dev_info(&qm->pdev->dev, "qm register to uacce\n"); + + if (qm->fun_type =3D=3D QM_HW_VF && test_bit(QM_SUPPORT_MB_COMMAND, &qm->= caps)) { + ret =3D qm_ping_pf(qm, QM_VF_GET_ISOLATE); + if (ret) + dev_err(&qm->pdev->dev, "failed to send cmd to PF to get isolate!\n"); + } + + return uacce_register(qm->uacce); +} +EXPORT_SYMBOL_GPL(hisi_qm_register_uacce); + /** * qm_frozen() - Try to froze QM to cut continuous queue request. If * there is user on the QM, return failure without doing anything. @@ -4484,7 +4539,7 @@ static int qm_try_stop_vfs(struct hisi_qm *qm, enum q= m_ifc_cmd cmd, =20 /* Kunpeng930 supports to notify VFs to stop before PF reset */ if (test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps)) { - ret =3D qm_ping_all_vfs(qm, cmd); + ret =3D qm_ping_all_vfs(qm, cmd, 0); if (ret) pci_err(pdev, "failed to send command to all VFs before PF reset!\n"); } else { @@ -4671,6 +4726,7 @@ static int qm_vf_reset_done(struct hisi_qm *qm) static int qm_try_start_vfs(struct hisi_qm *qm, enum qm_ifc_cmd cmd) { struct pci_dev *pdev =3D qm->pdev; + u32 data; int ret; =20 if (!qm->vfs_num) @@ -4684,7 +4740,11 @@ static int qm_try_start_vfs(struct hisi_qm *qm, enum= qm_ifc_cmd cmd) =20 /* Kunpeng930 supports to notify VFs to start after PF reset. */ if (test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps)) { - ret =3D qm_ping_all_vfs(qm, cmd); + data =3D qm->isolate_data.err_threshold; + if (qm->isolate_data.is_isolate) + data |=3D QM_ISOLATED_STATE; + /* Broadcasting isolate info via RAS to all VFs. */ + ret =3D qm_ping_all_vfs(qm, cmd, data); if (ret) pci_warn(pdev, "failed to send cmd to all VFs after PF reset!\n"); } else { @@ -5131,10 +5191,22 @@ static void qm_pf_reset_vf_done(struct hisi_qm *qm) qm_reset_bit_clear(qm); } =20 -static int qm_wait_pf_reset_finish(struct hisi_qm *qm) +static void qm_vf_update_isolate_info(struct hisi_qm *qm, u32 data) +{ + /* Updating the local isolation status. */ + mutex_lock(&qm->isolate_data.isolate_lock); + if (data & QM_ISOLATED_STATE) + qm->isolate_data.is_isolate =3D true; + else + qm->isolate_data.is_isolate =3D false; + qm->isolate_data.err_threshold =3D data & QM_ISOLATED_THRESHOLD_MASK; + mutex_unlock(&qm->isolate_data.isolate_lock); +} + +static int qm_wait_pf_reset_finish(struct hisi_qm *qm, enum qm_stop_reason= stop_reason) { struct device *dev =3D &qm->pdev->dev; - u32 val, cmd; + u32 val, cmd, data; int ret; =20 /* Wait for reset to finish */ @@ -5151,7 +5223,7 @@ static int qm_wait_pf_reset_finish(struct hisi_qm *qm) * Whether message is got successfully, * VF needs to ack PF by clearing the interrupt. */ - ret =3D qm->ops->get_ifc(qm, &cmd, NULL, 0); + ret =3D qm->ops->get_ifc(qm, &cmd, &data, 0); qm_clear_cmd_interrupt(qm, 0); if (ret) { dev_err(dev, "failed to get command from PF in reset done!\n"); @@ -5160,10 +5232,14 @@ static int qm_wait_pf_reset_finish(struct hisi_qm *= qm) =20 if (cmd !=3D QM_PF_RESET_DONE) { dev_err(dev, "the command(0x%x) is not reset done!\n", cmd); - ret =3D -EINVAL; + return -EINVAL; } =20 - return ret; + /* The VF processes the device isolation information received from the RA= S reset. */ + if (stop_reason =3D=3D QM_SOFT_RESET) + qm_vf_update_isolate_info(qm, data); + + return 0; } =20 static void qm_pf_reset_vf_process(struct hisi_qm *qm, @@ -5178,7 +5254,7 @@ static void qm_pf_reset_vf_process(struct hisi_qm *qm, qm_cmd_uninit(qm); qm_pf_reset_vf_prepare(qm, stop_reason); =20 - ret =3D qm_wait_pf_reset_finish(qm); + ret =3D qm_wait_pf_reset_finish(qm, stop_reason); if (ret) goto err_get_status; =20 @@ -5189,10 +5265,31 @@ static void qm_pf_reset_vf_process(struct hisi_qm *= qm, return; =20 err_get_status: + if (stop_reason =3D=3D QM_SOFT_RESET) { + /* Update local isolation status on PF-VF reset failure. */ + mutex_lock(&qm->isolate_data.isolate_lock); + qm->isolate_data.is_isolate =3D true; + mutex_unlock(&qm->isolate_data.isolate_lock); + } qm_cmd_init(qm); qm_reset_bit_clear(qm); } =20 +static void qm_vf_get_isolate_data(struct hisi_qm *qm, u32 fun_num) +{ + u32 data =3D qm->isolate_data.err_threshold; + struct device *dev =3D &qm->pdev->dev; + int ret; + + if (qm->isolate_data.is_isolate) + data |=3D QM_ISOLATED_STATE; + + ret =3D qm_ping_single_vf(qm, QM_PF_SET_ISOLATE, data, fun_num); + if (ret) + dev_err(dev, "failed to send command(0x%x) to VF(%u)!\n", + (unsigned int)QM_PF_SET_ISOLATE, fun_num); +} + static void qm_handle_cmd_msg(struct hisi_qm *qm, u32 fun_num) { struct device *dev =3D &qm->pdev->dev; @@ -5224,6 +5321,13 @@ static void qm_handle_cmd_msg(struct hisi_qm *qm, u3= 2 fun_num) case QM_PF_SET_QOS: qm->mb_qos =3D data; break; + case QM_VF_GET_ISOLATE: + /* Read the isolation policy of the PF during VF initialization. */ + qm_vf_get_isolate_data(qm, fun_num); + break; + case QM_PF_SET_ISOLATE: + qm_vf_update_isolate_info(qm, data); + break; default: dev_err(dev, "unsupported command(0x%x) sent by function(%u)!\n", cmd, f= un_num); break; diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisi= licon/sec2/sec_main.c index 056bd8f4da5a..e8bea1e496f7 100644 --- a/drivers/crypto/hisilicon/sec2/sec_main.c +++ b/drivers/crypto/hisilicon/sec2/sec_main.c @@ -1449,12 +1449,10 @@ static int sec_probe(struct pci_dev *pdev, const st= ruct pci_device_id *id) goto err_qm_del_list; } =20 - if (qm->uacce) { - ret =3D uacce_register(qm->uacce); - if (ret) { - pci_err(pdev, "failed to register uacce (%d)!\n", ret); - goto err_alg_unregister; - } + ret =3D hisi_qm_register_uacce(qm); + if (ret) { + pci_err(pdev, "failed to register uacce (%d)!\n", ret); + goto err_alg_unregister; } =20 if (qm->fun_type =3D=3D QM_HW_PF && vfs_num) { diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisil= icon/zip/zip_main.c index 44df9c859bd8..5135b3028cb2 100644 --- a/drivers/crypto/hisilicon/zip/zip_main.c +++ b/drivers/crypto/hisilicon/zip/zip_main.c @@ -1559,12 +1559,10 @@ static int hisi_zip_probe(struct pci_dev *pdev, con= st struct pci_device_id *id) goto err_qm_del_list; } =20 - if (qm->uacce) { - ret =3D uacce_register(qm->uacce); - if (ret) { - pci_err(pdev, "failed to register uacce (%d)!\n", ret); - goto err_qm_alg_unregister; - } + ret =3D hisi_qm_register_uacce(qm); + if (ret) { + pci_err(pdev, "failed to register uacce (%d)!\n", ret); + goto err_qm_alg_unregister; } =20 if (qm->fun_type =3D=3D QM_HW_PF && vfs_num > 0) { diff --git a/include/linux/hisi_acc_qm.h b/include/linux/hisi_acc_qm.h index a6268dc4f7cb..ddecdc2531a2 100644 --- a/include/linux/hisi_acc_qm.h +++ b/include/linux/hisi_acc_qm.h @@ -552,6 +552,7 @@ static inline void hisi_qm_del_list(struct hisi_qm *qm,= struct hisi_qm_list *qm_ mutex_unlock(&qm_list->lock); } =20 +int hisi_qm_register_uacce(struct hisi_qm *qm); int hisi_qm_q_num_set(const char *val, const struct kernel_param *kp, unsigned int device); int hisi_qm_init(struct hisi_qm *qm); --=20 2.33.0 From nobody Mon May 25 05:13:58 2026 Received: from canpmsgout02.his.huawei.com (canpmsgout02.his.huawei.com [113.46.200.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6336B29346F; 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Mon, 18 May 2026 22:31:21 +0800 From: ZongYu Wu To: , CC: , , , , , , Subject: [PATCH 2/6] crypto: hisilicon/qm - place the interrupt status interface after the PM usage counter Date: Mon, 18 May 2026 22:29:52 +0800 Message-ID: <20260518142956.3593934-3-wuzongyu1@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260518142956.3593934-1-wuzongyu1@huawei.com> References: <20260518142956.3593934-1-wuzongyu1@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemr100008.china.huawei.com (7.202.195.119) Content-Type: text/plain; charset="utf-8" From: Zhushuai Yin To avoid accessing memory of a suspended device, and since the counter interface used by PM involves sleep operations, the counter interface cannot be placed in the interrupt top half. Therefore, the interface for acquiring the interrupt status in the RAS reset flow that resides in the interrupt context needs to be moved to the bottom half for processing. Signed-off-by: Zhushuai Yin Signed-off-by: Zongyu Wu --- drivers/crypto/hisilicon/qm.c | 34 ++++++++++++++++++---------------- include/linux/hisi_acc_qm.h | 1 - 2 files changed, 18 insertions(+), 17 deletions(-) diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index 9cf52873a891..71af462daf5b 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -1195,6 +1195,11 @@ static irqreturn_t qm_aeq_thread(int irq, void *data) =20 atomic64_inc(&qm->debug.dfx.aeq_irq_cnt); =20 + if (qm_pm_get_sync(qm)) { + dev_err(&qm->pdev->dev, "failed to get runtime PM for aeq handle\n"); + return IRQ_HANDLED; + } + while (QM_AEQE_PHASE(dw0) =3D=3D qm->status.aeqc_phase) { type =3D (dw0 >> QM_AEQE_TYPE_SHIFT) & QM_AEQE_TYPE_MASK; qp_id =3D dw0 & QM_AEQE_CQN_MASK; @@ -1230,6 +1235,8 @@ static irqreturn_t qm_aeq_thread(int irq, void *data) =20 qm_db(qm, 0, QM_DOORBELL_CMD_AEQ, qm->status.aeq_head, 0); =20 + qm_pm_put_sync(qm); + return IRQ_HANDLED; } =20 @@ -3043,9 +3050,9 @@ void hisi_qm_wait_task_finish(struct hisi_qm *qm, str= uct hisi_qm_list *qm_list) msleep(WAIT_PERIOD); } =20 - while (test_bit(QM_RST_SCHED, &qm->misc_ctl) || - test_bit(QM_RESETTING, &qm->misc_ctl)) - msleep(WAIT_PERIOD); + /* Cancel possible RAS reset process during the uninstallation procedure.= */ + if (qm->fun_type =3D=3D QM_HW_PF) + cancel_work_sync(&qm->rst_work); =20 if (test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps)) flush_work(&qm->cmd_process); @@ -4595,8 +4602,6 @@ static int qm_controller_reset_prepare(struct hisi_qm= *qm) if (ret) pci_err(pdev, "failed to stop by vfs in soft reset!\n"); =20 - clear_bit(QM_RST_SCHED, &qm->misc_ctl); - return 0; } =20 @@ -4914,7 +4919,6 @@ static int qm_controller_reset(struct hisi_qm *qm) if (ret) { hisi_qm_set_hw_reset(qm, QM_RESET_STOP_TX_OFFSET); hisi_qm_set_hw_reset(qm, QM_RESET_STOP_RX_OFFSET); - clear_bit(QM_RST_SCHED, &qm->misc_ctl); return ret; } =20 @@ -5087,14 +5091,13 @@ static irqreturn_t qm_rsvd_irq(int irq, void *data) static irqreturn_t qm_abnormal_irq(int irq, void *data) { struct hisi_qm *qm =3D data; - enum acc_err_result ret; =20 atomic64_inc(&qm->debug.dfx.abnormal_irq_cnt); - ret =3D qm_process_dev_error(qm); - if (ret =3D=3D ACC_ERR_NEED_RESET && - !test_bit(QM_DRIVER_REMOVING, &qm->misc_ctl) && - !test_and_set_bit(QM_RST_SCHED, &qm->misc_ctl)) + + if (!test_bit(QM_DRIVER_REMOVING, &qm->misc_ctl)) schedule_work(&qm->rst_work); + else + pci_warn(qm->pdev, "Driver is down, need to reload driver!\n"); =20 return IRQ_HANDLED; } @@ -5123,14 +5126,13 @@ static void hisi_qm_controller_reset(struct work_st= ruct *rst_work) =20 ret =3D qm_pm_get_sync(qm); if (ret) { - clear_bit(QM_RST_SCHED, &qm->misc_ctl); + dev_err(&qm->pdev->dev, "failed to get runtime PM for controller\n"); return; } =20 - /* reset pcie device controller */ - ret =3D qm_controller_reset(qm); - if (ret) - dev_err(&qm->pdev->dev, "controller reset failed (%d)\n", ret); + ret =3D qm_process_dev_error(qm); + if (ret =3D=3D ACC_ERR_NEED_RESET) + (void)qm_controller_reset(qm); =20 qm_pm_put_sync(qm); } diff --git a/include/linux/hisi_acc_qm.h b/include/linux/hisi_acc_qm.h index ddecdc2531a2..98ff6bcfdebe 100644 --- a/include/linux/hisi_acc_qm.h +++ b/include/linux/hisi_acc_qm.h @@ -158,7 +158,6 @@ enum qm_vf_state { =20 enum qm_misc_ctl_bits { QM_DRIVER_REMOVING =3D 0x0, - QM_RST_SCHED, QM_RESETTING, QM_MODULE_PARAM, }; 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Mon, 18 May 2026 22:23:42 +0800 (CST) Received: from kwepemr100008.china.huawei.com (unknown [7.202.195.119]) by mail.maildlp.com (Postfix) with ESMTPS id 0523C4056D; Mon, 18 May 2026 22:31:22 +0800 (CST) Received: from localhost.localdomain (10.50.163.32) by kwepemr100008.china.huawei.com (7.202.195.119) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.36; Mon, 18 May 2026 22:31:21 +0800 From: ZongYu Wu To: , CC: , , , , , , Subject: [PATCH 3/6] crypto: hisilicon/qm - support function-level error reset Date: Mon, 18 May 2026 22:29:53 +0800 Message-ID: <20260518142956.3593934-4-wuzongyu1@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260518142956.3593934-1-wuzongyu1@huawei.com> References: <20260518142956.3593934-1-wuzongyu1@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemr100008.china.huawei.com (7.202.195.119) Content-Type: text/plain; charset="utf-8" From: Zhushuai Yin When executing operations on crypto devices, hardware errors are inevitable. For certain errors, a full device reset is required to recover. However, in certain cases, only a specific function may fail, while other functions can still operate normally. A system-wide RAS reset in such cases would unnecessarily impact functioning components. This patch introduces function-level granularity handling, enabling targeted resets of only the error-reporting functions without affecting other operational functions. Signed-off-by: Zhushuai Yin Signed-off-by: Zongyu Wu --- drivers/crypto/hisilicon/qm.c | 90 +++++++++++++++++++++++++++++++---- include/linux/hisi_acc_qm.h | 1 + 2 files changed, 83 insertions(+), 8 deletions(-) diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index 71af462daf5b..2b3132595e42 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -246,6 +246,11 @@ #define QM_QOS_MAX_CIR_U 6 #define QM_AUTOSUSPEND_DELAY 3000 =20 +/* qm function err mask */ +#define QM_FUNC_AXI_ERR_ST0 0x100280 +#define QM_RAS_FUNC_ERROR (BIT(0) | BIT(1)) +#define QM_FUNC_RAS_CLEAR_ALL GENMASK(63, 0) + /* qm isolation state mask */ #define QM_ISOLATED_STATE BIT(31) #define QM_ISOLATED_THRESHOLD_MASK GENMASK(15, 0) @@ -314,6 +319,7 @@ enum qm_ifc_cmd { QM_VF_START_FAIL, QM_PF_SET_QOS, QM_VF_GET_QOS, + QM_FUNCTION_RESET, QM_VF_GET_ISOLATE, QM_PF_SET_ISOLATE, }; @@ -493,6 +499,7 @@ static struct qm_typical_qos_table shaper_cbs_s[] =3D { static void qm_irqs_unregister(struct hisi_qm *qm); static int qm_reset_device(struct hisi_qm *qm); static void hisi_qm_stop_qp(struct hisi_qp *qp); +static int qm_restart(struct hisi_qm *qm); =20 int hisi_qm_q_num_set(const char *val, const struct kernel_param *kp, unsigned int device) @@ -1171,18 +1178,20 @@ static void qm_reset_function(struct hisi_qm *qm) return; } =20 + dev_info(dev, "function reset start...\n"); ret =3D hisi_qm_stop(qm, QM_DOWN); if (ret) { dev_err(dev, "failed to stop qm when reset function\n"); goto clear_bit; } =20 - ret =3D hisi_qm_start(qm); + ret =3D qm_restart(qm); if (ret) dev_err(dev, "failed to start qm when reset function\n"); =20 clear_bit: qm_reset_bit_clear(qm); + dev_info(dev, "function reset end...\n"); } =20 static irqreturn_t qm_aeq_thread(int irq, void *data) @@ -1505,6 +1514,8 @@ static void qm_hw_error_cfg(struct hisi_qm *qm) qm->error_mask =3D qm_err->nfe | qm_err->ce | qm_err->fe; /* clear QM hw residual error source */ writel(qm->error_mask, qm->io_base + QM_ABNORMAL_INT_SOURCE); + if (qm->ver >=3D QM_HW_V5) + writeq(QM_FUNC_RAS_CLEAR_ALL, qm->io_base + QM_FUNC_AXI_ERR_ST0); =20 /* configure error type */ writel(qm_err->ce, qm->io_base + QM_RAS_CE_ENABLE); @@ -1610,6 +1621,15 @@ static enum acc_err_result qm_hw_error_handle_v2(str= uct hisi_qm *qm) qm->err_status.is_qm_ecc_mbit =3D true; =20 qm_log_hw_error(qm, error_status); + /* Trigger func reset only when error is detected in bit 0 or bit 1. */ + if ((qm->ver >=3D QM_HW_V5) && + (error_status & QM_RAS_FUNC_ERROR) && + (error_status & qm_err->reset_mask) =3D=3D 0) { + writel(error_status, qm->io_base + QM_ABNORMAL_INT_SOURCE); + writel(qm_err->nfe, qm->io_base + QM_RAS_NFE_ENABLE); + return ACC_ERR_NEED_FUNC_RESET; + } + if (error_status & qm_err->reset_mask) { /* Disable the same error reporting until device is recovered. */ writel(qm_err->nfe & (~error_status), qm->io_base + QM_RAS_NFE_ENABLE); @@ -4364,10 +4384,13 @@ static enum acc_err_result qm_process_dev_error(str= uct hisi_qm *qm) =20 /* log device error */ dev_ret =3D qm_dev_err_handle(qm); + if (qm_ret =3D=3D ACC_ERR_NEED_RESET || dev_ret =3D=3D ACC_ERR_NEED_RESET) + return ACC_ERR_NEED_RESET; + + if (qm_ret =3D=3D ACC_ERR_NEED_FUNC_RESET) + return ACC_ERR_NEED_FUNC_RESET; =20 - return (qm_ret =3D=3D ACC_ERR_NEED_RESET || - dev_ret =3D=3D ACC_ERR_NEED_RESET) ? - ACC_ERR_NEED_RESET : ACC_ERR_RECOVERED; + return ACC_ERR_RECOVERED; } =20 /** @@ -4392,7 +4415,7 @@ pci_ers_result_t hisi_qm_dev_err_detected(struct pci_= dev *pdev, return PCI_ERS_RESULT_DISCONNECT; =20 ret =3D qm_process_dev_error(qm); - if (ret =3D=3D ACC_ERR_NEED_RESET) + if (ret =3D=3D ACC_ERR_NEED_RESET || ret =3D=3D ACC_ERR_NEED_FUNC_RESET) return PCI_ERS_RESULT_NEED_RESET; =20 return PCI_ERS_RESULT_RECOVERED; @@ -5119,9 +5142,53 @@ void hisi_qm_dev_shutdown(struct pci_dev *pdev) } EXPORT_SYMBOL_GPL(hisi_qm_dev_shutdown); =20 +static u64 qm_get_function_mask(struct hisi_qm *qm) +{ + return readq(qm->io_base + QM_FUNC_AXI_ERR_ST0); +} + +static void qm_clear_function_mask(struct hisi_qm *qm, u64 func_mask) +{ + /* Register write 1 clear */ + writeq(func_mask, qm->io_base + QM_FUNC_AXI_ERR_ST0); +} + +static void qm_function_reset(struct hisi_qm *qm) +{ + struct device *dev =3D &qm->pdev->dev; + u64 func_mask; + u32 fun_num; + int ret; + + func_mask =3D qm_get_function_mask(qm); + if (!func_mask) { + dev_info(dev, "no function need reset!\n"); + return; + } + + for (fun_num =3D 1; fun_num <=3D qm->vfs_num; fun_num++) { + if (func_mask & BIT(fun_num)) { + ret =3D qm_ping_single_vf(qm, QM_FUNCTION_RESET, 0, fun_num); + /* When function ping fail, user decides the VF reset method. */ + if (ret) + dev_err(dev, "failed to send command(0x%x) to VF(%u)!\n", + (unsigned int)QM_FUNCTION_RESET, fun_num); + } + } + + if (func_mask & BIT(0)) { + dev_info(dev, "function reset start...\n"); + qm_reset_function(qm); + dev_info(dev, "function reset end!\n"); + } + + qm_clear_function_mask(qm, func_mask); +} + static void hisi_qm_controller_reset(struct work_struct *rst_work) { struct hisi_qm *qm =3D container_of(rst_work, struct hisi_qm, rst_work); + enum acc_err_result err_result; int ret; =20 ret =3D qm_pm_get_sync(qm); @@ -5130,9 +5197,11 @@ static void hisi_qm_controller_reset(struct work_str= uct *rst_work) return; } =20 - ret =3D qm_process_dev_error(qm); - if (ret =3D=3D ACC_ERR_NEED_RESET) + err_result =3D qm_process_dev_error(qm); + if (err_result =3D=3D ACC_ERR_NEED_RESET) (void)qm_controller_reset(qm); + else if (err_result =3D=3D ACC_ERR_NEED_FUNC_RESET) + qm_function_reset(qm); =20 qm_pm_put_sync(qm); } @@ -5179,7 +5248,7 @@ static void qm_pf_reset_vf_done(struct hisi_qm *qm) int ret; =20 pci_restore_state(pdev); - ret =3D hisi_qm_start(qm); + ret =3D qm_restart(qm); if (ret) { dev_err(&pdev->dev, "failed to start QM, ret =3D %d.\n", ret); cmd =3D QM_VF_START_FAIL; @@ -5323,6 +5392,11 @@ static void qm_handle_cmd_msg(struct hisi_qm *qm, u3= 2 fun_num) case QM_PF_SET_QOS: qm->mb_qos =3D data; break; + case QM_FUNCTION_RESET: + dev_info(dev, "function reset start...\n"); + qm_reset_function(qm); + dev_info(dev, "function reset end!\n"); + break; case QM_VF_GET_ISOLATE: /* Read the isolation policy of the PF during VF initialization. */ qm_vf_get_isolate_data(qm, fun_num); diff --git a/include/linux/hisi_acc_qm.h b/include/linux/hisi_acc_qm.h index 98ff6bcfdebe..0a2da1029a3f 100644 --- a/include/linux/hisi_acc_qm.h +++ b/include/linux/hisi_acc_qm.h @@ -248,6 +248,7 @@ enum acc_err_result { ACC_ERR_NONE, ACC_ERR_NEED_RESET, ACC_ERR_RECOVERED, + ACC_ERR_NEED_FUNC_RESET, }; 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charset="utf-8" From: Weili Qian Before function level reset, driver first disable device error report and then waits for the device reset to complete. However, when the error is recovered, the error bits will be enabled again, resulting in invalid disable. It is modified to detect that there is no error before disable error report, and then do FLR. Fixes: 7ce396fa12a9 ("crypto: hisilicon - add FLR support") Signed-off-by: Weili Qian Signed-off-by: Zongyu Wu --- drivers/crypto/hisilicon/qm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index 2b3132595e42..90b447b934c6 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -5004,8 +5004,6 @@ void hisi_qm_reset_prepare(struct pci_dev *pdev) u32 delay =3D 0; int ret; =20 - hisi_qm_dev_err_uninit(pf_qm); - /* * Check whether there is an ECC mbit error, If it occurs, need to * wait for soft reset to fix it. @@ -5022,6 +5020,8 @@ void hisi_qm_reset_prepare(struct pci_dev *pdev) return; } =20 + hisi_qm_dev_err_uninit(pf_qm); + /* PF obtains the information of VF by querying the register. */ if (qm->fun_type =3D=3D QM_HW_PF) qm_cmd_uninit(qm); --=20 2.33.0 From nobody Mon May 25 05:13:58 2026 Received: from canpmsgout02.his.huawei.com (canpmsgout02.his.huawei.com [113.46.200.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65E4C2C3244; Mon, 18 May 2026 14:31:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.217 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779114691; cv=none; b=qPGmscedv4GqfnyP5fgzO8LfEgidC1GsavD7479YD0f7XFQTCSaQNMBXYif9RNp7071YhL6yXnnXUhhCsrUgZ7qo6lpxk55VnG1FSkyaDl+erBlsDBOCLTFvJL2Nl7gvkLP0K4rpxGA/DoF+HZOaL9/ufHIS8Y8QxUE/Jp8nOZo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779114691; c=relaxed/simple; bh=rNQZz1Pk3AFcWq7hWC8RyDtq/M93duNNUUiZQ17ZkrI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TKtxpg5y/D0jdd9pz59aqfPI2tTYfghoFTuCpmDSS6Vq3kWX4Z6hlBpMz8CY1OfJbKXZhIC/J5+V41sHHL72kPuh3xCNIeOuHpV+jeqUy/7Sid3y0FWbekmh6T28xGmKjZXPyhUtft9hA1u/IUCHLn7JTPUcPzbjdB28oa/wFUI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=MSNhITbF; arc=none smtp.client-ip=113.46.200.217 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="MSNhITbF" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=Haii3oyNo3W/HLHEmJWCWcR06NTtGEdS6MRylW8BA6E=; b=MSNhITbFwYYJBKoBOB+2nzbIU2d1O/N/Vb5GEOJ32xn0R03QSLimYfW2r2hOGDOq4Vf2psFRB uEmYKKFNrxhDqwLo/BHp2VWX5se/Lg+gEjszaO0GVdzZgELPWK663qxTmfrd0aPhDMzF4RPqa/9 t8g2b62CsTY8eqH+cVIDTwQ= Received: from mail.maildlp.com (unknown [172.19.163.104]) by canpmsgout02.his.huawei.com (SkyGuard) with ESMTPS id 4gK0RC5sb7zcb14; Mon, 18 May 2026 22:23:51 +0800 (CST) Received: from kwepemr100008.china.huawei.com (unknown [7.202.195.119]) by mail.maildlp.com (Postfix) with ESMTPS id 987994048F; Mon, 18 May 2026 22:31:22 +0800 (CST) Received: from localhost.localdomain (10.50.163.32) by kwepemr100008.china.huawei.com (7.202.195.119) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.36; Mon, 18 May 2026 22:31:22 +0800 From: ZongYu Wu To: , CC: , , , , , , Subject: [PATCH 5/6] crypto: hisilicon - mask all error type when removing driver Date: Mon, 18 May 2026 22:29:55 +0800 Message-ID: <20260518142956.3593934-6-wuzongyu1@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260518142956.3593934-1-wuzongyu1@huawei.com> References: <20260518142956.3593934-1-wuzongyu1@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemr100008.china.huawei.com (7.202.195.119) Content-Type: text/plain; charset="utf-8" From: Weili Qian Each bit in the error interrupt register corresponds to a specific error type. A bit value of 0 enables the interrupt, and a bit value of 1 disables the interrupt. Currently, when disabling interrupts, it incorrectly enables the interrupt types that were not enabled. Therefore, when disabling interrupts, all bits should be directly written to 1. Signed-off-by: Weili Qian Signed-off-by: Zongyu Wu --- drivers/crypto/hisilicon/hpre/hpre_main.c | 9 +++---- drivers/crypto/hisilicon/qm.c | 30 ++++++----------------- drivers/crypto/hisilicon/sec2/sec_main.c | 3 ++- drivers/crypto/hisilicon/zip/zip_main.c | 10 +++----- 4 files changed, 18 insertions(+), 34 deletions(-) diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c b/drivers/crypto/his= ilicon/hpre/hpre_main.c index a484381f522a..b6903fce6071 100644 --- a/drivers/crypto/hisilicon/hpre/hpre_main.c +++ b/drivers/crypto/hisilicon/hpre/hpre_main.c @@ -55,6 +55,8 @@ #define HPRE_RAS_FE_ENB 0x301418 #define HPRE_OOO_SHUTDOWN_SEL 0x301a3c #define HPRE_HAC_RAS_FE_ENABLE 0 +#define HPRE_RAS_MASK_ALL GENMASK(31, 0) +#define HPRE_RAS_CLEAR_ALL GENMASK(31, 0) =20 #define HPRE_CORE_ENB (HPRE_CLSTR_BASE + HPRE_CORE_EN_OFFSET) #define HPRE_CORE_INI_CFG (HPRE_CLSTR_BASE + HPRE_CORE_INI_CFG_OFFSET) @@ -820,11 +822,8 @@ static void hpre_master_ooo_ctrl(struct hisi_qm *qm, b= ool enable) =20 static void hpre_hw_error_disable(struct hisi_qm *qm) { - struct hisi_qm_err_mask *dev_err =3D &qm->err_info.dev_err; - u32 err_mask =3D dev_err->ce | dev_err->nfe | dev_err->fe; - /* disable hpre hw error interrupts */ - writel(err_mask, qm->io_base + HPRE_INT_MASK); + writel(HPRE_RAS_MASK_ALL, qm->io_base + HPRE_INT_MASK); /* disable HPRE block master OOO when nfe occurs on Kunpeng930 */ hpre_master_ooo_ctrl(qm, false); } @@ -835,7 +834,7 @@ static void hpre_hw_error_enable(struct hisi_qm *qm) u32 err_mask =3D dev_err->ce | dev_err->nfe | dev_err->fe; =20 /* clear HPRE hw error source if having */ - writel(err_mask, qm->io_base + HPRE_HAC_SOURCE_INT); + writel(HPRE_RAS_CLEAR_ALL, qm->io_base + HPRE_HAC_SOURCE_INT); =20 /* configure error type */ writel(dev_err->ce, qm->io_base + HPRE_RAS_CE_ENB); diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index 90b447b934c6..bfee16503c38 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -128,7 +128,6 @@ =20 #define QM_ABNORMAL_INT_SOURCE 0x100000 #define QM_ABNORMAL_INT_MASK 0x100004 -#define QM_ABNORMAL_INT_MASK_VALUE 0x7fff #define QM_ABNORMAL_INT_STATUS 0x100008 #define QM_ABNORMAL_INT_SET 0x10000c #define QM_ABNORMAL_INF00 0x100010 @@ -153,6 +152,8 @@ #define QM_DB_TIMEOUT BIT(10) #define QM_OF_FIFO_OF BIT(11) #define QM_RAS_AXI_ERROR (BIT(0) | BIT(1) | BIT(12)) +#define QM_RAS_MASK_ALL GENMASK(31, 0) +#define QM_RAS_CLEAR_ALL GENMASK(31, 0) =20 #define QM_RESET_WAIT_TIMEOUT 400 #define QM_PEH_VENDOR_ID 0x1000d8 @@ -1504,7 +1505,7 @@ static int qm_get_vft_v2(struct hisi_qm *qm, u32 *bas= e, u32 *number) =20 static void qm_hw_error_init_v1(struct hisi_qm *qm) { - writel(QM_ABNORMAL_INT_MASK_VALUE, qm->io_base + QM_ABNORMAL_INT_MASK); + writel(QM_RAS_MASK_ALL, qm->io_base + QM_ABNORMAL_INT_MASK); } =20 static void qm_hw_error_cfg(struct hisi_qm *qm) @@ -1513,7 +1514,7 @@ static void qm_hw_error_cfg(struct hisi_qm *qm) =20 qm->error_mask =3D qm_err->nfe | qm_err->ce | qm_err->fe; /* clear QM hw residual error source */ - writel(qm->error_mask, qm->io_base + QM_ABNORMAL_INT_SOURCE); + writel(QM_RAS_CLEAR_ALL, qm->io_base + QM_ABNORMAL_INT_SOURCE); if (qm->ver >=3D QM_HW_V5) writeq(QM_FUNC_RAS_CLEAR_ALL, qm->io_base + QM_FUNC_AXI_ERR_ST0); =20 @@ -1526,43 +1527,28 @@ static void qm_hw_error_cfg(struct hisi_qm *qm) =20 static void qm_hw_error_init_v2(struct hisi_qm *qm) { - u32 irq_unmask; - qm_hw_error_cfg(qm); =20 - irq_unmask =3D ~qm->error_mask; - irq_unmask &=3D readl(qm->io_base + QM_ABNORMAL_INT_MASK); - writel(irq_unmask, qm->io_base + QM_ABNORMAL_INT_MASK); + writel(~qm->error_mask, qm->io_base + QM_ABNORMAL_INT_MASK); } =20 static void qm_hw_error_uninit_v2(struct hisi_qm *qm) { - u32 irq_mask =3D qm->error_mask; - - irq_mask |=3D readl(qm->io_base + QM_ABNORMAL_INT_MASK); - writel(irq_mask, qm->io_base + QM_ABNORMAL_INT_MASK); + writel(QM_RAS_MASK_ALL, qm->io_base + QM_ABNORMAL_INT_MASK); } =20 static void qm_hw_error_init_v3(struct hisi_qm *qm) { - u32 irq_unmask; - qm_hw_error_cfg(qm); =20 /* enable close master ooo when hardware error happened */ writel(qm->err_info.qm_err.shutdown_mask, qm->io_base + QM_OOO_SHUTDOWN_S= EL); - - irq_unmask =3D ~qm->error_mask; - irq_unmask &=3D readl(qm->io_base + QM_ABNORMAL_INT_MASK); - writel(irq_unmask, qm->io_base + QM_ABNORMAL_INT_MASK); + writel(~qm->error_mask, qm->io_base + QM_ABNORMAL_INT_MASK); } =20 static void qm_hw_error_uninit_v3(struct hisi_qm *qm) { - u32 irq_mask =3D qm->error_mask; - - irq_mask |=3D readl(qm->io_base + QM_ABNORMAL_INT_MASK); - writel(irq_mask, qm->io_base + QM_ABNORMAL_INT_MASK); + writel(QM_RAS_MASK_ALL, qm->io_base + QM_ABNORMAL_INT_MASK); =20 /* disable close master ooo when hardware error happened */ writel(0x0, qm->io_base + QM_OOO_SHUTDOWN_SEL); diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisi= licon/sec2/sec_main.c index e8bea1e496f7..752565200c16 100644 --- a/drivers/crypto/hisilicon/sec2/sec_main.c +++ b/drivers/crypto/hisilicon/sec2/sec_main.c @@ -48,6 +48,7 @@ #define SEC_OOO_SHUTDOWN_SEL 0x301014 #define SEC_RAS_DISABLE 0x0 #define SEC_AXI_ERROR_MASK (BIT(0) | BIT(1)) +#define SEC_RAS_CLEAR_ALL GENMASK(31, 0) =20 #define SEC_MEM_START_INIT_REG 0x301100 #define SEC_MEM_INIT_DONE_REG 0x301104 @@ -752,7 +753,7 @@ static void sec_hw_error_enable(struct hisi_qm *qm) } =20 /* clear SEC hw error source if having */ - writel(err_mask, qm->io_base + SEC_CORE_INT_SOURCE); + writel(SEC_RAS_CLEAR_ALL, qm->io_base + SEC_CORE_INT_SOURCE); =20 /* enable RAS int */ writel(dev_err->ce, qm->io_base + SEC_RAS_CE_REG); diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisil= icon/zip/zip_main.c index 5135b3028cb2..706a73656977 100644 --- a/drivers/crypto/hisilicon/zip/zip_main.c +++ b/drivers/crypto/hisilicon/zip/zip_main.c @@ -64,7 +64,8 @@ #define HZIP_OOO_SHUTDOWN_SEL 0x30120C #define HZIP_SRAM_ECC_ERR_NUM_SHIFT 16 #define HZIP_SRAM_ECC_ERR_ADDR_SHIFT 24 -#define HZIP_CORE_INT_MASK_ALL GENMASK(12, 0) +#define HZIP_CORE_INT_MASK_ALL GENMASK(31, 0) +#define HZIP_CORE_RAS_CLEAR_ALL GENMASK(31, 0) #define HZIP_AXI_ERROR_MASK (BIT(2) | BIT(3)) #define HZIP_SQE_SIZE 128 #define HZIP_PF_DEF_Q_NUM 64 @@ -696,7 +697,7 @@ static void hisi_zip_hw_error_enable(struct hisi_qm *qm) } =20 /* clear ZIP hw error source if having */ - writel(err_mask, qm->io_base + HZIP_CORE_INT_SOURCE); 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Mon, 18 May 2026 22:31:22 +0800 From: ZongYu Wu To: , CC: , , , , , , Subject: [PATCH 6/6] crypto: hisilicon/qm - support doorbell enable control Date: Mon, 18 May 2026 22:29:56 +0800 Message-ID: <20260518142956.3593934-7-wuzongyu1@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260518142956.3593934-1-wuzongyu1@huawei.com> References: <20260518142956.3593934-1-wuzongyu1@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemr100008.china.huawei.com (7.202.195.119) Content-Type: text/plain; charset="utf-8" From: Zongyu Wu The driver notifies the hardware to handle task through doorbell. Currently, doorbell is enabled by default. To prevent the process from sending doorbells during hardware reset scenarios, which could cause the hardware to process doorbells and trigger new errors: For example, when the physical machine is resetting the device, doorbells are still being sent from the virtual machine. Therefore, the driver disables doorbell during hardware unavailability. After hardware initialization is completed, doorbell is enabled, and any task sent during the unavailability period will return errors. The hardware supports the PF to disable doorbells for all functions, while the VF can only disable its own doorbell function. When the PF is reset, it will disable doorbells for all functions. When VF is reset, it only disables its own doorbell and does not affect tasks on other functions. Signed-off-by: Zongyu Wu --- drivers/crypto/hisilicon/qm.c | 54 +++++++++++++++++++++++++++++++---- include/linux/hisi_acc_qm.h | 12 ++++++++ 2 files changed, 61 insertions(+), 5 deletions(-) diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index bfee16503c38..a951d2ef7833 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -247,6 +247,11 @@ #define QM_QOS_MAX_CIR_U 6 #define QM_AUTOSUSPEND_DELAY 3000 =20 +#define QM_DB_DROP_ALL_FUNC_ENABLE GENMASK(63, 0) +#define QM_DB_DROP_ALL_FUNC_DISABLE 0 +#define QM_DEV_DB_DROP 0x0100250 +#define QM_FUN_DB_DROP 0x0038 + /* qm function err mask */ #define QM_FUNC_AXI_ERR_ST0 0x100280 #define QM_RAS_FUNC_ERROR (BIT(0) | BIT(1)) @@ -577,6 +582,29 @@ static int qm_wait_reset_finish(struct hisi_qm *qm) return 0; } =20 +static void qm_fun_db_ctrl(struct hisi_qm *qm, bool enable) +{ + u32 val; + + if (qm->ver >=3D QM_HW_V5) { + val =3D readl(qm->io_base + QM_FUN_DB_DROP); + val =3D enable ? (val | BIT(0)) : (val & ~BIT(0)); + + writel(val, qm->io_base + QM_FUN_DB_DROP); + } +} + +static void qm_dev_db_ctrl(struct hisi_qm *qm, bool enable) +{ + u64 val; + + if (qm->ver >=3D QM_HW_V5 && qm->fun_type =3D=3D QM_HW_PF) { + val =3D enable ? QM_DB_DROP_ALL_FUNC_ENABLE : QM_DB_DROP_ALL_FUNC_DISABL= E; + + writeq(val, qm->io_base + QM_DEV_DB_DROP); + } +} + static int qm_reset_prepare_ready(struct hisi_qm *qm) { struct pci_dev *pdev =3D qm->pdev; @@ -3434,6 +3462,9 @@ static int __hisi_qm_start(struct hisi_qm *qm) if (ret) return ret; =20 + /* Enables the doorbell function when the device is enabled. */ + qm_dev_db_ctrl(qm, false); + qm_fun_db_ctrl(qm, false); qm_init_prefetch(qm); qm_enable_eq_aeq_interrupts(qm); =20 @@ -3541,7 +3572,7 @@ static void qm_invalid_queues(struct hisi_qm *qm) if (qm->status.stop_reason =3D=3D QM_NORMAL) return; =20 - if (qm->status.stop_reason =3D=3D QM_DOWN) + if (qm->status.stop_reason =3D=3D QM_DOWN || qm->status.stop_reason =3D= =3D QM_SHUTDOWN) hisi_qm_cache_wb(qm); =20 for (i =3D 0; i < qm->qp_num; i++) { @@ -3585,6 +3616,8 @@ int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_rea= son r) =20 if (qm->status.stop_reason !=3D QM_NORMAL) { hisi_qm_set_hw_reset(qm, QM_RESET_STOP_TX_OFFSET); + if (qm->status.stop_reason !=3D QM_SHUTDOWN) + qm_fun_db_ctrl(qm, true); /* * When performing soft reset, the hardware will no longer * do tasks, and the tasks in the device will be flushed @@ -4611,6 +4644,8 @@ static int qm_controller_reset_prepare(struct hisi_qm= *qm) if (ret) pci_err(pdev, "failed to stop by vfs in soft reset!\n"); =20 + qm_dev_db_ctrl(qm, true); + return 0; } =20 @@ -5019,16 +5054,25 @@ void hisi_qm_reset_prepare(struct pci_dev *pdev) ret =3D hisi_qm_stop(qm, QM_DOWN); if (ret) { pci_err(pdev, "Failed to stop QM, ret =3D %d.\n", ret); - hisi_qm_set_hw_reset(qm, QM_RESET_STOP_TX_OFFSET); - hisi_qm_set_hw_reset(qm, QM_RESET_STOP_RX_OFFSET); - return; + goto err_prepare; } =20 ret =3D qm_wait_vf_prepare_finish(qm); if (ret) pci_err(pdev, "failed to stop by vfs in FLR!\n"); =20 + qm_dev_db_ctrl(qm, true); + pci_info(pdev, "FLR resetting...\n"); + + return; + +err_prepare: + pci_info(pdev, "FLR resetting prepare failed!\n"); + atomic_set(&qm->status.flags, QM_STOP); + hisi_qm_set_hw_reset(qm, QM_RESET_STOP_TX_OFFSET); + hisi_qm_set_hw_reset(qm, QM_RESET_STOP_RX_OFFSET); + qm_dev_db_ctrl(qm, true); } EXPORT_SYMBOL_GPL(hisi_qm_reset_prepare); =20 @@ -5122,7 +5166,7 @@ void hisi_qm_dev_shutdown(struct pci_dev *pdev) struct hisi_qm *qm =3D pci_get_drvdata(pdev); int ret; =20 - ret =3D hisi_qm_stop(qm, QM_DOWN); + ret =3D hisi_qm_stop(qm, QM_SHUTDOWN); if (ret) dev_err(&pdev->dev, "Fail to stop qm in shutdown!\n"); } diff --git a/include/linux/hisi_acc_qm.h b/include/linux/hisi_acc_qm.h index 0a2da1029a3f..f7570a409905 100644 --- a/include/linux/hisi_acc_qm.h +++ b/include/linux/hisi_acc_qm.h @@ -115,10 +115,22 @@ =20 #define QM_ECC_MBIT BIT(2) =20 +/** + * enum qm_stop_reason - Queue manager stop reasons + * @QM_NORMAL: Graceful stop. Used for device unbind, driver removal, + * or runtime power management (runtime_suspend). + * @QM_SOFT_RESET: Error recovery reset. Triggered by unrecoverable hardw= are + * errors (e.g., PCIe AER, timeout) to recover device sta= te. + * @QM_DOWN: Function Level Reset. Used when the device needs to + * be reset at the function level without resetting the l= ink. + * @QM_SHUTDOWN: System shutdown. Used during system poweroff, reboot, = or + * kexec to ensure hardware is in a safe state. + */ enum qm_stop_reason { QM_NORMAL, QM_SOFT_RESET, QM_DOWN, + QM_SHUTDOWN, }; =20 enum qm_state { --=20 2.33.0