From nobody Mon May 25 05:12:26 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E570544102B for ; Mon, 18 May 2026 12:48:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779108537; cv=none; b=FT0aassPw1+16UtZl3/QANqhuqoOm9Vp/OhfBgBroEjChWkQOEQnVgVDx6Qxei8T+FIBq054/b43bctuW9g++ZS+/J8Gyu+JoeeuZgvLnHZfTELmlfnpaGPNwmNCkwHBcKqb/1dAMxEkUq0xFLj4wbJfLeBXdPIgDGN4VzSU6Us= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779108537; c=relaxed/simple; bh=lgomjevE6L8ROHcIL0ZW348lJl5Cm6rGy50dkWZx6LQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PWpHqvDbN9a93uJnQ32/wmRYKglB6IHjPMRC529IPsC1kn2vSrQbLrnjDHrWczz2odiAhUJ5Izjaq9J6xKYM1ZFlSY6QCr3/lMyZkTJQXjtpIXK1Uv6x9usVwhkGMxDYzdpciMNNsGTyWvzPMsl7NKStWq/GdrSvrnVcWqPGF8s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=ejjkYJBU; arc=none smtp.client-ip=170.10.129.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="ejjkYJBU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1779108535; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jC9H6hmJXtSXL1EjWfLGQfbsnaDczL2sh7s4JzF3p5E=; b=ejjkYJBUochRfumePZqFxgXBBOrHYrPuOF2KrBPVpE8L5qhQ3pgAPf5fduf38blEFQbZTK 81f6eBuMJLB8BVXNEcq3XT+hvEylOHq9FwteI83KqUaPQJAqNnrbPkUWgXQ+4zMASmiST1 VE5IPb06g/bZATnM46oyOpK60EWLyrI= Received: from mx-prod-mc-01.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-633-nUrOlvLROu-xBv6q9WHtdQ-1; Mon, 18 May 2026 08:48:51 -0400 X-MC-Unique: nUrOlvLROu-xBv6q9WHtdQ-1 X-Mimecast-MFC-AGG-ID: nUrOlvLROu-xBv6q9WHtdQ_1779108530 Received: from mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.17]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 9054919560A5; Mon, 18 May 2026 12:48:50 +0000 (UTC) Received: from fedora.redhat.com (unknown [10.44.32.67]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id D50D41956053; Mon, 18 May 2026 12:48:48 +0000 (UTC) From: Jose Ignacio Tornos Martinez To: bhelgaas@google.com, alex@shazbot.org Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Jose Ignacio Tornos Martinez Subject: [PATCH v4 1/3] PCI: Add d3cold as general reset method Date: Mon, 18 May 2026 14:48:33 +0200 Message-ID: <20260518124836.460805-2-jtornosm@redhat.com> In-Reply-To: <20260518124836.460805-1-jtornosm@redhat.com> References: <20260518124836.460805-1-jtornosm@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Content-Type: text/plain; charset="utf-8" Add D3cold power cycle as a general PCI reset method for single-function devices on platforms with ACPI _PR3 power resources. This provides true power cycle reset capability when the platform can physically cut power to the device. The implementation strictly requires _PR3 to be present - the platform must be able to control device power. This ensures d3cold only attempts true power cycling, not falling back to D3hot transitions. D3cold reset is placed at the end of the reset hierarchy since it requires specific platform support and should be tried after standard methods. Reset hierarchy with this change: 1. device_specific 2. acpi 3. flr 4. af_flr 5. pm (D3hot via config space, checks NoSoftRst) 6. bus (SBR) 7. cxl_bus 8. d3cold (NEW - true power cycle, requires _PR3) This benefits: - Platforms with _PR3 support - Single-function devices needing true power cycle - VFIO passthrough scenarios where FLR/PM unavailable Signed-off-by: Jose Ignacio Tornos Martinez --- v4: Strict _PR3 requirement - no D3hot fallback (Alex Williamson and Lukas Wunner feedback) v3: https://lore.kernel.org/all/20260513122349.268753-1-jtornosm@redhat.com= /=20 drivers/pci/pci.c | 40 ++++++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 2 +- 2 files changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 8f7cfcc00090..839903b59698 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4491,6 +4491,45 @@ static int pci_pm_reset(struct pci_dev *dev, bool pr= obe) return ret; } =20 +/** + * pci_d3cold_reset - Put device into D3cold and back to D0 for reset + * @dev: PCI device to reset + * @probe: if true, check if D3cold reset is supported; if false, perform = reset + * + * Reset the device by transitioning through D3cold (actual power removal = via + * platform power control) and back to D0. This requires ACPI _PR3 power + * resources to be present - the platform must be able to physically cut p= ower + * to the device. + * + * Only available for single-function devices to avoid affecting other + * functions in multi-function devices. + * + * Returns 0 if device can be/was reset this way, -ENOTTY if not supported, + * or other negative error code on failure. + */ +static int pci_d3cold_reset(struct pci_dev *dev, bool probe) +{ + int ret; + + if (dev->multifunction) + return -ENOTTY; + + if (!pci_pr3_present(dev)) + return -ENOTTY; + + if (probe) + return 0; + + if (dev->current_state !=3D PCI_D0) + return -EINVAL; + + ret =3D pci_set_power_state(dev, PCI_D3cold); + if (ret) + return ret; + + return pci_set_power_state(dev, PCI_D0); +} + /** * pcie_wait_for_link_status - Wait for link status change * @pdev: Device whose link to wait for. @@ -5065,6 +5104,7 @@ const struct pci_reset_fn_method pci_reset_fn_methods= [] =3D { { pci_pm_reset, .name =3D "pm" }, { pci_reset_bus_function, .name =3D "bus" }, { cxl_reset_bus_function, .name =3D "cxl_bus" }, + { pci_d3cold_reset, .name =3D "d3cold" }, }; =20 /** diff --git a/include/linux/pci.h b/include/linux/pci.h index 2c4454583c11..1ca7b880ead7 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -51,7 +51,7 @@ PCI_STATUS_PARITY) =20 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */ -#define PCI_NUM_RESET_METHODS 8 +#define PCI_NUM_RESET_METHODS 9 =20 #define PCI_RESET_PROBE true #define PCI_RESET_DO_RESET false --=20 2.54.0 From nobody Mon May 25 05:12:26 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0FD043E494 for ; Mon, 18 May 2026 12:48:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779108541; cv=none; b=OzVwRVb98QPzy+tteytoRxP+hcO2mneKP8c5Eog+NpIMMkrghTF7c+S4B2Ym/O2qLpQvPq6jo8806cz3l1GWQ93hhL6C/o1UvY8Rl9+UWJJlv7gynhWTm2aHXZeQkV/JzYwZxABgpW0P8r6WhrwK29uDMTwKr5q5a2i8/iFX3VU= ARC-Message-Signature: i=1; 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Mon, 18 May 2026 12:48:54 +0000 (UTC) Received: from fedora.redhat.com (unknown [10.44.32.67]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 9B4581956053; Mon, 18 May 2026 12:48:52 +0000 (UTC) From: Jose Ignacio Tornos Martinez To: bhelgaas@google.com, alex@shazbot.org Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Jose Ignacio Tornos Martinez Subject: [PATCH v4 2/3] PCI: Add soft reset method as last resort Date: Mon, 18 May 2026 14:48:34 +0200 Message-ID: <20260518124836.460805-3-jtornosm@redhat.com> In-Reply-To: <20260518124836.460805-1-jtornosm@redhat.com> References: <20260518124836.460805-1-jtornosm@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Content-Type: text/plain; charset="utf-8" Add a software-initiated "soft" reset method that attempts D3hot->D0 transition as an absolute last resort when all other reset methods have failed. Some devices incorrectly advertise NoSoftRst+ (blocking PM reset) but the D3hot transition does provide sufficient reset for certain use cases, particularly VFIO passthrough scenarios. This method provides a "better than nothing" option when the device would otherwise have no reset capability. The method only becomes available when: - pci_pm_reset() is unavailable (typically blocked by NoSoftRst+) - pci_d3cold_reset() is unavailable (no platform _PR3 support) - Device has PM capability (required for D3hot transition) Extract the D3hot transition logic into a shared helper function (pci_do_d3hot_transition) used by both pci_pm_reset and pci_soft_reset. Reset hierarchy with this change: 1. device_specific 2. acpi 3. flr 4. af_flr 5. pm (proper method, checks NoSoftRst) 6. bus 7. cxl_bus 8. d3cold (requires _PR3) 9. soft (NEW - D3hot without NoSoftRst check, absolute last resort) Signed-off-by: Jose Ignacio Tornos Martinez --- v4: Implements D3hot transition as last resort when pm/d3cold unavailable v3: https://lore.kernel.org/all/20260513122349.268753-1-jtornosm@redhat.com/ drivers/pci/pci.c | 98 ++++++++++++++++++++++++++++++++++----------- include/linux/pci.h | 2 +- 2 files changed, 76 insertions(+), 24 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 839903b59698..8dad386bd65d 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4437,6 +4437,43 @@ static int pci_af_flr(struct pci_dev *dev, bool prob= e) return ret; } =20 +/** + * pci_do_d3hot_transition - Perform D3hot->D0 power state transition + * @dev: Device to transition + * + * Common helper to perform D3hot->D0 transition for PM-based reset method= s. + * Handles IOMMU preparation, state transition, and waiting for device rea= dy. + */ +static int pci_do_d3hot_transition(struct pci_dev *dev) +{ + u16 csr; + int ret; + + if (dev->current_state !=3D PCI_D0) + return -EINVAL; + + ret =3D pci_dev_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", ret); + return ret; + } + + pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); + csr &=3D ~PCI_PM_CTRL_STATE_MASK; + csr |=3D PCI_D3hot; + pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); + pci_dev_d3_sleep(dev); + + csr &=3D ~PCI_PM_CTRL_STATE_MASK; + csr |=3D PCI_D0; + pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); + pci_dev_d3_sleep(dev); + + ret =3D pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); + pci_dev_reset_iommu_done(dev); + return ret; +} + /** * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. * @dev: Device to reset. @@ -4455,7 +4492,6 @@ static int pci_af_flr(struct pci_dev *dev, bool probe) static int pci_pm_reset(struct pci_dev *dev, bool probe) { u16 csr; - int ret; =20 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) return -ENOTTY; @@ -4467,28 +4503,7 @@ static int pci_pm_reset(struct pci_dev *dev, bool pr= obe) if (probe) return 0; =20 - if (dev->current_state !=3D PCI_D0) - return -EINVAL; - - ret =3D pci_dev_reset_iommu_prepare(dev); - if (ret) { - pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", ret); - return ret; - } - - csr &=3D ~PCI_PM_CTRL_STATE_MASK; - csr |=3D PCI_D3hot; - pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); - pci_dev_d3_sleep(dev); - - csr &=3D ~PCI_PM_CTRL_STATE_MASK; - csr |=3D PCI_D0; - pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); - pci_dev_d3_sleep(dev); - - ret =3D pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); - pci_dev_reset_iommu_done(dev); - return ret; + return pci_do_d3hot_transition(dev); } =20 /** @@ -4530,6 +4545,42 @@ static int pci_d3cold_reset(struct pci_dev *dev, boo= l probe) return pci_set_power_state(dev, PCI_D0); } =20 +/** + * pci_soft_reset - Software-initiated reset via D3hot as last resort + * @dev: PCI device to reset + * @probe: if true, check if soft reset is supported; if false, perform re= set + * + * Attempt a software-initiated reset via D3hot->D0 transition as an absol= ute + * last resort when all other reset methods have failed. This method only + * becomes available if the device has PM capability, pci_pm_reset() is bl= ocked + * (typically by NoSoftRst+), and pci_d3cold_reset() is not available. + * + * Some devices incorrectly advertise NoSoftRst+ but D3hot transition does + * provide sufficient reset for certain use cases (e.g., VFIO passthrough). + * This method provides a "better than nothing" option when the device wou= ld + * otherwise have no reset capability. + * + * Returns 0 if device can be/was reset this way, -ENOTTY if a better reset + * method is available (pm or d3cold) or device lacks PM capability, or ot= her + * negative error code on failure. + */ +static int pci_soft_reset(struct pci_dev *dev, bool probe) +{ + if (pci_pm_reset(dev, true) =3D=3D 0) + return -ENOTTY; + + if (pci_d3cold_reset(dev, true) =3D=3D 0) + return -ENOTTY; + + if (!dev->pm_cap) + return -ENOTTY; + + if (probe) + return 0; + + return pci_do_d3hot_transition(dev); +} + /** * pcie_wait_for_link_status - Wait for link status change * @pdev: Device whose link to wait for. @@ -5105,6 +5156,7 @@ const struct pci_reset_fn_method pci_reset_fn_methods= [] =3D { { pci_reset_bus_function, .name =3D "bus" }, { cxl_reset_bus_function, .name =3D "cxl_bus" }, { pci_d3cold_reset, .name =3D "d3cold" }, + { pci_soft_reset, .name =3D "soft" }, }; =20 /** diff --git a/include/linux/pci.h b/include/linux/pci.h index 1ca7b880ead7..bcd2987b868b 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -51,7 +51,7 @@ PCI_STATUS_PARITY) =20 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */ -#define PCI_NUM_RESET_METHODS 9 +#define PCI_NUM_RESET_METHODS 10 =20 #define PCI_RESET_PROBE true #define PCI_RESET_DO_RESET false --=20 2.54.0 From nobody Mon May 25 05:12:26 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDEB843E9F9 for ; Mon, 18 May 2026 12:49:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779108546; cv=none; b=Q8IM2L79ityRIaVNJVi8fpCGjW3CQP9EoFJ1Rp3db7kHJGAmeWIHVXvI6m3ENjf0C2k/nOXAX1pDPO2L/duaLmUBkaCFpOihYHUknbBnEGXEoF5mCveQtRG8cDF9ZxJGCq45L/RYktZekczolluPEyfdWiHbVhcBFqHnh/KNIuE= ARC-Message-Signature: i=1; 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Mon, 18 May 2026 12:48:59 +0000 (UTC) Received: from fedora.redhat.com (unknown [10.44.32.67]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 15267196B09E; Mon, 18 May 2026 12:48:56 +0000 (UTC) From: Jose Ignacio Tornos Martinez To: bhelgaas@google.com, alex@shazbot.org Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Jose Ignacio Tornos Martinez Subject: [PATCH v4 3/3] PCI: Disable broken bus reset on Qualcomm devices Date: Mon, 18 May 2026 14:48:35 +0200 Message-ID: <20260518124836.460805-4-jtornosm@redhat.com> In-Reply-To: <20260518124836.460805-1-jtornosm@redhat.com> References: <20260518124836.460805-1-jtornosm@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Content-Type: text/plain; charset="utf-8" Some Qualcomm PCIe devices do not properly support Secondary Bus Reset (SBR). These devices have no FLR capability and advertise NoSoftRst+ (blocking PM reset), leaving bus reset as the only available method. However, bus reset does not work reliably for these devices. The problem manifests in VFIO passthrough scenarios with these affected devices: - ath11k WiFi (17cb:1103): Normal VM operation works fine, including clean shutdown/reboot. However, when the VM terminates uncleanly (crash, force-off), VFIO attempts to reset the device before it can be assigned to another VM. Without a working reset method, the device remains in an undefined state, preventing reuse. - ath12k WiFi (17cb:1107): Same behavior as ath11k. - SDX62/SDX65 5G modems (17cb:0308): Never successfully initialize even on first VM assignment without proper reset capability. Disable bus reset for these devices (following the pattern of other Atheros/Qualcomm devices) so alternative reset methods (d3cold or soft) are used instead, which provide working reset capability. Signed-off-by: Jose Ignacio Tornos Martinez --- v4: Quirk code unchanged from v3 v3: https://lore.kernel.org/all/20260513122349.268753-2-jtornosm@redhat.com/ drivers/pci/quirks.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 000000000000..111111111111 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3789,6 +3789,9 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003= 0, quirk_no_bus_reset); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset= ); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset= ); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset= ); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset= ); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset= ); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_QCOM, 0x1103, quirk_no_bus_reset); = /* ath11k */ +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_QCOM, 0x1107, quirk_no_bus_reset); = /* ath12k */ +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_QCOM, 0x0308, quirk_no_bus_reset); = /* SDX62/SDX65 */ /* * Root port on some Cavium CN8xxx chips do not successfully complete a bus -- 2.53.0