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Mon, 18 May 2026 04:40:25 -0700 From: Akhil R To: Laxman Dewangan , Dmitry Osipenko , Andi Shyti , Thierry Reding , Jonathan Hunter , "Kartik Rajput" , Wolfram Sang , , , CC: Akhil R Subject: [PATCH v2 1/4] i2c: tegra: use dmaengine_get_dma_device() for DMA buffer allocation Date: Mon, 18 May 2026 17:10:10 +0530 Message-ID: <20260518114013.62065-2-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260518114013.62065-1-akhilrajeev@nvidia.com> References: <20260518114013.62065-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009B:EE_|SA3PR12MB8000:EE_ X-MS-Office365-Filtering-Correlation-Id: f6fe8d07-9bba-4d93-e714-08deb4d24d7e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700016|921020|18002099003|22082099003|56012099003|11063799003; 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charset="utf-8" Use dmaengine_get_dma_device() to obtain the correct struct device pointer for dma_alloc_coherent() instead of directly dereferencing chan->device->dev. The dmaengine_get_dma_device() helper checks whether the DMA channel has a per-channel DMA device (chan->dev->chan_dma_dev) and returns it when available, falling back to the controller device otherwise. On platforms where the DMA controller sits behind an IOMMU with per-channel IOVA spaces (e.g. Tegra264 GPC DMA), the per-channel device carries the correct DMA mapping context. Using the controller device directly would allocate DMA buffers against the wrong IOMMU domain, leading to SMMU faults at runtime. On platforms without per-channel DMA devices the helper returns the same pointer as before, so there is no change in behavior for existing hardware. Assisted-by: Cursor:claude-4.6-opus Reviewed-by: Jon Hunter Signed-off-by: Akhil R --- drivers/i2c/busses/i2c-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 9fd5ade774a0..a21f6457d41b 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -712,7 +712,7 @@ static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c= _dev) goto err_out; } =20 - i2c_dev->dma_dev =3D i2c_dev->dma_chan->device->dev; + i2c_dev->dma_dev =3D dmaengine_get_dma_device(i2c_dev->dma_chan); i2c_dev->dma_buf_size =3D i2c_dev->hw->quirks->max_write_len + I2C_PACKET_HEADER_SIZE; =20 --=20 2.50.1 From nobody Mon May 25 05:12:28 2026 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012034.outbound.protection.outlook.com [40.93.195.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B0B434678E; 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charset="utf-8" Recent Tegra I2C controllers have a fairness arbitration register, which allows configuring the fair idle time required to support MCTP protocol over I2C. It is enabled by default, adding a per-transfer latency overhead that impacts non-MCTP I2C buses. Disable the fairness arbitration register during controller init for buses that are not MCTP controllers. Assisted-by: Cursor:claude-4.6-opus Reviewed-by: Jon Hunter Signed-off-by: Akhil R --- drivers/i2c/busses/i2c-tegra.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index a21f6457d41b..f96a118249b3 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -164,6 +164,7 @@ struct tegra_i2c_regs { unsigned int master_reset_cntrl; unsigned int mst_fifo_control; unsigned int mst_fifo_status; + unsigned int fairness_arb; unsigned int sw_mutex; }; =20 @@ -272,6 +273,7 @@ static const struct tegra_i2c_regs tegra264_i2c_regs = =3D { .master_reset_cntrl =3D 0x0a8, .mst_fifo_control =3D 0x0b4, .mst_fifo_status =3D 0x0b8, + .fairness_arb =3D 0x0e8, .sw_mutex =3D 0x0ec, }; =20 @@ -300,6 +302,7 @@ static const struct tegra_i2c_regs tegra410_i2c_regs = =3D { .master_reset_cntrl =3D 0x0ac, .mst_fifo_control =3D 0x0b8, .mst_fifo_status =3D 0x0bc, + .fairness_arb =3D 0x0ec, .sw_mutex =3D 0x0f0, }; =20 @@ -379,6 +382,7 @@ enum tegra_i2c_variant { * timing settings. * @enable_hs_mode_support: Enable support for high speed (HS) mode transf= ers. * @has_mutex: Has mutex register for mutual exclusion with other firmware= s or VMs. + * @has_fairarb_reg: Has fairness arbitration register for SMBUS/MCTP supp= ort. * @variant: This represents the I2C controller variant. * @regs: Register offsets for the specific SoC variant. */ @@ -412,6 +416,7 @@ struct tegra_i2c_hw_feature { bool has_interface_timing_reg; bool enable_hs_mode_support; bool has_mutex; + bool has_fairarb_reg; enum tegra_i2c_variant variant; const struct tegra_i2c_regs *regs; }; @@ -436,6 +441,7 @@ struct tegra_i2c_hw_feature { * @msg_read: indicates that the transfer is a read access * @timings: i2c timings information like bus frequency * @multimaster_mode: indicates that I2C controller is in multi-master mode + * @is_mctp: indicates that the I2C controller is used as an MCTP controll= er * @dma_chan: DMA channel * @dma_phys: handle to DMA resources * @dma_buf: pointer to allocated DMA buffer @@ -476,6 +482,7 @@ struct tegra_i2c_dev { void *dma_buf; =20 bool multimaster_mode; + bool is_mctp; bool atomic_mode; bool dma_mode; bool msg_read; @@ -914,6 +921,10 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_de= v) if (IS_VI(i2c_dev)) tegra_i2c_vi_init(i2c_dev); =20 + /* Disable fairness arbitration if not an MCTP controller */ + if (i2c_dev->hw->has_fairarb_reg && !i2c_dev->is_mctp) + i2c_writel(i2c_dev, 0, i2c_dev->hw->regs->fairness_arb); + if (i2c_dev->hw->enable_hs_mode_support) max_bus_freq_hz =3D I2C_MAX_HIGH_SPEED_MODE_FREQ; else @@ -1779,6 +1790,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_= hw =3D { .has_interface_timing_reg =3D false, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .has_fairarb_reg =3D false, .variant =3D TEGRA_I2C_VARIANT_DEFAULT, .regs =3D &tegra20_i2c_regs, }; @@ -1812,6 +1824,7 @@ static const struct tegra_i2c_hw_feature tegra20_dvc_= i2c_hw =3D { .has_interface_timing_reg =3D false, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .has_fairarb_reg =3D false, .variant =3D TEGRA_I2C_VARIANT_DVC, .regs =3D &tegra20_dvc_i2c_regs, }; @@ -1845,6 +1858,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_= hw =3D { .has_interface_timing_reg =3D false, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .has_fairarb_reg =3D false, .variant =3D TEGRA_I2C_VARIANT_DEFAULT, .regs =3D &tegra20_i2c_regs, }; @@ -1877,6 +1891,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c= _hw =3D { .has_interface_timing_reg =3D false, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .has_fairarb_reg =3D false, .variant =3D TEGRA_I2C_VARIANT_DEFAULT, .regs =3D &tegra20_i2c_regs, }; @@ -1909,6 +1924,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .has_fairarb_reg =3D false, .variant =3D TEGRA_I2C_VARIANT_DEFAULT, .regs =3D &tegra20_i2c_regs, }; @@ -1941,6 +1957,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .has_fairarb_reg =3D false, .variant =3D TEGRA_I2C_VARIANT_DEFAULT, .regs =3D &tegra20_i2c_regs, }; @@ -1974,6 +1991,7 @@ static const struct tegra_i2c_hw_feature tegra210_vi_= i2c_hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .has_fairarb_reg =3D false, .variant =3D TEGRA_I2C_VARIANT_VI, .regs =3D &tegra210_vi_i2c_regs, }; @@ -2007,6 +2025,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .has_fairarb_reg =3D false, .variant =3D TEGRA_I2C_VARIANT_DEFAULT, .regs =3D &tegra20_i2c_regs, }; @@ -2041,6 +2060,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D true, .has_mutex =3D false, + .has_fairarb_reg =3D false, .variant =3D TEGRA_I2C_VARIANT_DEFAULT, .regs =3D &tegra20_i2c_regs, }; @@ -2075,6 +2095,7 @@ static const struct tegra_i2c_hw_feature tegra256_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D true, .has_mutex =3D true, + .has_fairarb_reg =3D true, .variant =3D TEGRA_I2C_VARIANT_DEFAULT, .regs =3D &tegra264_i2c_regs, }; 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charset="utf-8" Update Tegra410 I2C timing parameters based on hardware characterization results. This adjusts the fast mode and HS mode settings to be compliant with the I2C specification. Fixes: 59717f260183 ("i2c: tegra: Add support for Tegra410") Reviewed-by: Jon Hunter Signed-off-by: Akhil R --- drivers/i2c/busses/i2c-tegra.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index f96a118249b3..93677bd2d3b1 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -2138,9 +2138,9 @@ static const struct tegra_i2c_hw_feature tegra264_i2c= _hw =3D { static const struct tegra_i2c_hw_feature tegra410_i2c_hw =3D { .has_continue_xfer_support =3D true, .has_per_pkt_xfer_complete_irq =3D true, - .clk_divisor_hs_mode =3D 1, + .clk_divisor_hs_mode =3D 2, .clk_divisor_std_mode =3D 0x3f, - .clk_divisor_fast_mode =3D 0x2c, + .clk_divisor_fast_mode =3D 0x2f, .clk_divisor_fast_plus_mode =3D 0x11, .has_config_load_reg =3D true, .has_multi_master_mode =3D true, @@ -2156,8 +2156,8 @@ static const struct tegra_i2c_hw_feature tegra410_i2c= _hw =3D { .thigh_fast_mode =3D 0x2, .tlow_fastplus_mode =3D 0x2, .thigh_fastplus_mode =3D 0x2, - .tlow_hs_mode =3D 0x8, - .thigh_hs_mode =3D 0x6, + .tlow_hs_mode =3D 0x5, + .thigh_hs_mode =3D 0x2, .setup_hold_time_std_mode =3D 0x08080808, .setup_hold_time_fast_mode =3D 0x02020202, .setup_hold_time_fastplus_mode =3D 0x02020202, --=20 2.50.1 From nobody Mon May 25 05:12:28 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012041.outbound.protection.outlook.com [52.101.43.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3DAE3F6C55; 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charset="utf-8" The Tegra I2C driver relies on runtime PM to wake up the controller before each transfer. However, runtime PM is disabled between the system suspend and NOIRQ suspend. If an I2C device initiates a transfer during this window, the I2C controller fails to wake up and the transfer fails. To handle this, the controller must be kept available for this period to allow transfers. Rework the I2C controller's system PM callbacks such that the controller is resumed from runtime suspend during system suspend and it stays RPM_ACTIVE throughout the suspend-resume cycle until it is runtime suspended back in the system resume. The clocks are disabled in NOIRQ suspend and enabled back in NOIRQ resume by calling the controller's runtime PM functions directly. Fixes: 8ebf15e9c869 ("i2c: tegra: Move suspend handling to NOIRQ phase") Assisted-by: Cursor:claude-4.6-opus Reviewed-by: Jon Hunter Signed-off-by: Akhil R --- drivers/i2c/busses/i2c-tegra.c | 53 +++++++++++++++++++--------------- 1 file changed, 30 insertions(+), 23 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 93677bd2d3b1..a24b6ef26dbe 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -2426,29 +2426,38 @@ static int __maybe_unused tegra_i2c_runtime_suspend= (struct device *dev) } =20 static int __maybe_unused tegra_i2c_suspend(struct device *dev) +{ + /* + * Bring the controller up and hold a usage count so it stays + * available until the noirq phase. + */ + return pm_runtime_resume_and_get(dev); +} + +static int __maybe_unused tegra_i2c_suspend_noirq(struct device *dev) { struct tegra_i2c_dev *i2c_dev =3D dev_get_drvdata(dev); - int err; =20 i2c_mark_adapter_suspended(&i2c_dev->adapter); =20 - if (!pm_runtime_status_suspended(dev)) { - err =3D tegra_i2c_runtime_suspend(dev); - if (err) - return err; - } - - return 0; + /* + * Runtime PM is already disabled at this point, so invoke the + * runtime_suspend callback directly to put the controller down. + */ + return tegra_i2c_runtime_suspend(dev); } =20 -static int __maybe_unused tegra_i2c_resume(struct device *dev) +static int __maybe_unused tegra_i2c_resume_noirq(struct device *dev) { struct tegra_i2c_dev *i2c_dev =3D dev_get_drvdata(dev); int err; =20 /* - * We need to ensure that clocks are enabled so that registers can be - * restored in tegra_i2c_init(). + * Runtime PM is still disabled at this point, so invoke the + * runtime_resume callback directly to bring the controller back up + * before re-initializing the hardware. The adapter is then marked + * resumed so that consumers can issue transfers from their own + * resume_noirq() handlers and onwards. */ err =3D tegra_i2c_runtime_resume(dev); if (err) @@ -2458,24 +2467,22 @@ static int __maybe_unused tegra_i2c_resume(struct d= evice *dev) if (err) return err; =20 - /* - * In case we are runtime suspended, disable clocks again so that we - * don't unbalance the clock reference counts during the next runtime - * resume transition. - */ - if (pm_runtime_status_suspended(dev)) { - err =3D tegra_i2c_runtime_suspend(dev); - if (err) - return err; - } - i2c_mark_adapter_resumed(&i2c_dev->adapter); =20 return 0; } =20 +static int __maybe_unused tegra_i2c_resume(struct device *dev) +{ + pm_runtime_put(dev); + + return 0; +} + static const struct dev_pm_ops tegra_i2c_pm =3D { - SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume) + SET_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume) + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend_noirq, + tegra_i2c_resume_noirq) SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume, NULL) }; --=20 2.50.1